Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

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config.ini (10451:3a87241adfb8)	config.ini (10736:4433fb00fa7d)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem
	26mmap_using_noreserve=false
26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=DerivO3CPU 48children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 49LFSTSize=1024 50LQEntries=32 51LSQCheckLoads=true 52LSQDepCheckShift=4 53SQEntries=32 54SSITSize=1024 55activity=0 56backComSize=5 57branchPred=system.cpu.branchPred 58cachePorts=200 59checker=Null 60clk_domain=system.cpu_clk_domain 61commitToDecodeDelay=1 62commitToFetchDelay=1 63commitToIEWDelay=1 64commitToRenameDelay=1 65commitWidth=8 66cpu_id=0 67decodeToFetchDelay=1 68decodeToRenameDelay=1 69decodeWidth=8 70dispatchWidth=8 71do_checkpoint_insts=true 72do_quiesce=true 73do_statistics_insts=true 74dtb=system.cpu.dtb 75eventq_index=0 76fetchBufferSize=64 77fetchQueueSize=32 78fetchToDecodeDelay=1 79fetchTrapLatency=1 80fetchWidth=8 81forwardComSize=5 82fuPool=system.cpu.fuPool 83function_trace=false 84function_trace_start=0 85iewToCommitDelay=1 86iewToDecodeDelay=1 87iewToFetchDelay=1 88iewToRenameDelay=1 89interrupts=system.cpu.interrupts 90isa=system.cpu.isa 91issueToExecuteDelay=1 92issueWidth=8 93itb=system.cpu.itb 94max_insts_all_threads=0 95max_insts_any_thread=0 96max_loads_all_threads=0 97max_loads_any_thread=0 98needsTSO=false 99numIQEntries=64 100numPhysCCRegs=0 101numPhysFloatRegs=256 102numPhysIntRegs=256 103numROBEntries=192 104numRobs=1 105numThreads=1 106profile=0 107progress_interval=0 108renameToDecodeDelay=1 109renameToFetchDelay=1 110renameToIEWDelay=2 111renameToROBDelay=1 112renameWidth=8 113simpoint_start_insts= 114smtCommitPolicy=RoundRobin 115smtFetchPolicy=SingleThread 116smtIQPolicy=Partitioned 117smtIQThreshold=100 118smtLSQPolicy=Partitioned 119smtLSQThreshold=100 120smtNumFetchingThreads=1 121smtROBPolicy=Partitioned 122smtROBThreshold=100 123socket_id=0 124squashWidth=8 125store_set_clear_period=250000 126switched_out=false 127system=system 128tracer=system.cpu.tracer 129trapLatency=13 130wbWidth=8 131workload=system.cpu.workload 132dcache_port=system.cpu.dcache.cpu_side 133icache_port=system.cpu.icache.cpu_side 134 135[system.cpu.branchPred] 136type=BranchPredictor 137BTBEntries=4096 138BTBTagSize=16 139RASSize=16 140choiceCtrBits=2 141choicePredictorSize=8192 142eventq_index=0 143globalCtrBits=2 144globalPredictorSize=8192 145instShiftAmt=2 146localCtrBits=2 147localHistoryTableSize=2048 148localPredictorSize=2048 149numThreads=1 150predType=tournament 151 152[system.cpu.dcache] 153type=BaseCache 154children=tags 155addr_ranges=0:18446744073709551615 156assoc=2 157clk_domain=system.cpu_clk_domain	27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=DerivO3CPU 49children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 50LFSTSize=1024 51LQEntries=32 52LSQCheckLoads=true 53LSQDepCheckShift=4 54SQEntries=32 55SSITSize=1024 56activity=0 57backComSize=5 58branchPred=system.cpu.branchPred 59cachePorts=200 60checker=Null 61clk_domain=system.cpu_clk_domain 62commitToDecodeDelay=1 63commitToFetchDelay=1 64commitToIEWDelay=1 65commitToRenameDelay=1 66commitWidth=8 67cpu_id=0 68decodeToFetchDelay=1 69decodeToRenameDelay=1 70decodeWidth=8 71dispatchWidth=8 72do_checkpoint_insts=true 73do_quiesce=true 74do_statistics_insts=true 75dtb=system.cpu.dtb 76eventq_index=0 77fetchBufferSize=64 78fetchQueueSize=32 79fetchToDecodeDelay=1 80fetchTrapLatency=1 81fetchWidth=8 82forwardComSize=5 83fuPool=system.cpu.fuPool 84function_trace=false 85function_trace_start=0 86iewToCommitDelay=1 87iewToDecodeDelay=1 88iewToFetchDelay=1 89iewToRenameDelay=1 90interrupts=system.cpu.interrupts 91isa=system.cpu.isa 92issueToExecuteDelay=1 93issueWidth=8 94itb=system.cpu.itb 95max_insts_all_threads=0 96max_insts_any_thread=0 97max_loads_all_threads=0 98max_loads_any_thread=0 99needsTSO=false 100numIQEntries=64 101numPhysCCRegs=0 102numPhysFloatRegs=256 103numPhysIntRegs=256 104numROBEntries=192 105numRobs=1 106numThreads=1 107profile=0 108progress_interval=0 109renameToDecodeDelay=1 110renameToFetchDelay=1 111renameToIEWDelay=2 112renameToROBDelay=1 113renameWidth=8 114simpoint_start_insts= 115smtCommitPolicy=RoundRobin 116smtFetchPolicy=SingleThread 117smtIQPolicy=Partitioned 118smtIQThreshold=100 119smtLSQPolicy=Partitioned 120smtLSQThreshold=100 121smtNumFetchingThreads=1 122smtROBPolicy=Partitioned 123smtROBThreshold=100 124socket_id=0 125squashWidth=8 126store_set_clear_period=250000 127switched_out=false 128system=system 129tracer=system.cpu.tracer 130trapLatency=13 131wbWidth=8 132workload=system.cpu.workload 133dcache_port=system.cpu.dcache.cpu_side 134icache_port=system.cpu.icache.cpu_side 135 136[system.cpu.branchPred] 137type=BranchPredictor 138BTBEntries=4096 139BTBTagSize=16 140RASSize=16 141choiceCtrBits=2 142choicePredictorSize=8192 143eventq_index=0 144globalCtrBits=2 145globalPredictorSize=8192 146instShiftAmt=2 147localCtrBits=2 148localHistoryTableSize=2048 149localPredictorSize=2048 150numThreads=1 151predType=tournament 152 153[system.cpu.dcache] 154type=BaseCache 155children=tags 156addr_ranges=0:18446744073709551615 157assoc=2 158clk_domain=system.cpu_clk_domain
	159demand_mshr_reserve=1
158eventq_index=0 159forward_snoops=true 160hit_latency=2 161is_top_level=true 162max_miss_count=0 163mshrs=4 164prefetch_on_access=false 165prefetcher=Null 166response_latency=2 167sequential_access=false 168size=262144 169system=system 170tags=system.cpu.dcache.tags 171tgts_per_mshr=20 172two_queue=false 173write_buffers=8 174cpu_side=system.cpu.dcache_port 175mem_side=system.cpu.toL2Bus.slave[1] 176 177[system.cpu.dcache.tags] 178type=LRU 179assoc=2 180block_size=64 181clk_domain=system.cpu_clk_domain 182eventq_index=0 183hit_latency=2 184sequential_access=false 185size=262144 186 187[system.cpu.dtb] 188type=MipsTLB 189eventq_index=0 190size=64 191 192[system.cpu.fuPool] 193type=FUPool 194children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 195FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 196eventq_index=0 197 198[system.cpu.fuPool.FUList0] 199type=FUDesc 200children=opList 201count=6 202eventq_index=0 203opList=system.cpu.fuPool.FUList0.opList 204 205[system.cpu.fuPool.FUList0.opList] 206type=OpDesc 207eventq_index=0 208issueLat=1 209opClass=IntAlu 210opLat=1 211 212[system.cpu.fuPool.FUList1] 213type=FUDesc 214children=opList0 opList1 215count=2 216eventq_index=0 217opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 218 219[system.cpu.fuPool.FUList1.opList0] 220type=OpDesc 221eventq_index=0 222issueLat=1 223opClass=IntMult 224opLat=3 225 226[system.cpu.fuPool.FUList1.opList1] 227type=OpDesc 228eventq_index=0 229issueLat=19 230opClass=IntDiv 231opLat=20 232 233[system.cpu.fuPool.FUList2] 234type=FUDesc 235children=opList0 opList1 opList2 236count=4 237eventq_index=0 238opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 239 240[system.cpu.fuPool.FUList2.opList0] 241type=OpDesc 242eventq_index=0 243issueLat=1 244opClass=FloatAdd 245opLat=2 246 247[system.cpu.fuPool.FUList2.opList1] 248type=OpDesc 249eventq_index=0 250issueLat=1 251opClass=FloatCmp 252opLat=2 253 254[system.cpu.fuPool.FUList2.opList2] 255type=OpDesc 256eventq_index=0 257issueLat=1 258opClass=FloatCvt 259opLat=2 260 261[system.cpu.fuPool.FUList3] 262type=FUDesc 263children=opList0 opList1 opList2 264count=2 265eventq_index=0 266opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 267 268[system.cpu.fuPool.FUList3.opList0] 269type=OpDesc 270eventq_index=0 271issueLat=1 272opClass=FloatMult 273opLat=4 274 275[system.cpu.fuPool.FUList3.opList1] 276type=OpDesc 277eventq_index=0 278issueLat=12 279opClass=FloatDiv 280opLat=12 281 282[system.cpu.fuPool.FUList3.opList2] 283type=OpDesc 284eventq_index=0 285issueLat=24 286opClass=FloatSqrt 287opLat=24 288 289[system.cpu.fuPool.FUList4] 290type=FUDesc 291children=opList 292count=0 293eventq_index=0 294opList=system.cpu.fuPool.FUList4.opList 295 296[system.cpu.fuPool.FUList4.opList] 297type=OpDesc 298eventq_index=0 299issueLat=1 300opClass=MemRead 301opLat=1 302 303[system.cpu.fuPool.FUList5] 304type=FUDesc 305children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 306count=4 307eventq_index=0 308opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 309 310[system.cpu.fuPool.FUList5.opList00] 311type=OpDesc 312eventq_index=0 313issueLat=1 314opClass=SimdAdd 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList01] 318type=OpDesc 319eventq_index=0 320issueLat=1 321opClass=SimdAddAcc 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList02] 325type=OpDesc 326eventq_index=0 327issueLat=1 328opClass=SimdAlu 329opLat=1 330 331[system.cpu.fuPool.FUList5.opList03] 332type=OpDesc 333eventq_index=0 334issueLat=1 335opClass=SimdCmp 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList04] 339type=OpDesc 340eventq_index=0 341issueLat=1 342opClass=SimdCvt 343opLat=1 344 345[system.cpu.fuPool.FUList5.opList05] 346type=OpDesc 347eventq_index=0 348issueLat=1 349opClass=SimdMisc 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList06] 353type=OpDesc 354eventq_index=0 355issueLat=1 356opClass=SimdMult 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList07] 360type=OpDesc 361eventq_index=0 362issueLat=1 363opClass=SimdMultAcc 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList08] 367type=OpDesc 368eventq_index=0 369issueLat=1 370opClass=SimdShift 371opLat=1 372 373[system.cpu.fuPool.FUList5.opList09] 374type=OpDesc 375eventq_index=0 376issueLat=1 377opClass=SimdShiftAcc 378opLat=1 379 380[system.cpu.fuPool.FUList5.opList10] 381type=OpDesc 382eventq_index=0 383issueLat=1 384opClass=SimdSqrt 385opLat=1 386 387[system.cpu.fuPool.FUList5.opList11] 388type=OpDesc 389eventq_index=0 390issueLat=1 391opClass=SimdFloatAdd 392opLat=1 393 394[system.cpu.fuPool.FUList5.opList12] 395type=OpDesc 396eventq_index=0 397issueLat=1 398opClass=SimdFloatAlu 399opLat=1 400 401[system.cpu.fuPool.FUList5.opList13] 402type=OpDesc 403eventq_index=0 404issueLat=1 405opClass=SimdFloatCmp 406opLat=1 407 408[system.cpu.fuPool.FUList5.opList14] 409type=OpDesc 410eventq_index=0 411issueLat=1 412opClass=SimdFloatCvt 413opLat=1 414 415[system.cpu.fuPool.FUList5.opList15] 416type=OpDesc 417eventq_index=0 418issueLat=1 419opClass=SimdFloatDiv 420opLat=1 421 422[system.cpu.fuPool.FUList5.opList16] 423type=OpDesc 424eventq_index=0 425issueLat=1 426opClass=SimdFloatMisc 427opLat=1 428 429[system.cpu.fuPool.FUList5.opList17] 430type=OpDesc 431eventq_index=0 432issueLat=1 433opClass=SimdFloatMult 434opLat=1 435 436[system.cpu.fuPool.FUList5.opList18] 437type=OpDesc 438eventq_index=0 439issueLat=1 440opClass=SimdFloatMultAcc 441opLat=1 442 443[system.cpu.fuPool.FUList5.opList19] 444type=OpDesc 445eventq_index=0 446issueLat=1 447opClass=SimdFloatSqrt 448opLat=1 449 450[system.cpu.fuPool.FUList6] 451type=FUDesc 452children=opList 453count=0 454eventq_index=0 455opList=system.cpu.fuPool.FUList6.opList 456 457[system.cpu.fuPool.FUList6.opList] 458type=OpDesc 459eventq_index=0 460issueLat=1 461opClass=MemWrite 462opLat=1 463 464[system.cpu.fuPool.FUList7] 465type=FUDesc 466children=opList0 opList1 467count=4 468eventq_index=0 469opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 470 471[system.cpu.fuPool.FUList7.opList0] 472type=OpDesc 473eventq_index=0 474issueLat=1 475opClass=MemRead 476opLat=1 477 478[system.cpu.fuPool.FUList7.opList1] 479type=OpDesc 480eventq_index=0 481issueLat=1 482opClass=MemWrite 483opLat=1 484 485[system.cpu.fuPool.FUList8] 486type=FUDesc 487children=opList 488count=1 489eventq_index=0 490opList=system.cpu.fuPool.FUList8.opList 491 492[system.cpu.fuPool.FUList8.opList] 493type=OpDesc 494eventq_index=0 495issueLat=3 496opClass=IprAccess 497opLat=3 498 499[system.cpu.icache] 500type=BaseCache 501children=tags 502addr_ranges=0:18446744073709551615 503assoc=2 504clk_domain=system.cpu_clk_domain	160eventq_index=0 161forward_snoops=true 162hit_latency=2 163is_top_level=true 164max_miss_count=0 165mshrs=4 166prefetch_on_access=false 167prefetcher=Null 168response_latency=2 169sequential_access=false 170size=262144 171system=system 172tags=system.cpu.dcache.tags 173tgts_per_mshr=20 174two_queue=false 175write_buffers=8 176cpu_side=system.cpu.dcache_port 177mem_side=system.cpu.toL2Bus.slave[1] 178 179[system.cpu.dcache.tags] 180type=LRU 181assoc=2 182block_size=64 183clk_domain=system.cpu_clk_domain 184eventq_index=0 185hit_latency=2 186sequential_access=false 187size=262144 188 189[system.cpu.dtb] 190type=MipsTLB 191eventq_index=0 192size=64 193 194[system.cpu.fuPool] 195type=FUPool 196children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 197FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 198eventq_index=0 199 200[system.cpu.fuPool.FUList0] 201type=FUDesc 202children=opList 203count=6 204eventq_index=0 205opList=system.cpu.fuPool.FUList0.opList 206 207[system.cpu.fuPool.FUList0.opList] 208type=OpDesc 209eventq_index=0 210issueLat=1 211opClass=IntAlu 212opLat=1 213 214[system.cpu.fuPool.FUList1] 215type=FUDesc 216children=opList0 opList1 217count=2 218eventq_index=0 219opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 220 221[system.cpu.fuPool.FUList1.opList0] 222type=OpDesc 223eventq_index=0 224issueLat=1 225opClass=IntMult 226opLat=3 227 228[system.cpu.fuPool.FUList1.opList1] 229type=OpDesc 230eventq_index=0 231issueLat=19 232opClass=IntDiv 233opLat=20 234 235[system.cpu.fuPool.FUList2] 236type=FUDesc 237children=opList0 opList1 opList2 238count=4 239eventq_index=0 240opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 241 242[system.cpu.fuPool.FUList2.opList0] 243type=OpDesc 244eventq_index=0 245issueLat=1 246opClass=FloatAdd 247opLat=2 248 249[system.cpu.fuPool.FUList2.opList1] 250type=OpDesc 251eventq_index=0 252issueLat=1 253opClass=FloatCmp 254opLat=2 255 256[system.cpu.fuPool.FUList2.opList2] 257type=OpDesc 258eventq_index=0 259issueLat=1 260opClass=FloatCvt 261opLat=2 262 263[system.cpu.fuPool.FUList3] 264type=FUDesc 265children=opList0 opList1 opList2 266count=2 267eventq_index=0 268opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 269 270[system.cpu.fuPool.FUList3.opList0] 271type=OpDesc 272eventq_index=0 273issueLat=1 274opClass=FloatMult 275opLat=4 276 277[system.cpu.fuPool.FUList3.opList1] 278type=OpDesc 279eventq_index=0 280issueLat=12 281opClass=FloatDiv 282opLat=12 283 284[system.cpu.fuPool.FUList3.opList2] 285type=OpDesc 286eventq_index=0 287issueLat=24 288opClass=FloatSqrt 289opLat=24 290 291[system.cpu.fuPool.FUList4] 292type=FUDesc 293children=opList 294count=0 295eventq_index=0 296opList=system.cpu.fuPool.FUList4.opList 297 298[system.cpu.fuPool.FUList4.opList] 299type=OpDesc 300eventq_index=0 301issueLat=1 302opClass=MemRead 303opLat=1 304 305[system.cpu.fuPool.FUList5] 306type=FUDesc 307children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 308count=4 309eventq_index=0 310opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 311 312[system.cpu.fuPool.FUList5.opList00] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=SimdAdd 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList01] 320type=OpDesc 321eventq_index=0 322issueLat=1 323opClass=SimdAddAcc 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList02] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdAlu 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList03] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdCmp 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList04] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdCvt 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList05] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdMisc 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList06] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdMult 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList07] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdMultAcc 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList08] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdShift 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList09] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdShiftAcc 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList10] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdSqrt 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList11] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdFloatAdd 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList12] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdFloatAlu 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList13] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatCmp 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList14] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatCvt 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList15] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatDiv 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList16] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatMisc 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList17] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatMult 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList18] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatMultAcc 443opLat=1 444 445[system.cpu.fuPool.FUList5.opList19] 446type=OpDesc 447eventq_index=0 448issueLat=1 449opClass=SimdFloatSqrt 450opLat=1 451 452[system.cpu.fuPool.FUList6] 453type=FUDesc 454children=opList 455count=0 456eventq_index=0 457opList=system.cpu.fuPool.FUList6.opList 458 459[system.cpu.fuPool.FUList6.opList] 460type=OpDesc 461eventq_index=0 462issueLat=1 463opClass=MemWrite 464opLat=1 465 466[system.cpu.fuPool.FUList7] 467type=FUDesc 468children=opList0 opList1 469count=4 470eventq_index=0 471opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 472 473[system.cpu.fuPool.FUList7.opList0] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemRead 478opLat=1 479 480[system.cpu.fuPool.FUList7.opList1] 481type=OpDesc 482eventq_index=0 483issueLat=1 484opClass=MemWrite 485opLat=1 486 487[system.cpu.fuPool.FUList8] 488type=FUDesc 489children=opList 490count=1 491eventq_index=0 492opList=system.cpu.fuPool.FUList8.opList 493 494[system.cpu.fuPool.FUList8.opList] 495type=OpDesc 496eventq_index=0 497issueLat=3 498opClass=IprAccess 499opLat=3 500 501[system.cpu.icache] 502type=BaseCache 503children=tags 504addr_ranges=0:18446744073709551615 505assoc=2 506clk_domain=system.cpu_clk_domain
	507demand_mshr_reserve=1
505eventq_index=0 506forward_snoops=true 507hit_latency=2 508is_top_level=true 509max_miss_count=0 510mshrs=4 511prefetch_on_access=false 512prefetcher=Null 513response_latency=2 514sequential_access=false 515size=131072 516system=system 517tags=system.cpu.icache.tags 518tgts_per_mshr=20 519two_queue=false 520write_buffers=8 521cpu_side=system.cpu.icache_port 522mem_side=system.cpu.toL2Bus.slave[0] 523 524[system.cpu.icache.tags] 525type=LRU 526assoc=2 527block_size=64 528clk_domain=system.cpu_clk_domain 529eventq_index=0 530hit_latency=2 531sequential_access=false 532size=131072 533 534[system.cpu.interrupts] 535type=MipsInterrupts 536eventq_index=0 537 538[system.cpu.isa] 539type=MipsISA 540eventq_index=0 541num_threads=1 542num_vpes=1 543system=system 544 545[system.cpu.itb] 546type=MipsTLB 547eventq_index=0 548size=64 549 550[system.cpu.l2cache] 551type=BaseCache 552children=tags 553addr_ranges=0:18446744073709551615 554assoc=8 555clk_domain=system.cpu_clk_domain	508eventq_index=0 509forward_snoops=true 510hit_latency=2 511is_top_level=true 512max_miss_count=0 513mshrs=4 514prefetch_on_access=false 515prefetcher=Null 516response_latency=2 517sequential_access=false 518size=131072 519system=system 520tags=system.cpu.icache.tags 521tgts_per_mshr=20 522two_queue=false 523write_buffers=8 524cpu_side=system.cpu.icache_port 525mem_side=system.cpu.toL2Bus.slave[0] 526 527[system.cpu.icache.tags] 528type=LRU 529assoc=2 530block_size=64 531clk_domain=system.cpu_clk_domain 532eventq_index=0 533hit_latency=2 534sequential_access=false 535size=131072 536 537[system.cpu.interrupts] 538type=MipsInterrupts 539eventq_index=0 540 541[system.cpu.isa] 542type=MipsISA 543eventq_index=0 544num_threads=1 545num_vpes=1 546system=system 547 548[system.cpu.itb] 549type=MipsTLB 550eventq_index=0 551size=64 552 553[system.cpu.l2cache] 554type=BaseCache 555children=tags 556addr_ranges=0:18446744073709551615 557assoc=8 558clk_domain=system.cpu_clk_domain
	559demand_mshr_reserve=1
556eventq_index=0 557forward_snoops=true 558hit_latency=20 559is_top_level=false 560max_miss_count=0 561mshrs=20 562prefetch_on_access=false 563prefetcher=Null 564response_latency=20 565sequential_access=false 566size=2097152 567system=system 568tags=system.cpu.l2cache.tags 569tgts_per_mshr=12 570two_queue=false 571write_buffers=8 572cpu_side=system.cpu.toL2Bus.master[0] 573mem_side=system.membus.slave[1] 574 575[system.cpu.l2cache.tags] 576type=LRU 577assoc=8 578block_size=64 579clk_domain=system.cpu_clk_domain 580eventq_index=0 581hit_latency=20 582sequential_access=false 583size=2097152 584 585[system.cpu.toL2Bus] 586type=CoherentXBar 587clk_domain=system.cpu_clk_domain 588eventq_index=0	560eventq_index=0 561forward_snoops=true 562hit_latency=20 563is_top_level=false 564max_miss_count=0 565mshrs=20 566prefetch_on_access=false 567prefetcher=Null 568response_latency=20 569sequential_access=false 570size=2097152 571system=system 572tags=system.cpu.l2cache.tags 573tgts_per_mshr=12 574two_queue=false 575write_buffers=8 576cpu_side=system.cpu.toL2Bus.master[0] 577mem_side=system.membus.slave[1] 578 579[system.cpu.l2cache.tags] 580type=LRU 581assoc=8 582block_size=64 583clk_domain=system.cpu_clk_domain 584eventq_index=0 585hit_latency=20 586sequential_access=false 587size=2097152 588 589[system.cpu.toL2Bus] 590type=CoherentXBar 591clk_domain=system.cpu_clk_domain 592eventq_index=0
589header_cycles=1	593forward_latency=0 594frontend_latency=1 595response_latency=1
590snoop_filter=Null	596snoop_filter=Null
	597snoop_response_latency=1
591system=system 592use_default_range=false 593width=32 594master=system.cpu.l2cache.cpu_side 595slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 596 597[system.cpu.tracer] 598type=ExeTracer 599eventq_index=0 600 601[system.cpu.workload] 602type=LiveProcess 603cmd=hello 604cwd=	598system=system 599use_default_range=false 600width=32 601master=system.cpu.l2cache.cpu_side 602slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 603 604[system.cpu.tracer] 605type=ExeTracer 606eventq_index=0 607 608[system.cpu.workload] 609type=LiveProcess 610cmd=hello 611cwd=
	612drivers=
605egid=100 606env= 607errout=cerr 608euid=100 609eventq_index=0 610executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello 611gid=100 612input=cin	613egid=100 614env= 615errout=cerr 616euid=100 617eventq_index=0 618executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello 619gid=100 620input=cin
	621kvmInSE=false
613max_stack_size=67108864 614output=cout 615pid=100 616ppid=99 617simpoint=0 618system=system 619uid=100 620useArchPT=false 621 622[system.cpu_clk_domain] 623type=SrcClockDomain 624clock=500 625domain_id=-1 626eventq_index=0 627init_perf_level=0 628voltage_domain=system.voltage_domain 629 630[system.dvfs_handler] 631type=DVFSHandler 632domains= 633enable=false 634eventq_index=0 635sys_clk_domain=system.clk_domain 636transition_latency=100000000 637 638[system.membus] 639type=CoherentXBar 640clk_domain=system.clk_domain 641eventq_index=0	622max_stack_size=67108864 623output=cout 624pid=100 625ppid=99 626simpoint=0 627system=system 628uid=100 629useArchPT=false 630 631[system.cpu_clk_domain] 632type=SrcClockDomain 633clock=500 634domain_id=-1 635eventq_index=0 636init_perf_level=0 637voltage_domain=system.voltage_domain 638 639[system.dvfs_handler] 640type=DVFSHandler 641domains= 642enable=false 643eventq_index=0 644sys_clk_domain=system.clk_domain 645transition_latency=100000000 646 647[system.membus] 648type=CoherentXBar 649clk_domain=system.clk_domain 650eventq_index=0
642header_cycles=1	651forward_latency=4 652frontend_latency=3 653response_latency=2
643snoop_filter=Null	654snoop_filter=Null
	655snoop_response_latency=4
644system=system 645use_default_range=false	656system=system 657use_default_range=false
646width=8	658width=16
647master=system.physmem.port 648slave=system.system_port system.cpu.l2cache.mem_side 649 650[system.physmem] 651type=DRAMCtrl 652IDD0=0.075000 653IDD02=0.000000 654IDD2N=0.050000 655IDD2N2=0.000000 656IDD2P0=0.000000 657IDD2P02=0.000000 658IDD2P1=0.000000 659IDD2P12=0.000000 660IDD3N=0.057000 661IDD3N2=0.000000 662IDD3P0=0.000000 663IDD3P02=0.000000 664IDD3P1=0.000000 665IDD3P12=0.000000 666IDD4R=0.187000 667IDD4R2=0.000000 668IDD4W=0.165000 669IDD4W2=0.000000 670IDD5=0.220000 671IDD52=0.000000 672IDD6=0.000000 673IDD62=0.000000 674VDD=1.500000 675VDD2=0.000000 676activation_limit=4	659master=system.physmem.port 660slave=system.system_port system.cpu.l2cache.mem_side 661 662[system.physmem] 663type=DRAMCtrl 664IDD0=0.075000 665IDD02=0.000000 666IDD2N=0.050000 667IDD2N2=0.000000 668IDD2P0=0.000000 669IDD2P02=0.000000 670IDD2P1=0.000000 671IDD2P12=0.000000 672IDD3N=0.057000 673IDD3N2=0.000000 674IDD3P0=0.000000 675IDD3P02=0.000000 676IDD3P1=0.000000 677IDD3P12=0.000000 678IDD4R=0.187000 679IDD4R2=0.000000 680IDD4W=0.165000 681IDD4W2=0.000000 682IDD5=0.220000 683IDD52=0.000000 684IDD6=0.000000 685IDD62=0.000000 686VDD=1.500000 687VDD2=0.000000 688activation_limit=4
677addr_mapping=RoRaBaChCo	689addr_mapping=RoRaBaCoCh
678bank_groups_per_rank=0 679banks_per_rank=8 680burst_length=8 681channels=1 682clk_domain=system.clk_domain 683conf_table_reported=true 684device_bus_width=8 685device_rowbuffer_size=1024	690bank_groups_per_rank=0 691banks_per_rank=8 692burst_length=8 693channels=1 694clk_domain=system.clk_domain 695conf_table_reported=true 696device_bus_width=8 697device_rowbuffer_size=1024
	698device_size=536870912
686devices_per_rank=8 687dll=true 688eventq_index=0 689in_addr_map=true 690max_accesses_per_row=16 691mem_sched_policy=frfcfs 692min_writes_per_switch=16 693null=false 694page_policy=open_adaptive 695range=0:134217727 696ranks_per_channel=2 697read_buffer_size=32 698static_backend_latency=10000 699static_frontend_latency=10000 700tBURST=5000 701tCCD_L=0 702tCK=1250 703tCL=13750 704tCS=2500 705tRAS=35000 706tRCD=13750 707tREFI=7800000 708tRFC=260000 709tRP=13750 710tRRD=6000 711tRRD_L=0 712tRTP=7500 713tRTW=2500 714tWR=15000 715tWTR=7500 716tXAW=30000 717tXP=0 718tXPDLL=0 719tXS=0 720tXSDLL=0 721write_buffer_size=64 722write_high_thresh_perc=85 723write_low_thresh_perc=50 724port=system.membus.master[0] 725 726[system.voltage_domain] 727type=VoltageDomain 728eventq_index=0 729voltage=1.000000 730	699devices_per_rank=8 700dll=true 701eventq_index=0 702in_addr_map=true 703max_accesses_per_row=16 704mem_sched_policy=frfcfs 705min_writes_per_switch=16 706null=false 707page_policy=open_adaptive 708range=0:134217727 709ranks_per_channel=2 710read_buffer_size=32 711static_backend_latency=10000 712static_frontend_latency=10000 713tBURST=5000 714tCCD_L=0 715tCK=1250 716tCL=13750 717tCS=2500 718tRAS=35000 719tRCD=13750 720tREFI=7800000 721tRFC=260000 722tRP=13750 723tRRD=6000 724tRRD_L=0 725tRTP=7500 726tRTW=2500 727tWR=15000 728tWTR=7500 729tXAW=30000 730tXP=0 731tXPDLL=0 732tXS=0 733tXSDLL=0 734write_buffer_size=64 735write_high_thresh_perc=85 736write_low_thresh_perc=50 737port=system.membus.master[0] 738 739[system.voltage_domain] 740type=VoltageDomain 741eventq_index=0 742voltage=1.000000 743