Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

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config.ini (10036:80e84beef3bb)	config.ini (10242:cb4e86c17767)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775
	21load_offset=0
21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 29work_begin_exit_count=0 30work_cpus_ckpt_count=0 31work_end_ckpt_count=0 32work_end_exit_count=0 33work_item_id=-1 34system_port=system.membus.slave[0] 35 36[system.clk_domain] 37type=SrcClockDomain 38clock=1000 39eventq_index=0 40voltage_domain=system.voltage_domain 41 42[system.cpu] 43type=DerivO3CPU 44children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 45LFSTSize=1024 46LQEntries=32 47LSQCheckLoads=true 48LSQDepCheckShift=4 49SQEntries=32 50SSITSize=1024 51activity=0 52backComSize=5 53branchPred=system.cpu.branchPred 54cachePorts=200 55checker=Null 56clk_domain=system.cpu_clk_domain 57commitToDecodeDelay=1 58commitToFetchDelay=1 59commitToIEWDelay=1 60commitToRenameDelay=1 61commitWidth=8 62cpu_id=0 63decodeToFetchDelay=1 64decodeToRenameDelay=1 65decodeWidth=8 66dispatchWidth=8 67do_checkpoint_insts=true 68do_quiesce=true 69do_statistics_insts=true 70dtb=system.cpu.dtb 71eventq_index=0 72fetchBufferSize=64 73fetchToDecodeDelay=1 74fetchTrapLatency=1 75fetchWidth=8 76forwardComSize=5 77fuPool=system.cpu.fuPool 78function_trace=false 79function_trace_start=0 80iewToCommitDelay=1 81iewToDecodeDelay=1 82iewToFetchDelay=1 83iewToRenameDelay=1 84interrupts=system.cpu.interrupts 85isa=system.cpu.isa 86issueToExecuteDelay=1 87issueWidth=8 88itb=system.cpu.itb 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysCCRegs=0 96numPhysFloatRegs=256 97numPhysIntRegs=256 98numROBEntries=192 99numRobs=1 100numThreads=1 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108simpoint_start_insts= 109smtCommitPolicy=RoundRobin 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100	22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 30work_begin_exit_count=0 31work_cpus_ckpt_count=0 32work_end_ckpt_count=0 33work_end_exit_count=0 34work_item_id=-1 35system_port=system.membus.slave[0] 36 37[system.clk_domain] 38type=SrcClockDomain 39clock=1000 40eventq_index=0 41voltage_domain=system.voltage_domain 42 43[system.cpu] 44type=DerivO3CPU 45children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 46LFSTSize=1024 47LQEntries=32 48LSQCheckLoads=true 49LSQDepCheckShift=4 50SQEntries=32 51SSITSize=1024 52activity=0 53backComSize=5 54branchPred=system.cpu.branchPred 55cachePorts=200 56checker=Null 57clk_domain=system.cpu_clk_domain 58commitToDecodeDelay=1 59commitToFetchDelay=1 60commitToIEWDelay=1 61commitToRenameDelay=1 62commitWidth=8 63cpu_id=0 64decodeToFetchDelay=1 65decodeToRenameDelay=1 66decodeWidth=8 67dispatchWidth=8 68do_checkpoint_insts=true 69do_quiesce=true 70do_statistics_insts=true 71dtb=system.cpu.dtb 72eventq_index=0 73fetchBufferSize=64 74fetchToDecodeDelay=1 75fetchTrapLatency=1 76fetchWidth=8 77forwardComSize=5 78fuPool=system.cpu.fuPool 79function_trace=false 80function_trace_start=0 81iewToCommitDelay=1 82iewToDecodeDelay=1 83iewToFetchDelay=1 84iewToRenameDelay=1 85interrupts=system.cpu.interrupts 86isa=system.cpu.isa 87issueToExecuteDelay=1 88issueWidth=8 89itb=system.cpu.itb 90max_insts_all_threads=0 91max_insts_any_thread=0 92max_loads_all_threads=0 93max_loads_any_thread=0 94needsTSO=false 95numIQEntries=64 96numPhysCCRegs=0 97numPhysFloatRegs=256 98numPhysIntRegs=256 99numROBEntries=192 100numRobs=1 101numThreads=1 102profile=0 103progress_interval=0 104renameToDecodeDelay=1 105renameToFetchDelay=1 106renameToIEWDelay=2 107renameToROBDelay=1 108renameWidth=8 109simpoint_start_insts= 110smtCommitPolicy=RoundRobin 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100
	119socket_id=0
118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 126workload=system.cpu.workload 127dcache_port=system.cpu.dcache.cpu_side 128icache_port=system.cpu.icache.cpu_side 129 130[system.cpu.branchPred] 131type=BranchPredictor 132BTBEntries=4096 133BTBTagSize=16 134RASSize=16 135choiceCtrBits=2 136choicePredictorSize=8192 137eventq_index=0 138globalCtrBits=2 139globalPredictorSize=8192 140instShiftAmt=2 141localCtrBits=2 142localHistoryTableSize=2048 143localPredictorSize=2048 144numThreads=1 145predType=tournament 146 147[system.cpu.dcache] 148type=BaseCache 149children=tags 150addr_ranges=0:18446744073709551615 151assoc=2 152clk_domain=system.cpu_clk_domain 153eventq_index=0 154forward_snoops=true 155hit_latency=2 156is_top_level=true 157max_miss_count=0 158mshrs=4 159prefetch_on_access=false 160prefetcher=Null 161response_latency=2 162sequential_access=false 163size=262144 164system=system 165tags=system.cpu.dcache.tags 166tgts_per_mshr=20 167two_queue=false 168write_buffers=8 169cpu_side=system.cpu.dcache_port 170mem_side=system.cpu.toL2Bus.slave[1] 171 172[system.cpu.dcache.tags] 173type=LRU 174assoc=2 175block_size=64 176clk_domain=system.cpu_clk_domain 177eventq_index=0 178hit_latency=2 179sequential_access=false 180size=262144 181 182[system.cpu.dtb] 183type=MipsTLB 184eventq_index=0 185size=64 186 187[system.cpu.fuPool] 188type=FUPool 189children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 190FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 191eventq_index=0 192 193[system.cpu.fuPool.FUList0] 194type=FUDesc 195children=opList 196count=6 197eventq_index=0 198opList=system.cpu.fuPool.FUList0.opList 199 200[system.cpu.fuPool.FUList0.opList] 201type=OpDesc 202eventq_index=0 203issueLat=1 204opClass=IntAlu 205opLat=1 206 207[system.cpu.fuPool.FUList1] 208type=FUDesc 209children=opList0 opList1 210count=2 211eventq_index=0 212opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 213 214[system.cpu.fuPool.FUList1.opList0] 215type=OpDesc 216eventq_index=0 217issueLat=1 218opClass=IntMult 219opLat=3 220 221[system.cpu.fuPool.FUList1.opList1] 222type=OpDesc 223eventq_index=0 224issueLat=19 225opClass=IntDiv 226opLat=20 227 228[system.cpu.fuPool.FUList2] 229type=FUDesc 230children=opList0 opList1 opList2 231count=4 232eventq_index=0 233opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 234 235[system.cpu.fuPool.FUList2.opList0] 236type=OpDesc 237eventq_index=0 238issueLat=1 239opClass=FloatAdd 240opLat=2 241 242[system.cpu.fuPool.FUList2.opList1] 243type=OpDesc 244eventq_index=0 245issueLat=1 246opClass=FloatCmp 247opLat=2 248 249[system.cpu.fuPool.FUList2.opList2] 250type=OpDesc 251eventq_index=0 252issueLat=1 253opClass=FloatCvt 254opLat=2 255 256[system.cpu.fuPool.FUList3] 257type=FUDesc 258children=opList0 opList1 opList2 259count=2 260eventq_index=0 261opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 262 263[system.cpu.fuPool.FUList3.opList0] 264type=OpDesc 265eventq_index=0 266issueLat=1 267opClass=FloatMult 268opLat=4 269 270[system.cpu.fuPool.FUList3.opList1] 271type=OpDesc 272eventq_index=0 273issueLat=12 274opClass=FloatDiv 275opLat=12 276 277[system.cpu.fuPool.FUList3.opList2] 278type=OpDesc 279eventq_index=0 280issueLat=24 281opClass=FloatSqrt 282opLat=24 283 284[system.cpu.fuPool.FUList4] 285type=FUDesc 286children=opList 287count=0 288eventq_index=0 289opList=system.cpu.fuPool.FUList4.opList 290 291[system.cpu.fuPool.FUList4.opList] 292type=OpDesc 293eventq_index=0 294issueLat=1 295opClass=MemRead 296opLat=1 297 298[system.cpu.fuPool.FUList5] 299type=FUDesc 300children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 301count=4 302eventq_index=0 303opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 304 305[system.cpu.fuPool.FUList5.opList00] 306type=OpDesc 307eventq_index=0 308issueLat=1 309opClass=SimdAdd 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList01] 313type=OpDesc 314eventq_index=0 315issueLat=1 316opClass=SimdAddAcc 317opLat=1 318 319[system.cpu.fuPool.FUList5.opList02] 320type=OpDesc 321eventq_index=0 322issueLat=1 323opClass=SimdAlu 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList03] 327type=OpDesc 328eventq_index=0 329issueLat=1 330opClass=SimdCmp 331opLat=1 332 333[system.cpu.fuPool.FUList5.opList04] 334type=OpDesc 335eventq_index=0 336issueLat=1 337opClass=SimdCvt 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList05] 341type=OpDesc 342eventq_index=0 343issueLat=1 344opClass=SimdMisc 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList06] 348type=OpDesc 349eventq_index=0 350issueLat=1 351opClass=SimdMult 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList07] 355type=OpDesc 356eventq_index=0 357issueLat=1 358opClass=SimdMultAcc 359opLat=1 360 361[system.cpu.fuPool.FUList5.opList08] 362type=OpDesc 363eventq_index=0 364issueLat=1 365opClass=SimdShift 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList09] 369type=OpDesc 370eventq_index=0 371issueLat=1 372opClass=SimdShiftAcc 373opLat=1 374 375[system.cpu.fuPool.FUList5.opList10] 376type=OpDesc 377eventq_index=0 378issueLat=1 379opClass=SimdSqrt 380opLat=1 381 382[system.cpu.fuPool.FUList5.opList11] 383type=OpDesc 384eventq_index=0 385issueLat=1 386opClass=SimdFloatAdd 387opLat=1 388 389[system.cpu.fuPool.FUList5.opList12] 390type=OpDesc 391eventq_index=0 392issueLat=1 393opClass=SimdFloatAlu 394opLat=1 395 396[system.cpu.fuPool.FUList5.opList13] 397type=OpDesc 398eventq_index=0 399issueLat=1 400opClass=SimdFloatCmp 401opLat=1 402 403[system.cpu.fuPool.FUList5.opList14] 404type=OpDesc 405eventq_index=0 406issueLat=1 407opClass=SimdFloatCvt 408opLat=1 409 410[system.cpu.fuPool.FUList5.opList15] 411type=OpDesc 412eventq_index=0 413issueLat=1 414opClass=SimdFloatDiv 415opLat=1 416 417[system.cpu.fuPool.FUList5.opList16] 418type=OpDesc 419eventq_index=0 420issueLat=1 421opClass=SimdFloatMisc 422opLat=1 423 424[system.cpu.fuPool.FUList5.opList17] 425type=OpDesc 426eventq_index=0 427issueLat=1 428opClass=SimdFloatMult 429opLat=1 430 431[system.cpu.fuPool.FUList5.opList18] 432type=OpDesc 433eventq_index=0 434issueLat=1 435opClass=SimdFloatMultAcc 436opLat=1 437 438[system.cpu.fuPool.FUList5.opList19] 439type=OpDesc 440eventq_index=0 441issueLat=1 442opClass=SimdFloatSqrt 443opLat=1 444 445[system.cpu.fuPool.FUList6] 446type=FUDesc 447children=opList 448count=0 449eventq_index=0 450opList=system.cpu.fuPool.FUList6.opList 451 452[system.cpu.fuPool.FUList6.opList] 453type=OpDesc 454eventq_index=0 455issueLat=1 456opClass=MemWrite 457opLat=1 458 459[system.cpu.fuPool.FUList7] 460type=FUDesc 461children=opList0 opList1 462count=4 463eventq_index=0 464opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 465 466[system.cpu.fuPool.FUList7.opList0] 467type=OpDesc 468eventq_index=0 469issueLat=1 470opClass=MemRead 471opLat=1 472 473[system.cpu.fuPool.FUList7.opList1] 474type=OpDesc 475eventq_index=0 476issueLat=1 477opClass=MemWrite 478opLat=1 479 480[system.cpu.fuPool.FUList8] 481type=FUDesc 482children=opList 483count=1 484eventq_index=0 485opList=system.cpu.fuPool.FUList8.opList 486 487[system.cpu.fuPool.FUList8.opList] 488type=OpDesc 489eventq_index=0 490issueLat=3 491opClass=IprAccess 492opLat=3 493 494[system.cpu.icache] 495type=BaseCache 496children=tags 497addr_ranges=0:18446744073709551615 498assoc=2 499clk_domain=system.cpu_clk_domain 500eventq_index=0 501forward_snoops=true 502hit_latency=2 503is_top_level=true 504max_miss_count=0 505mshrs=4 506prefetch_on_access=false 507prefetcher=Null 508response_latency=2 509sequential_access=false 510size=131072 511system=system 512tags=system.cpu.icache.tags 513tgts_per_mshr=20 514two_queue=false 515write_buffers=8 516cpu_side=system.cpu.icache_port 517mem_side=system.cpu.toL2Bus.slave[0] 518 519[system.cpu.icache.tags] 520type=LRU 521assoc=2 522block_size=64 523clk_domain=system.cpu_clk_domain 524eventq_index=0 525hit_latency=2 526sequential_access=false 527size=131072 528 529[system.cpu.interrupts] 530type=MipsInterrupts 531eventq_index=0 532 533[system.cpu.isa] 534type=MipsISA 535eventq_index=0 536num_threads=1 537num_vpes=1 538system=system 539 540[system.cpu.itb] 541type=MipsTLB 542eventq_index=0 543size=64 544 545[system.cpu.l2cache] 546type=BaseCache 547children=tags 548addr_ranges=0:18446744073709551615 549assoc=8 550clk_domain=system.cpu_clk_domain 551eventq_index=0 552forward_snoops=true 553hit_latency=20 554is_top_level=false 555max_miss_count=0 556mshrs=20 557prefetch_on_access=false 558prefetcher=Null 559response_latency=20 560sequential_access=false 561size=2097152 562system=system 563tags=system.cpu.l2cache.tags 564tgts_per_mshr=12 565two_queue=false 566write_buffers=8 567cpu_side=system.cpu.toL2Bus.master[0] 568mem_side=system.membus.slave[1] 569 570[system.cpu.l2cache.tags] 571type=LRU 572assoc=8 573block_size=64 574clk_domain=system.cpu_clk_domain 575eventq_index=0 576hit_latency=20 577sequential_access=false 578size=2097152 579 580[system.cpu.toL2Bus] 581type=CoherentBus 582clk_domain=system.cpu_clk_domain 583eventq_index=0 584header_cycles=1 585system=system 586use_default_range=false 587width=32 588master=system.cpu.l2cache.cpu_side 589slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 590 591[system.cpu.tracer] 592type=ExeTracer 593eventq_index=0 594 595[system.cpu.workload] 596type=LiveProcess 597cmd=hello 598cwd= 599egid=100 600env= 601errout=cerr 602euid=100 603eventq_index=0	120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 128workload=system.cpu.workload 129dcache_port=system.cpu.dcache.cpu_side 130icache_port=system.cpu.icache.cpu_side 131 132[system.cpu.branchPred] 133type=BranchPredictor 134BTBEntries=4096 135BTBTagSize=16 136RASSize=16 137choiceCtrBits=2 138choicePredictorSize=8192 139eventq_index=0 140globalCtrBits=2 141globalPredictorSize=8192 142instShiftAmt=2 143localCtrBits=2 144localHistoryTableSize=2048 145localPredictorSize=2048 146numThreads=1 147predType=tournament 148 149[system.cpu.dcache] 150type=BaseCache 151children=tags 152addr_ranges=0:18446744073709551615 153assoc=2 154clk_domain=system.cpu_clk_domain 155eventq_index=0 156forward_snoops=true 157hit_latency=2 158is_top_level=true 159max_miss_count=0 160mshrs=4 161prefetch_on_access=false 162prefetcher=Null 163response_latency=2 164sequential_access=false 165size=262144 166system=system 167tags=system.cpu.dcache.tags 168tgts_per_mshr=20 169two_queue=false 170write_buffers=8 171cpu_side=system.cpu.dcache_port 172mem_side=system.cpu.toL2Bus.slave[1] 173 174[system.cpu.dcache.tags] 175type=LRU 176assoc=2 177block_size=64 178clk_domain=system.cpu_clk_domain 179eventq_index=0 180hit_latency=2 181sequential_access=false 182size=262144 183 184[system.cpu.dtb] 185type=MipsTLB 186eventq_index=0 187size=64 188 189[system.cpu.fuPool] 190type=FUPool 191children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 192FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 193eventq_index=0 194 195[system.cpu.fuPool.FUList0] 196type=FUDesc 197children=opList 198count=6 199eventq_index=0 200opList=system.cpu.fuPool.FUList0.opList 201 202[system.cpu.fuPool.FUList0.opList] 203type=OpDesc 204eventq_index=0 205issueLat=1 206opClass=IntAlu 207opLat=1 208 209[system.cpu.fuPool.FUList1] 210type=FUDesc 211children=opList0 opList1 212count=2 213eventq_index=0 214opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 215 216[system.cpu.fuPool.FUList1.opList0] 217type=OpDesc 218eventq_index=0 219issueLat=1 220opClass=IntMult 221opLat=3 222 223[system.cpu.fuPool.FUList1.opList1] 224type=OpDesc 225eventq_index=0 226issueLat=19 227opClass=IntDiv 228opLat=20 229 230[system.cpu.fuPool.FUList2] 231type=FUDesc 232children=opList0 opList1 opList2 233count=4 234eventq_index=0 235opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 236 237[system.cpu.fuPool.FUList2.opList0] 238type=OpDesc 239eventq_index=0 240issueLat=1 241opClass=FloatAdd 242opLat=2 243 244[system.cpu.fuPool.FUList2.opList1] 245type=OpDesc 246eventq_index=0 247issueLat=1 248opClass=FloatCmp 249opLat=2 250 251[system.cpu.fuPool.FUList2.opList2] 252type=OpDesc 253eventq_index=0 254issueLat=1 255opClass=FloatCvt 256opLat=2 257 258[system.cpu.fuPool.FUList3] 259type=FUDesc 260children=opList0 opList1 opList2 261count=2 262eventq_index=0 263opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 264 265[system.cpu.fuPool.FUList3.opList0] 266type=OpDesc 267eventq_index=0 268issueLat=1 269opClass=FloatMult 270opLat=4 271 272[system.cpu.fuPool.FUList3.opList1] 273type=OpDesc 274eventq_index=0 275issueLat=12 276opClass=FloatDiv 277opLat=12 278 279[system.cpu.fuPool.FUList3.opList2] 280type=OpDesc 281eventq_index=0 282issueLat=24 283opClass=FloatSqrt 284opLat=24 285 286[system.cpu.fuPool.FUList4] 287type=FUDesc 288children=opList 289count=0 290eventq_index=0 291opList=system.cpu.fuPool.FUList4.opList 292 293[system.cpu.fuPool.FUList4.opList] 294type=OpDesc 295eventq_index=0 296issueLat=1 297opClass=MemRead 298opLat=1 299 300[system.cpu.fuPool.FUList5] 301type=FUDesc 302children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 303count=4 304eventq_index=0 305opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 306 307[system.cpu.fuPool.FUList5.opList00] 308type=OpDesc 309eventq_index=0 310issueLat=1 311opClass=SimdAdd 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList01] 315type=OpDesc 316eventq_index=0 317issueLat=1 318opClass=SimdAddAcc 319opLat=1 320 321[system.cpu.fuPool.FUList5.opList02] 322type=OpDesc 323eventq_index=0 324issueLat=1 325opClass=SimdAlu 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList03] 329type=OpDesc 330eventq_index=0 331issueLat=1 332opClass=SimdCmp 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList04] 336type=OpDesc 337eventq_index=0 338issueLat=1 339opClass=SimdCvt 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList05] 343type=OpDesc 344eventq_index=0 345issueLat=1 346opClass=SimdMisc 347opLat=1 348 349[system.cpu.fuPool.FUList5.opList06] 350type=OpDesc 351eventq_index=0 352issueLat=1 353opClass=SimdMult 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList07] 357type=OpDesc 358eventq_index=0 359issueLat=1 360opClass=SimdMultAcc 361opLat=1 362 363[system.cpu.fuPool.FUList5.opList08] 364type=OpDesc 365eventq_index=0 366issueLat=1 367opClass=SimdShift 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList09] 371type=OpDesc 372eventq_index=0 373issueLat=1 374opClass=SimdShiftAcc 375opLat=1 376 377[system.cpu.fuPool.FUList5.opList10] 378type=OpDesc 379eventq_index=0 380issueLat=1 381opClass=SimdSqrt 382opLat=1 383 384[system.cpu.fuPool.FUList5.opList11] 385type=OpDesc 386eventq_index=0 387issueLat=1 388opClass=SimdFloatAdd 389opLat=1 390 391[system.cpu.fuPool.FUList5.opList12] 392type=OpDesc 393eventq_index=0 394issueLat=1 395opClass=SimdFloatAlu 396opLat=1 397 398[system.cpu.fuPool.FUList5.opList13] 399type=OpDesc 400eventq_index=0 401issueLat=1 402opClass=SimdFloatCmp 403opLat=1 404 405[system.cpu.fuPool.FUList5.opList14] 406type=OpDesc 407eventq_index=0 408issueLat=1 409opClass=SimdFloatCvt 410opLat=1 411 412[system.cpu.fuPool.FUList5.opList15] 413type=OpDesc 414eventq_index=0 415issueLat=1 416opClass=SimdFloatDiv 417opLat=1 418 419[system.cpu.fuPool.FUList5.opList16] 420type=OpDesc 421eventq_index=0 422issueLat=1 423opClass=SimdFloatMisc 424opLat=1 425 426[system.cpu.fuPool.FUList5.opList17] 427type=OpDesc 428eventq_index=0 429issueLat=1 430opClass=SimdFloatMult 431opLat=1 432 433[system.cpu.fuPool.FUList5.opList18] 434type=OpDesc 435eventq_index=0 436issueLat=1 437opClass=SimdFloatMultAcc 438opLat=1 439 440[system.cpu.fuPool.FUList5.opList19] 441type=OpDesc 442eventq_index=0 443issueLat=1 444opClass=SimdFloatSqrt 445opLat=1 446 447[system.cpu.fuPool.FUList6] 448type=FUDesc 449children=opList 450count=0 451eventq_index=0 452opList=system.cpu.fuPool.FUList6.opList 453 454[system.cpu.fuPool.FUList6.opList] 455type=OpDesc 456eventq_index=0 457issueLat=1 458opClass=MemWrite 459opLat=1 460 461[system.cpu.fuPool.FUList7] 462type=FUDesc 463children=opList0 opList1 464count=4 465eventq_index=0 466opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 467 468[system.cpu.fuPool.FUList7.opList0] 469type=OpDesc 470eventq_index=0 471issueLat=1 472opClass=MemRead 473opLat=1 474 475[system.cpu.fuPool.FUList7.opList1] 476type=OpDesc 477eventq_index=0 478issueLat=1 479opClass=MemWrite 480opLat=1 481 482[system.cpu.fuPool.FUList8] 483type=FUDesc 484children=opList 485count=1 486eventq_index=0 487opList=system.cpu.fuPool.FUList8.opList 488 489[system.cpu.fuPool.FUList8.opList] 490type=OpDesc 491eventq_index=0 492issueLat=3 493opClass=IprAccess 494opLat=3 495 496[system.cpu.icache] 497type=BaseCache 498children=tags 499addr_ranges=0:18446744073709551615 500assoc=2 501clk_domain=system.cpu_clk_domain 502eventq_index=0 503forward_snoops=true 504hit_latency=2 505is_top_level=true 506max_miss_count=0 507mshrs=4 508prefetch_on_access=false 509prefetcher=Null 510response_latency=2 511sequential_access=false 512size=131072 513system=system 514tags=system.cpu.icache.tags 515tgts_per_mshr=20 516two_queue=false 517write_buffers=8 518cpu_side=system.cpu.icache_port 519mem_side=system.cpu.toL2Bus.slave[0] 520 521[system.cpu.icache.tags] 522type=LRU 523assoc=2 524block_size=64 525clk_domain=system.cpu_clk_domain 526eventq_index=0 527hit_latency=2 528sequential_access=false 529size=131072 530 531[system.cpu.interrupts] 532type=MipsInterrupts 533eventq_index=0 534 535[system.cpu.isa] 536type=MipsISA 537eventq_index=0 538num_threads=1 539num_vpes=1 540system=system 541 542[system.cpu.itb] 543type=MipsTLB 544eventq_index=0 545size=64 546 547[system.cpu.l2cache] 548type=BaseCache 549children=tags 550addr_ranges=0:18446744073709551615 551assoc=8 552clk_domain=system.cpu_clk_domain 553eventq_index=0 554forward_snoops=true 555hit_latency=20 556is_top_level=false 557max_miss_count=0 558mshrs=20 559prefetch_on_access=false 560prefetcher=Null 561response_latency=20 562sequential_access=false 563size=2097152 564system=system 565tags=system.cpu.l2cache.tags 566tgts_per_mshr=12 567two_queue=false 568write_buffers=8 569cpu_side=system.cpu.toL2Bus.master[0] 570mem_side=system.membus.slave[1] 571 572[system.cpu.l2cache.tags] 573type=LRU 574assoc=8 575block_size=64 576clk_domain=system.cpu_clk_domain 577eventq_index=0 578hit_latency=20 579sequential_access=false 580size=2097152 581 582[system.cpu.toL2Bus] 583type=CoherentBus 584clk_domain=system.cpu_clk_domain 585eventq_index=0 586header_cycles=1 587system=system 588use_default_range=false 589width=32 590master=system.cpu.l2cache.cpu_side 591slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 592 593[system.cpu.tracer] 594type=ExeTracer 595eventq_index=0 596 597[system.cpu.workload] 598type=LiveProcess 599cmd=hello 600cwd= 601egid=100 602env= 603errout=cerr 604euid=100 605eventq_index=0
604executable=/dist/test-progs/hello/bin/mips/linux/hello	606executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
605gid=100 606input=cin 607max_stack_size=67108864 608output=cout 609pid=100 610ppid=99 611simpoint=0 612system=system 613uid=100 614 615[system.cpu_clk_domain] 616type=SrcClockDomain 617clock=500 618eventq_index=0 619voltage_domain=system.voltage_domain 620 621[system.membus] 622type=CoherentBus 623clk_domain=system.clk_domain 624eventq_index=0 625header_cycles=1 626system=system 627use_default_range=false 628width=8 629master=system.physmem.port 630slave=system.system_port system.cpu.l2cache.mem_side 631 632[system.physmem]	607gid=100 608input=cin 609max_stack_size=67108864 610output=cout 611pid=100 612ppid=99 613simpoint=0 614system=system 615uid=100 616 617[system.cpu_clk_domain] 618type=SrcClockDomain 619clock=500 620eventq_index=0 621voltage_domain=system.voltage_domain 622 623[system.membus] 624type=CoherentBus 625clk_domain=system.clk_domain 626eventq_index=0 627header_cycles=1 628system=system 629use_default_range=false 630width=8 631master=system.physmem.port 632slave=system.system_port system.cpu.l2cache.mem_side 633 634[system.physmem]
633type=SimpleDRAM	635type=DRAMCtrl
634activation_limit=4	636activation_limit=4
635addr_mapping=RaBaChCo	637addr_mapping=RoRaBaChCo
636banks_per_rank=8 637burst_length=8 638channels=1 639clk_domain=system.clk_domain 640conf_table_reported=true 641device_bus_width=8 642device_rowbuffer_size=1024 643devices_per_rank=8 644eventq_index=0 645in_addr_map=true	638banks_per_rank=8 639burst_length=8 640channels=1 641clk_domain=system.clk_domain 642conf_table_reported=true 643device_bus_width=8 644device_rowbuffer_size=1024 645devices_per_rank=8 646eventq_index=0 647in_addr_map=true
	648max_accesses_per_row=16
646mem_sched_policy=frfcfs	649mem_sched_policy=frfcfs
	650min_writes_per_switch=16
647null=false	651null=false
648page_policy=open	652page_policy=open_adaptive
649range=0:134217727 650ranks_per_channel=2 651read_buffer_size=32 652static_backend_latency=10000 653static_frontend_latency=10000 654tBURST=5000	653range=0:134217727 654ranks_per_channel=2 655read_buffer_size=32 656static_backend_latency=10000 657static_frontend_latency=10000 658tBURST=5000
	659tCK=1250
655tCL=13750 656tRAS=35000 657tRCD=13750 658tREFI=7800000	660tCL=13750 661tRAS=35000 662tRCD=13750 663tREFI=7800000
659tRFC=300000	664tRFC=260000
660tRP=13750	665tRP=13750
661tRRD=6250	666tRRD=6000 667tRTP=7500 668tRTW=2500 669tWR=15000
662tWTR=7500	670tWTR=7500
663tXAW=40000 664write_buffer_size=32 665write_high_thresh_perc=70 666write_low_thresh_perc=0	671tXAW=30000 672write_buffer_size=64 673write_high_thresh_perc=85 674write_low_thresh_perc=50
667port=system.membus.master[0] 668 669[system.voltage_domain] 670type=VoltageDomain 671eventq_index=0 672voltage=1.000000 673	675port=system.membus.master[0] 676 677[system.voltage_domain] 678type=VoltageDomain 679eventq_index=0 680voltage=1.000000 681