1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=cpu membus physmem
12boot_osflags=a
13clock=1000
14init_param=0
15kernel=
16load_addr_mask=1099511627775
17mem_mode=atomic
18memories=system.physmem
19num_work_ids=16
20readfile=
21symbolfile=
22work_begin_ckpt_count=0
23work_begin_cpu_id_exit=-1
24work_begin_exit_count=0
25work_cpus_ckpt_count=0
26work_end_ckpt_count=0
27work_end_exit_count=0
28work_item_id=-1
29system_port=system.membus.slave[0]
30
31[system.cpu]
32type=DerivO3CPU
33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
34BTBEntries=4096
35BTBTagSize=16
36LFSTSize=1024
37LQEntries=32
38LSQCheckLoads=true
39LSQDepCheckShift=4
40RASSize=16
41SQEntries=32
42SSITSize=1024
43activity=0
44backComSize=5
45cachePorts=200
46checker=Null
47choiceCtrBits=2
48choicePredictorSize=8192
49clock=500
50commitToDecodeDelay=1
51commitToFetchDelay=1
52commitToIEWDelay=1
53commitToRenameDelay=1
54commitWidth=8
55cpu_id=0
56decodeToFetchDelay=1
57decodeToRenameDelay=1
58decodeWidth=8
59defer_registration=false
60dispatchWidth=8
61do_checkpoint_insts=true
62do_quiesce=true
63do_statistics_insts=true
64dtb=system.cpu.dtb
65fetchToDecodeDelay=1
66fetchTrapLatency=1
67fetchWidth=8
68forwardComSize=5
69fuPool=system.cpu.fuPool
70function_trace=false
71function_trace_start=0
72globalCtrBits=2
73globalHistoryBits=13
74globalPredictorSize=8192
75iewToCommitDelay=1
76iewToDecodeDelay=1
77iewToFetchDelay=1
78iewToRenameDelay=1
79instShiftAmt=2
80interrupts=system.cpu.interrupts
81isa=system.cpu.isa
82issueToExecuteDelay=1
83issueWidth=8
84itb=system.cpu.itb
85localCtrBits=2
86localHistoryBits=11
87localHistoryTableSize=2048
88localPredictorSize=2048
89max_insts_all_threads=0
90max_insts_any_thread=0
91max_loads_all_threads=0
92max_loads_any_thread=0
93needsTSO=false
94numIQEntries=64
95numPhysFloatRegs=256
96numPhysIntRegs=256
97numROBEntries=192
98numRobs=1
99numThreads=1
100predType=tournament
101profile=0
102progress_interval=0
103renameToDecodeDelay=1
104renameToFetchDelay=1
105renameToIEWDelay=2
106renameToROBDelay=1
107renameWidth=8
108smtCommitPolicy=RoundRobin
109smtFetchPolicy=SingleThread
110smtIQPolicy=Partitioned
111smtIQThreshold=100
112smtLSQPolicy=Partitioned
113smtLSQThreshold=100
114smtNumFetchingThreads=1
115smtROBPolicy=Partitioned
116smtROBThreshold=100
117squashWidth=8
118store_set_clear_period=250000
119system=system
120tracer=system.cpu.tracer
121trapLatency=13
122wbDepth=1
123wbWidth=8
124workload=system.cpu.workload
125dcache_port=system.cpu.dcache.cpu_side
126icache_port=system.cpu.icache.cpu_side
127
128[system.cpu.dcache]
129type=BaseCache
130addr_ranges=0:18446744073709551615
131assoc=2
132block_size=64
133clock=500
134forward_snoops=true
135hash_delay=1
136hit_latency=2
137is_top_level=true
138max_miss_count=0
139mshrs=4
140prefetch_on_access=false
141prefetcher=Null
142prioritizeRequests=false
143repl=Null
144response_latency=2
145size=262144
146subblock_size=0
147system=system
148tgts_per_mshr=20
149trace_addr=0
150two_queue=false
151write_buffers=8
152cpu_side=system.cpu.dcache_port
153mem_side=system.cpu.toL2Bus.slave[1]
154
155[system.cpu.dtb]
156type=MipsTLB
157size=64
158
159[system.cpu.fuPool]
160type=FUPool
161children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
162FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
163
164[system.cpu.fuPool.FUList0]
165type=FUDesc
166children=opList
167count=6
168opList=system.cpu.fuPool.FUList0.opList
169
170[system.cpu.fuPool.FUList0.opList]
171type=OpDesc
172issueLat=1
173opClass=IntAlu
174opLat=1
175
176[system.cpu.fuPool.FUList1]
177type=FUDesc
178children=opList0 opList1
179count=2
180opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
181
182[system.cpu.fuPool.FUList1.opList0]
183type=OpDesc
184issueLat=1
185opClass=IntMult
186opLat=3
187
188[system.cpu.fuPool.FUList1.opList1]
189type=OpDesc
190issueLat=19
191opClass=IntDiv
192opLat=20
193
194[system.cpu.fuPool.FUList2]
195type=FUDesc
196children=opList0 opList1 opList2
197count=4
198opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
199
200[system.cpu.fuPool.FUList2.opList0]
201type=OpDesc
202issueLat=1
203opClass=FloatAdd
204opLat=2
205
206[system.cpu.fuPool.FUList2.opList1]
207type=OpDesc
208issueLat=1
209opClass=FloatCmp
210opLat=2
211
212[system.cpu.fuPool.FUList2.opList2]
213type=OpDesc
214issueLat=1
215opClass=FloatCvt
216opLat=2
217
218[system.cpu.fuPool.FUList3]
219type=FUDesc
220children=opList0 opList1 opList2
221count=2
222opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
223
224[system.cpu.fuPool.FUList3.opList0]
225type=OpDesc
226issueLat=1
227opClass=FloatMult
228opLat=4
229
230[system.cpu.fuPool.FUList3.opList1]
231type=OpDesc
232issueLat=12
233opClass=FloatDiv
234opLat=12
235
236[system.cpu.fuPool.FUList3.opList2]
237type=OpDesc
238issueLat=24
239opClass=FloatSqrt
240opLat=24
241
242[system.cpu.fuPool.FUList4]
243type=FUDesc
244children=opList
245count=0
246opList=system.cpu.fuPool.FUList4.opList
247
248[system.cpu.fuPool.FUList4.opList]
249type=OpDesc
250issueLat=1
251opClass=MemRead
252opLat=1
253
254[system.cpu.fuPool.FUList5]
255type=FUDesc
256children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
257count=4
258opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
259
260[system.cpu.fuPool.FUList5.opList00]
261type=OpDesc
262issueLat=1
263opClass=SimdAdd
264opLat=1
265
266[system.cpu.fuPool.FUList5.opList01]
267type=OpDesc
268issueLat=1
269opClass=SimdAddAcc
270opLat=1
271
272[system.cpu.fuPool.FUList5.opList02]
273type=OpDesc
274issueLat=1
275opClass=SimdAlu
276opLat=1
277
278[system.cpu.fuPool.FUList5.opList03]
279type=OpDesc
280issueLat=1
281opClass=SimdCmp
282opLat=1
283
284[system.cpu.fuPool.FUList5.opList04]
285type=OpDesc
286issueLat=1
287opClass=SimdCvt
288opLat=1
289
290[system.cpu.fuPool.FUList5.opList05]
291type=OpDesc
292issueLat=1
293opClass=SimdMisc
294opLat=1
295
296[system.cpu.fuPool.FUList5.opList06]
297type=OpDesc
298issueLat=1
299opClass=SimdMult
300opLat=1
301
302[system.cpu.fuPool.FUList5.opList07]
303type=OpDesc
304issueLat=1
305opClass=SimdMultAcc
306opLat=1
307
308[system.cpu.fuPool.FUList5.opList08]
309type=OpDesc
310issueLat=1
311opClass=SimdShift
312opLat=1
313
314[system.cpu.fuPool.FUList5.opList09]
315type=OpDesc
316issueLat=1
317opClass=SimdShiftAcc
318opLat=1
319
320[system.cpu.fuPool.FUList5.opList10]
321type=OpDesc
322issueLat=1
323opClass=SimdSqrt
324opLat=1
325
326[system.cpu.fuPool.FUList5.opList11]
327type=OpDesc
328issueLat=1
329opClass=SimdFloatAdd
330opLat=1
331
332[system.cpu.fuPool.FUList5.opList12]
333type=OpDesc
334issueLat=1
335opClass=SimdFloatAlu
336opLat=1
337
338[system.cpu.fuPool.FUList5.opList13]
339type=OpDesc
340issueLat=1
341opClass=SimdFloatCmp
342opLat=1
343
344[system.cpu.fuPool.FUList5.opList14]
345type=OpDesc
346issueLat=1
347opClass=SimdFloatCvt
348opLat=1
349
350[system.cpu.fuPool.FUList5.opList15]
351type=OpDesc
352issueLat=1
353opClass=SimdFloatDiv
354opLat=1
355
356[system.cpu.fuPool.FUList5.opList16]
357type=OpDesc
358issueLat=1
359opClass=SimdFloatMisc
360opLat=1
361
362[system.cpu.fuPool.FUList5.opList17]
363type=OpDesc
364issueLat=1
365opClass=SimdFloatMult
366opLat=1
367
368[system.cpu.fuPool.FUList5.opList18]
369type=OpDesc
370issueLat=1
371opClass=SimdFloatMultAcc
372opLat=1
373
374[system.cpu.fuPool.FUList5.opList19]
375type=OpDesc
376issueLat=1
377opClass=SimdFloatSqrt
378opLat=1
379
380[system.cpu.fuPool.FUList6]
381type=FUDesc
382children=opList
383count=0
384opList=system.cpu.fuPool.FUList6.opList
385
386[system.cpu.fuPool.FUList6.opList]
387type=OpDesc
388issueLat=1
389opClass=MemWrite
390opLat=1
391
392[system.cpu.fuPool.FUList7]
393type=FUDesc
394children=opList0 opList1
395count=4
396opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
397
398[system.cpu.fuPool.FUList7.opList0]
399type=OpDesc
400issueLat=1
401opClass=MemRead
402opLat=1
403
404[system.cpu.fuPool.FUList7.opList1]
405type=OpDesc
406issueLat=1
407opClass=MemWrite
408opLat=1
409
410[system.cpu.fuPool.FUList8]
411type=FUDesc
412children=opList
413count=1
414opList=system.cpu.fuPool.FUList8.opList
415
416[system.cpu.fuPool.FUList8.opList]
417type=OpDesc
418issueLat=3
419opClass=IprAccess
420opLat=3
421
422[system.cpu.icache]
423type=BaseCache
424addr_ranges=0:18446744073709551615
425assoc=2
426block_size=64
427clock=500
428forward_snoops=true
429hash_delay=1
430hit_latency=2
431is_top_level=true
432max_miss_count=0
433mshrs=4
434prefetch_on_access=false
435prefetcher=Null
436prioritizeRequests=false
437repl=Null
438response_latency=2
439size=131072
440subblock_size=0
441system=system
442tgts_per_mshr=20
443trace_addr=0
444two_queue=false
445write_buffers=8
446cpu_side=system.cpu.icache_port
447mem_side=system.cpu.toL2Bus.slave[0]
448
449[system.cpu.interrupts]
450type=MipsInterrupts
451
452[system.cpu.isa]
453type=MipsISA
454num_threads=1
455num_vpes=1
456
457[system.cpu.itb]
458type=MipsTLB
459size=64
460
461[system.cpu.l2cache]
462type=BaseCache
463addr_ranges=0:18446744073709551615
464assoc=8
465block_size=64
466clock=500
467forward_snoops=true
468hash_delay=1
469hit_latency=20
470is_top_level=false
471max_miss_count=0
472mshrs=20
473prefetch_on_access=false
474prefetcher=Null
475prioritizeRequests=false
476repl=Null
477response_latency=20
478size=2097152
479subblock_size=0
480system=system
481tgts_per_mshr=12
482trace_addr=0
483two_queue=false
484write_buffers=8
485cpu_side=system.cpu.toL2Bus.master[0]
486mem_side=system.membus.slave[1]
487
488[system.cpu.toL2Bus]
489type=CoherentBus
490block_size=64
491clock=500
492header_cycles=1
493use_default_range=false
494width=32
495master=system.cpu.l2cache.cpu_side
496slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
497
498[system.cpu.tracer]
499type=ExeTracer
500
501[system.cpu.workload]
502type=LiveProcess
503cmd=hello
504cwd=
505egid=100
506env=
507errout=cerr
508euid=100
509executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello
510gid=100
511input=cin
512max_stack_size=67108864
513output=cout
514pid=100
515ppid=99
516simpoint=0
517system=system
518uid=100
519
520[system.membus]
521type=CoherentBus
522block_size=64
523clock=1000
524header_cycles=1
525use_default_range=false
526width=8
527master=system.physmem.port
528slave=system.system_port system.cpu.l2cache.mem_side
529
530[system.physmem]
531type=SimpleDRAM
532addr_mapping=openmap
533banks_per_rank=8
534clock=1000
535conf_table_reported=false
536in_addr_map=true
537lines_per_rowbuffer=64
538mem_sched_policy=fcfs
539null=false
540page_policy=open
541range=0:134217727
542ranks_per_channel=2
543read_buffer_size=32
544tBURST=4000
545tCL=14000
546tRCD=14000
547tREFI=7800000
548tRFC=300000
549tRP=14000
550tWTR=1000
551write_buffer_size=32
552write_thresh_perc=70
553zero=false
554port=system.membus.master[0]
555