1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 159 unchanged lines hidden (view full) ---

168localHistoryTableSize=2048
169localPredictorSize=2048
170numThreads=1
171useIndirect=true
172
173[system.cpu.dcache]
174type=Cache
175children=tags
176addr_ranges=0:18446744073709551615
177assoc=2
178clk_domain=system.cpu_clk_domain
179clusivity=mostly_incl
180default_p_state=UNDEFINED
181demand_mshr_reserve=1
182eventq_index=0
183hit_latency=2
184is_read_only=false

--- 341 unchanged lines hidden (view full) ---

526eventq_index=0
527opClass=IprAccess
528opLat=3
529pipelined=false
530
531[system.cpu.icache]
532type=Cache
533children=tags
534addr_ranges=0:18446744073709551615
535assoc=2
536clk_domain=system.cpu_clk_domain
537clusivity=mostly_incl
538default_p_state=UNDEFINED
539demand_mshr_reserve=1
540eventq_index=0
541hit_latency=2
542is_read_only=true

--- 45 unchanged lines hidden (view full) ---

588[system.cpu.itb]
589type=MipsTLB
590eventq_index=0
591size=64
592
593[system.cpu.l2cache]
594type=Cache
595children=tags
596addr_ranges=0:18446744073709551615
597assoc=8
598clk_domain=system.cpu_clk_domain
599clusivity=mostly_incl
600default_p_state=UNDEFINED
601demand_mshr_reserve=1
602eventq_index=0
603hit_latency=20
604is_read_only=false

--- 100 unchanged lines hidden (view full) ---

705domains=
706enable=false
707eventq_index=0
708sys_clk_domain=system.clk_domain
709transition_latency=100000000
710
711[system.membus]
712type=CoherentXBar
713clk_domain=system.clk_domain
714default_p_state=UNDEFINED
715eventq_index=0
716forward_latency=4
717frontend_latency=3
718p_state_clk_gate_bins=20
719p_state_clk_gate_max=1000000000000
720p_state_clk_gate_min=1000
721point_of_coherency=true
722power_model=Null
723response_latency=2
724snoop_filter=Null
725snoop_response_latency=4
726system=system
727use_default_range=false
728width=16
729master=system.physmem.port
730slave=system.system_port system.cpu.l2cache.mem_side
731
732[system.physmem]
733type=DRAMCtrl
734IDD0=0.075000
735IDD02=0.000000
736IDD2N=0.050000
737IDD2N2=0.000000
738IDD2P0=0.000000
739IDD2P02=0.000000
740IDD2P1=0.000000
741IDD2P12=0.000000
742IDD3N=0.057000
743IDD3N2=0.000000
744IDD3P0=0.000000
745IDD3P02=0.000000
746IDD3P1=0.000000
747IDD3P12=0.000000
748IDD4R=0.187000
749IDD4R2=0.000000
750IDD4W=0.165000
751IDD4W2=0.000000
752IDD5=0.220000
753IDD52=0.000000
754IDD6=0.000000
755IDD62=0.000000
756VDD=1.500000
757VDD2=0.000000
758activation_limit=4
759addr_mapping=RoRaBaCoCh
760bank_groups_per_rank=0
761banks_per_rank=8
762burst_length=8
763channels=1
764clk_domain=system.clk_domain
765conf_table_reported=true
766default_p_state=UNDEFINED
767device_bus_width=8
768device_rowbuffer_size=1024
769device_size=536870912
770devices_per_rank=8
771dll=true
772eventq_index=0
773in_addr_map=true
774max_accesses_per_row=16
775mem_sched_policy=frfcfs
776min_writes_per_switch=16
777null=false
778p_state_clk_gate_bins=20
779p_state_clk_gate_max=1000000000000
780p_state_clk_gate_min=1000
781page_policy=open_adaptive
782power_model=Null
783range=0:134217727
784ranks_per_channel=2
785read_buffer_size=32
786static_backend_latency=10000
787static_frontend_latency=10000
788tBURST=5000
789tCCD_L=0
790tCK=1250
791tCL=13750

--- 5 unchanged lines hidden (view full) ---

797tRP=13750
798tRRD=6000
799tRRD_L=0
800tRTP=7500
801tRTW=2500
802tWR=15000
803tWTR=7500
804tXAW=30000
805tXP=0
806tXPDLL=0
807tXS=0
808tXSDLL=0
809write_buffer_size=64
810write_high_thresh_perc=85
811write_low_thresh_perc=50
812port=system.membus.master[0]
813
814[system.voltage_domain]
815type=VoltageDomain
816eventq_index=0
817voltage=1.000000
818