1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000

--- 4 unchanged lines hidden (view full) ---

13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
14boot_osflags=a
15cache_line_size=64
16clk_domain=system.clk_domain
17eventq_index=0
18init_param=0
19kernel=
20load_addr_mask=1099511627775
21load_offset=0
22mem_mode=timing
23mem_ranges=
24memories=system.physmem
25num_work_ids=16
26readfile=
27symbolfile=
28work_begin_ckpt_count=0
29work_begin_cpu_id_exit=-1

--- 81 unchanged lines hidden (view full) ---

111smtFetchPolicy=SingleThread
112smtIQPolicy=Partitioned
113smtIQThreshold=100
114smtLSQPolicy=Partitioned
115smtLSQThreshold=100
116smtNumFetchingThreads=1
117smtROBPolicy=Partitioned
118smtROBThreshold=100
119socket_id=0
120squashWidth=8
121store_set_clear_period=250000
122switched_out=false
123system=system
124tracer=system.cpu.tracer
125trapLatency=13
126wbDepth=1
127wbWidth=8

--- 470 unchanged lines hidden (view full) ---

598type=LiveProcess
599cmd=hello
600cwd=
601egid=100
602env=
603errout=cerr
604euid=100
605eventq_index=0
606executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello
607gid=100
608input=cin
609max_stack_size=67108864
610output=cout
611pid=100
612ppid=99
613simpoint=0
614system=system

--- 12 unchanged lines hidden (view full) ---

627header_cycles=1
628system=system
629use_default_range=false
630width=8
631master=system.physmem.port
632slave=system.system_port system.cpu.l2cache.mem_side
633
634[system.physmem]
635type=DRAMCtrl
636activation_limit=4
637addr_mapping=RoRaBaChCo
638banks_per_rank=8
639burst_length=8
640channels=1
641clk_domain=system.clk_domain
642conf_table_reported=true
643device_bus_width=8
644device_rowbuffer_size=1024
645devices_per_rank=8
646eventq_index=0
647in_addr_map=true
648max_accesses_per_row=16
649mem_sched_policy=frfcfs
650min_writes_per_switch=16
651null=false
652page_policy=open_adaptive
653range=0:134217727
654ranks_per_channel=2
655read_buffer_size=32
656static_backend_latency=10000
657static_frontend_latency=10000
658tBURST=5000
659tCK=1250
660tCL=13750
661tRAS=35000
662tRCD=13750
663tREFI=7800000
664tRFC=260000
665tRP=13750
666tRRD=6000
667tRTP=7500
668tRTW=2500
669tWR=15000
670tWTR=7500
671tXAW=30000
672write_buffer_size=64
673write_high_thresh_perc=85
674write_low_thresh_perc=50
675port=system.membus.master[0]
676
677[system.voltage_domain]
678type=VoltageDomain
679eventq_index=0
680voltage=1.000000
681