| stats.txt (9481:b0fa6b872f40) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25969000 # Number of ticks simulated 5final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25969000 # Number of ticks simulated 5final_tick 25969000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66941 # Simulator instruction rate (inst/s) 8host_op_rate 83151 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 380602116 # Simulator tick rate (ticks/s) 10host_mem_usage 284140 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 220478 # Simulator instruction rate (inst/s) 8host_op_rate 273604 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1251201624 # Simulator tick rate (ticks/s) 10host_mem_usage 241012 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 554507297 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 308059610 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 862566907 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 554507297 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 554507297 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 554507297 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 308059610 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 862566907 # Total bandwidth to/from this memory (bytes/s) |
| 30system.membus.throughput 862566907 # Throughput (bytes/s) 31system.membus.trans_dist::ReadReq 307 # Transaction distribution 32system.membus.trans_dist::ReadResp 307 # Transaction distribution 33system.membus.trans_dist::ReadExReq 43 # Transaction distribution 34system.membus.trans_dist::ReadExResp 43 # Transaction distribution 35system.membus.pkt_count_system.cpu.l2cache.mem_side 700 # Packet count per connected master and slave (bytes) 36system.membus.pkt_count 700 # Packet count per connected master and slave (bytes) 37system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 22400 # Cumulative packet size per connected master and slave (bytes) 38system.membus.tot_pkt_size 22400 # Cumulative packet size per connected master and slave (bytes) 39system.membus.data_through_bus 22400 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.membus.reqLayer0.occupancy 350000 # Layer occupancy (ticks) 42system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 43system.membus.respLayer1.occupancy 3150000 # Layer occupancy (ticks) 44system.membus.respLayer1.utilization 12.1 # Layer utilization (%) |
|
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 361 unchanged lines hidden (view full) --- 399system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 400system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 401system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 402system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 403system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 404system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 405system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 406system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 45system.cpu.dtb.inst_hits 0 # ITB inst hits 46system.cpu.dtb.inst_misses 0 # ITB inst misses 47system.cpu.dtb.read_hits 0 # DTB read hits 48system.cpu.dtb.read_misses 0 # DTB read misses 49system.cpu.dtb.write_hits 0 # DTB write hits 50system.cpu.dtb.write_misses 0 # DTB write misses 51system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 52system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 361 unchanged lines hidden (view full) --- 414system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency 415system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 416system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 417system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 418system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 419system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 420system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 421system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 422system.cpu.toL2Bus.throughput 941430167 # Throughput (bytes/s) 423system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 424system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 425system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 426system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 427system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 482 # Packet count per connected master and slave (bytes) 428system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 282 # Packet count per connected master and slave (bytes) 429system.cpu.toL2Bus.pkt_count 764 # Packet count per connected master and slave (bytes) 430system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 15424 # Cumulative packet size per connected master and slave (bytes) 431system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9024 # Cumulative packet size per connected master and slave (bytes) 432system.cpu.toL2Bus.tot_pkt_size 24448 # Cumulative packet size per connected master and slave (bytes) 433system.cpu.toL2Bus.data_through_bus 24448 # Total data (bytes) 434system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 435system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 436system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 437system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 438system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 439system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 440system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
|
| 407 408---------- End Simulation Statistics ---------- | 441 442---------- End Simulation Statistics ---------- |