| stats.txt (9079:9a244ebdc3c9) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26351000 # Number of ticks simulated 5final_tick 26351000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000027 # Number of seconds simulated 4sim_ticks 27316000 # Number of ticks simulated 5final_tick 27316000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 50718 # Simulator instruction rate (inst/s) 8host_op_rate 63005 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 292657577 # Simulator tick rate (ticks/s) 10host_mem_usage 231660 # Number of bytes of host memory used | 7host_inst_rate 53670 # Simulator instruction rate (inst/s) 8host_op_rate 66671 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 321019881 # Simulator tick rate (ticks/s) 10host_mem_usage 231588 # Number of bytes of host memory used |
| 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory | 11host_seconds 0.09 # Real time elapsed on the host 12sim_insts 4565 # Number of instructions simulated 13sim_ops 5672 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 16system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 350 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 546468825 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 303593792 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 850062616 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 546468825 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 546468825 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 546468825 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 303593792 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 850062616 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 527163567 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 292868648 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 820032216 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 527163567 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 527163567 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 527163567 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 292868648 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 820032216 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls | 30system.cpu.dtb.inst_hits 0 # ITB inst hits 31system.cpu.dtb.inst_misses 0 # ITB inst misses 32system.cpu.dtb.read_hits 0 # DTB read hits 33system.cpu.dtb.read_misses 0 # DTB read misses 34system.cpu.dtb.write_hits 0 # DTB write hits 35system.cpu.dtb.write_misses 0 # DTB write misses 36system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 37system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 65system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 66system.cpu.itb.read_accesses 0 # DTB read accesses 67system.cpu.itb.write_accesses 0 # DTB write accesses 68system.cpu.itb.inst_accesses 0 # ITB inst accesses 69system.cpu.itb.hits 0 # DTB hits 70system.cpu.itb.misses 0 # DTB misses 71system.cpu.itb.accesses 0 # DTB accesses 72system.cpu.workload.num_syscalls 13 # Number of system calls |
| 73system.cpu.numCycles 52702 # number of cpu cycles simulated | 73system.cpu.numCycles 54632 # number of cpu cycles simulated |
| 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 4565 # Number of instructions committed 77system.cpu.committedOps 5672 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 80system.cpu.num_func_calls 203 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls 82system.cpu.num_int_insts 4976 # number of integer instructions 83system.cpu.num_fp_insts 16 # number of float instructions 84system.cpu.num_int_register_reads 28656 # number of times the integer registers were read 85system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 88system.cpu.num_mem_refs 2138 # number of memory refs 89system.cpu.num_load_insts 1200 # Number of load instructions 90system.cpu.num_store_insts 938 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles | 74system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 75system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 76system.cpu.committedInsts 4565 # Number of instructions committed 77system.cpu.committedOps 5672 # Number of ops (including micro ops) committed 78system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 79system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 80system.cpu.num_func_calls 203 # number of times a function call or return occured 81system.cpu.num_conditional_control_insts 774 # number of instructions that are conditional controls 82system.cpu.num_int_insts 4976 # number of integer instructions 83system.cpu.num_fp_insts 16 # number of float instructions 84system.cpu.num_int_register_reads 28656 # number of times the integer registers were read 85system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 86system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 87system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 88system.cpu.num_mem_refs 2138 # number of memory refs 89system.cpu.num_load_insts 1200 # Number of load instructions 90system.cpu.num_store_insts 938 # Number of store instructions 91system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 92system.cpu.num_busy_cycles 52702 # Number of busy cycles | 92system.cpu.num_busy_cycles 54632 # Number of busy cycles |
| 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 1 # number of replacements | 93system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 94system.cpu.idle_fraction 0 # Percentage of idle cycles 95system.cpu.icache.replacements 1 # number of replacements |
| 96system.cpu.icache.tagsinuse 114.562374 # Cycle average of tags in use | 96system.cpu.icache.tagsinuse 114.832264 # Cycle average of tags in use |
| 97system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 97system.cpu.icache.total_refs 4364 # Total number of references to valid blocks. 98system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks. 99system.cpu.icache.avg_refs 18.107884 # Average number of references to valid blocks. 100system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 101system.cpu.icache.occ_blocks::cpu.inst 114.562374 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.055939 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.055939 # Average percentage of cache occupancy | 101system.cpu.icache.occ_blocks::cpu.inst 114.832264 # Average occupied blocks per requestor 102system.cpu.icache.occ_percent::cpu.inst 0.056070 # Average percentage of cache occupancy 103system.cpu.icache.occ_percent::total 0.056070 # Average percentage of cache occupancy |
| 104system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 109system.cpu.icache.overall_hits::total 4364 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.dcache.replacements 0 # number of replacements | 104system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits 105system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits 106system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits 107system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits 108system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits 109system.cpu.icache.overall_hits::total 4364 # number of overall hits 110system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 111system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 166system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency 167system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50211.618257 # average ReadReq mshr miss latency 168system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 169system.cpu.icache.demand_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 170system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency 171system.cpu.icache.overall_avg_mshr_miss_latency::total 50211.618257 # average overall mshr miss latency 172system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 173system.cpu.dcache.replacements 0 # number of replacements |
| 174system.cpu.dcache.tagsinuse 82.961484 # Cycle average of tags in use | 174system.cpu.dcache.tagsinuse 83.122861 # Cycle average of tags in use |
| 175system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. 176system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 177system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. 178system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 175system.cpu.dcache.total_refs 1940 # Total number of references to valid blocks. 176system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. 177system.cpu.dcache.avg_refs 13.758865 # Average number of references to valid blocks. 178system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 179system.cpu.dcache.occ_blocks::cpu.data 82.961484 # Average occupied blocks per requestor 180system.cpu.dcache.occ_percent::cpu.data 0.020254 # Average percentage of cache occupancy 181system.cpu.dcache.occ_percent::total 0.020254 # Average percentage of cache occupancy | 179system.cpu.dcache.occ_blocks::cpu.data 83.122861 # Average occupied blocks per requestor 180system.cpu.dcache.occ_percent::cpu.data 0.020294 # Average percentage of cache occupancy 181system.cpu.dcache.occ_percent::total 0.020294 # Average percentage of cache occupancy |
| 182system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 183system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 184system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 185system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 186system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 187system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 188system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 189system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 82 unchanged lines hidden (view full) --- 272system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 273system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 274system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 275system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 276system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 277system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 278system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 279system.cpu.l2cache.replacements 0 # number of replacements | 182system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 183system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 184system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 185system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 186system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 187system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 188system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 189system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 82 unchanged lines hidden (view full) --- 272system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 273system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 274system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 275system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 276system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency 277system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency 278system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 279system.cpu.l2cache.replacements 0 # number of replacements |
| 280system.cpu.l2cache.tagsinuse 154.001524 # Cycle average of tags in use | 280system.cpu.l2cache.tagsinuse 154.336658 # Cycle average of tags in use |
| 281system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. 282system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 283system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. 284system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 281system.cpu.l2cache.total_refs 32 # Total number of references to valid blocks. 282system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks. 283system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks. 284system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 285system.cpu.l2cache.occ_blocks::cpu.inst 105.840466 # Average occupied blocks per requestor 286system.cpu.l2cache.occ_blocks::cpu.data 48.161058 # Average occupied blocks per requestor 287system.cpu.l2cache.occ_percent::cpu.inst 0.003230 # Average percentage of cache occupancy 288system.cpu.l2cache.occ_percent::cpu.data 0.001470 # Average percentage of cache occupancy 289system.cpu.l2cache.occ_percent::total 0.004700 # Average percentage of cache occupancy | 285system.cpu.l2cache.occ_blocks::cpu.inst 106.089659 # Average occupied blocks per requestor 286system.cpu.l2cache.occ_blocks::cpu.data 48.246999 # Average occupied blocks per requestor 287system.cpu.l2cache.occ_percent::cpu.inst 0.003238 # Average percentage of cache occupancy 288system.cpu.l2cache.occ_percent::cpu.data 0.001472 # Average percentage of cache occupancy 289system.cpu.l2cache.occ_percent::total 0.004710 # Average percentage of cache occupancy |
| 290system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 291system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 292system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 293system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 294system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 295system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 296system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 297system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 111 unchanged lines hidden --- | 290system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 291system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 292system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 293system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 294system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 295system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 296system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 297system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits --- 111 unchanged lines hidden --- |