| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26361000 # Number of ticks simulated 5final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 26361000 # Number of ticks simulated 5final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 140316 # Simulator instruction rate (inst/s) 8host_op_rate 174230 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 807994403 # Simulator tick rate (ticks/s) 10host_mem_usage 221092 # Number of bytes of host memory used | 7host_inst_rate 148609 # Simulator instruction rate (inst/s) 8host_op_rate 184448 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 855039933 # Simulator tick rate (ticks/s) 10host_mem_usage 228200 # Number of bytes of host memory used |
| 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 4574 # Number of instructions simulated 13sim_ops 5682 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 22400 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 350 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory --- 104 unchanged lines hidden (view full) --- 123system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency 125system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 126system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 11host_seconds 0.03 # Real time elapsed on the host 12sim_insts 4574 # Number of instructions simulated 13sim_ops 5682 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 22400 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 350 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory --- 104 unchanged lines hidden (view full) --- 123system.cpu.icache.overall_miss_rate::cpu.inst 0.052232 # miss rate for overall accesses 124system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency 125system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 126system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency 127system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 128system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 129system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 130system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 131system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 132system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 131system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 132system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 133system.cpu.icache.fast_writes 0 # number of fast writes performed 134system.cpu.icache.cache_copies 0 # number of cache copies performed 135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 136system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 137system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 138system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 139system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 140system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency 208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 209system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 210system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 133system.cpu.icache.fast_writes 0 # number of fast writes performed 134system.cpu.icache.cache_copies 0 # number of cache copies performed 135system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 136system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 137system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 138system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 139system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 140system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses --- 66 unchanged lines hidden (view full) --- 207system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency 208system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 209system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 210system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency 211system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 212system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 213system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 214system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 215system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 215system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 216system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 217system.cpu.dcache.fast_writes 0 # number of fast writes performed 218system.cpu.dcache.cache_copies 0 # number of cache copies performed 219system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 220system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 221system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 222system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 223system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 224system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses --- 82 unchanged lines hidden (view full) --- 307system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 308system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 309system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 310system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 311system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 314system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 217system.cpu.dcache.fast_writes 0 # number of fast writes performed 218system.cpu.dcache.cache_copies 0 # number of cache copies performed 219system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 220system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 221system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 222system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 223system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 224system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses --- 82 unchanged lines hidden (view full) --- 307system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 308system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 309system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 310system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 311system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 312system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 313system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 314system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 315system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 316system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 315system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 316system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 317system.cpu.l2cache.fast_writes 0 # number of fast writes performed 318system.cpu.l2cache.cache_copies 0 # number of cache copies performed 319system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 320system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 321system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 322system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 323system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 324system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 317system.cpu.l2cache.fast_writes 0 # number of fast writes performed 318system.cpu.l2cache.cache_copies 0 # number of cache copies performed 319system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 320system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 321system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 322system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 323system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 324system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |