Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28298500 # Number of ticks simulated
5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000029 # Number of seconds simulated
4sim_ticks 28648500 # Number of ticks simulated
5final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 246555 # Simulator instruction rate (inst/s)
8host_op_rate 287459 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1524533550 # Simulator tick rate (ticks/s)
10host_mem_usage 264352 # Number of bytes of host memory used

7host_inst_rate 192730 # Simulator instruction rate (inst/s)
8host_op_rate 224907 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1208517164 # Simulator tick rate (ticks/s)
10host_mem_usage 267456 # Number of bytes of host memory used

11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 4566 # Number of instructions simulated
13sim_ops 5330 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

16system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory

25system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

25system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s)
33system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 13 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 56597 # number of cpu cycles simulated

156system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states
157system.cpu.numCycles 57297 # number of cpu cycles simulated

158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 4566 # Number of instructions committed
161system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 203 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls

--- 4 unchanged lines hidden (view full) ---

170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
174system.cpu.num_mem_refs 1965 # number of memory refs
175system.cpu.num_load_insts 1027 # Number of load instructions
176system.cpu.num_store_insts 938 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles

178system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles

178system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles

179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 1008 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
184system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction

--- 22 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
212system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
213system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 5391 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

218system.cpu.dcache.tags.replacements 0 # number of replacements

219system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use

219system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use

220system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

224system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy

224system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy

227system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id

228system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id

228system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id

230system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
231system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
232system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses

233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

234system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
235system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
236system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
237system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
238system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
239system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
240system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
241system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits

--- 4 unchanged lines hidden (view full) ---

246system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
247system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
248system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
249system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
250system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
251system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
252system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
253system.cpu.dcache.overall_misses::total 141 # number of overall misses

254system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
255system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
256system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
257system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
258system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
259system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
260system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
261system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles

254system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles
255system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles
256system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles
257system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles
258system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles
259system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles
260system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles
261system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles

262system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
263system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
264system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
265system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
268system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
269system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)

--- 4 unchanged lines hidden (view full) ---

274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses
275system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses
276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
277system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
278system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses
279system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
280system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
281system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses

282system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
283system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
284system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
285system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
286system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
287system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
288system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
289system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency

282system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
283system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
284system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
285system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
286system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
287system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency
288system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
289system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency

290system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
291system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
292system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
293system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
294system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
295system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
296system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
297system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
298system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
299system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
300system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
301system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
302system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
303system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses

304system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
305system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
306system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
307system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
308system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
309system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
310system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
311system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles

304system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles
305system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles
306system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles
307system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles
308system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles
309system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles
310system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles
311system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles

312system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
313system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
314system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
315system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
316system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses
317system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
318system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
319system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses

320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
325system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
327system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
325system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
327system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

329system.cpu.icache.tags.replacements 1 # number of replacements

330system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use

330system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use

331system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
332system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
333system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
334system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

335system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
336system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
337system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy

335system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor
336system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy
337system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy

338system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id

339system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
340system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id

339system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
340system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id

341system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
342system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
343system.cpu.icache.tags.data_accesses 9453 # Number of data accesses

344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

345system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
346system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
347system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
348system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
349system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
350system.cpu.icache.overall_hits::total 4365 # number of overall hits
351system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
352system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
353system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
354system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
355system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
356system.cpu.icache.overall_misses::total 241 # number of overall misses

357system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
358system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
359system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
360system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
361system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
362system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles

357system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles
358system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles
359system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles
360system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles
361system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles
362system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles

363system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
364system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
366system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses
367system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses
368system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses
369system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses
370system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses
372system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
374system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses

375system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
376system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
377system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
378system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
379system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
380system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency

375system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency
376system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency
377system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
378system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency
379system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
380system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency

381system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
382system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
383system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
384system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
385system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
386system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
387system.cpu.icache.writebacks::writebacks 1 # number of writebacks
388system.cpu.icache.writebacks::total 1 # number of writebacks
389system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
390system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
391system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
392system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
393system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
394system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses

395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
396system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles

395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles
396system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles
397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles

401system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
402system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
404system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
406system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses

407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
410system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
412system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
410system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
412system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

414system.cpu.l2cache.tags.replacements 0 # number of replacements

415system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use

415system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use

416system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.

417system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
418system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.

417system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
418system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks.

419system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.

420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
421system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
423system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
424system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
425system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id

420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor
421system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor
422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy
423system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy
424system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy
425system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id

429system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
430system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses

431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

432system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
433system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
434system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
435system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits
436system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
437system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
438system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
439system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits

--- 6 unchanged lines hidden (view full) ---

446system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses
447system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses
448system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
449system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
450system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
451system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
452system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
453system.cpu.l2cache.overall_misses::total 350 # number of overall misses

454system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
455system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
456system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
457system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
458system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
459system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
460system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
461system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
462system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
463system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
464system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
465system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles

454system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles
455system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles
456system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles
457system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles
458system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles
459system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles
460system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles
461system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles
462system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles
463system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles
464system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles
465system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles

466system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
467system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
468system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
469system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses)
470system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses)
471system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses)
472system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
473system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses

--- 8 unchanged lines hidden (view full) ---

482system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses
483system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses
484system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
485system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
486system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
487system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
488system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
489system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses

490system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
491system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
492system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
493system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
494system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
495system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
496system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
497system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
498system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
499system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
500system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
501system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency

490system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
491system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
492system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency
493system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency
494system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
495system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
496system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
497system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
498system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency
499system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
500system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
501system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency

502system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
503system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
504system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
505system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
506system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
507system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
508system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
509system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
510system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
511system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses
512system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses
513system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses
514system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
515system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
516system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
517system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
518system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
519system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses

520system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
521system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
522system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
523system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
524system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
525system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
526system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
527system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
528system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
529system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
530system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
531system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles

520system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles
521system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles
522system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles
523system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles
524system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles
525system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles
526system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles
527system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles
528system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
529system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles
530system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles
531system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles

532system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
533system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
534system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
535system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses
536system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses
537system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses
538system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
539system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
540system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
541system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
542system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
543system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses

544system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
545system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
546system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
547system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
548system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
549system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
550system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
552system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
553system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency

544system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
545system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
546system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency
547system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency
548system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
549system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
550system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
552system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
553system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency

556system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
557system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
558system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
559system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
560system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
561system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

563system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
564system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
565system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
569system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
570system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)

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586system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
587system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
588system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
589system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
590system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
591system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
592system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
593system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)

594system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

594system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter.
595system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
596system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
597system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
598system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
599system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
600system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states

595system.membus.trans_dist::ReadResp 307 # Transaction distribution
596system.membus.trans_dist::ReadExReq 43 # Transaction distribution
597system.membus.trans_dist::ReadExResp 43 # Transaction distribution
598system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution
599system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
600system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
601system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
602system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)

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608system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
609system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram
610system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
611system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
612system.membus.snoop_fanout::min_value 0 # Request fanout histogram
613system.membus.snoop_fanout::max_value 0 # Request fanout histogram
614system.membus.snoop_fanout::total 350 # Request fanout histogram
615system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)

601system.membus.trans_dist::ReadResp 307 # Transaction distribution
602system.membus.trans_dist::ReadExReq 43 # Transaction distribution
603system.membus.trans_dist::ReadExResp 43 # Transaction distribution
604system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution
605system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes)
606system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes)
607system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes)
608system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes)

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614system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
615system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram
616system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
617system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
618system.membus.snoop_fanout::min_value 0 # Request fanout histogram
619system.membus.snoop_fanout::max_value 0 # Request fanout histogram
620system.membus.snoop_fanout::total 350 # Request fanout histogram
621system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)

616system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)

622system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)

617system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks)

623system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks)

618system.membus.respLayer1.utilization 6.2 # Layer utilization (%)

624system.membus.respLayer1.utilization 6.1 # Layer utilization (%)