Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 311400 # Simulator instruction rate (inst/s) 8host_op_rate 363255 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1927478424 # Simulator tick rate (ticks/s) 10host_mem_usage 306584 # Number of bytes of host memory used	7host_inst_rate 377704 # Simulator instruction rate (inst/s) 8host_op_rate 440559 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2337429945 # Simulator tick rate (ticks/s) 10host_mem_usage 308268 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks	34system.cpu_clk_domain.clock 500 # Clock period in ticks
	35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses	66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses
	95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls	126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 13 # Number of system calls
	156system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
150system.cpu.numCycles 56597 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction	157system.cpu.numCycles 56597 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 4566 # Number of instructions committed 161system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 203 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 209system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 212system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 213system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 5391 # Class of executed instruction
	217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
210system.cpu.dcache.tags.replacements 0 # number of replacements 211system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses	218system.cpu.dcache.tags.replacements 0 # number of replacements 219system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
	233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 78 unchanged lines hidden (view full) --- 311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 312system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 314system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 315system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 316system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 317system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 318system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency	234system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 235system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 236system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 237system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 238system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 239system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 240system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 241system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 78 unchanged lines hidden (view full) --- 320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 325system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 327system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
	328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
319system.cpu.icache.tags.replacements 1 # number of replacements 320system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 321system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 322system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 323system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 324system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 325system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 326system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy 327system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy 328system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 329system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 330system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 331system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 332system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 333system.cpu.icache.tags.data_accesses 9453 # Number of data accesses	329system.cpu.icache.tags.replacements 1 # number of replacements 330system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 331system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 332system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 333system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 334system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 335system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 336system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy 337system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy 338system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 339system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 340system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 341system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 342system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 343system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
	344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
334system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 335system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 336system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 337system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 338system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 339system.cpu.icache.overall_hits::total 4365 # number of overall hits 340system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 341system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 394system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 395system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 396system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 397system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 398system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 399system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 400system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 401system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency	345system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 346system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 347system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 348system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 349system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 350system.cpu.icache.overall_hits::total 4365 # number of overall hits 351system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 352system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 406system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 410system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 412system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
	413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
402system.cpu.l2cache.tags.replacements 0 # number of replacements 403system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 404system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 405system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 406system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 407system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 408system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 409system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor 410system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy 411system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy 412system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy 413system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 414system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 415system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 416system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 417system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 418system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses	414system.cpu.l2cache.tags.replacements 0 # number of replacements 415system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 416system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 417system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 418system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 419system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 421system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor 422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy 423system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy 424system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy 425system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 429system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 430system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
	431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
419system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits 420system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits 421system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 422system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits 423system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 424system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 425system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 426system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits --- 114 unchanged lines hidden (view full) --- 541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 542system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 543system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 544system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 545system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 546system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 547system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 548system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	432system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits 433system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits 434system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 435system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits 436system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 437system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 438system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 439system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits --- 114 unchanged lines hidden (view full) --- 554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 556system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 557system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 558system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 559system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 560system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 561system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
549system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 573system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) 574system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 575system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 576system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)	563system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 569system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 585system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 587system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) 588system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 589system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 590system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 591system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 592system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
	593system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
579system.membus.trans_dist::ReadResp 307 # Transaction distribution 580system.membus.trans_dist::ReadExReq 43 # Transaction distribution 581system.membus.trans_dist::ReadExResp 43 # Transaction distribution 582system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution 583system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 584system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 585system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 586system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---	594system.membus.trans_dist::ReadResp 307 # Transaction distribution 595system.membus.trans_dist::ReadExReq 43 # Transaction distribution 596system.membus.trans_dist::ReadExResp 43 # Transaction distribution 597system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution 598system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 599system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 600system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 601system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden ---

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28298500 # Number of ticks simulated
5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 311400 # Simulator instruction rate (inst/s)
8host_op_rate 363255 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1927478424 # Simulator tick rate (ticks/s)
10host_mem_usage 306584 # Number of bytes of host memory used

7host_inst_rate 377704 # Simulator instruction rate (inst/s)
8host_op_rate 440559 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2337429945 # Simulator tick rate (ticks/s)
10host_mem_usage 308268 # Number of bytes of host memory used

11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4566 # Number of instructions simulated
13sim_ops 5330 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 13 unchanged lines hidden (view full) ---

117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 13 # Number of system calls

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst

--- 14 unchanged lines hidden (view full) ---

148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 13 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states

150system.cpu.numCycles 56597 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 4566 # Number of instructions committed
154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
157system.cpu.num_func_calls 203 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 5391 # Class of executed instruction

157system.cpu.numCycles 56597 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 4566 # Number of instructions committed
161system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 203 # number of times a function call or return occured

--- 44 unchanged lines hidden (view full) ---

209system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
212system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
213system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 5391 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

210system.cpu.dcache.tags.replacements 0 # number of replacements
211system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses

218system.cpu.dcache.tags.replacements 0 # number of replacements
219system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
220system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
230system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
231system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
232system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses

233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits

--- 78 unchanged lines hidden (view full) ---

311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
312system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
314system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
315system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
316system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
317system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
318system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency

234system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
235system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
236system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
237system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
238system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
239system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
240system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
241system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits

--- 78 unchanged lines hidden (view full) ---

320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
325system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
327system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency

328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

319system.cpu.icache.tags.replacements 1 # number of replacements
320system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
321system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
322system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
323system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
324system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
325system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
326system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
327system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
328system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
329system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
330system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
331system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
332system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
333system.cpu.icache.tags.data_accesses 9453 # Number of data accesses

329system.cpu.icache.tags.replacements 1 # number of replacements
330system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
331system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
332system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
333system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
334system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
335system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
336system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
337system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
338system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
339system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
340system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
341system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
342system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
343system.cpu.icache.tags.data_accesses 9453 # Number of data accesses

344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

334system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
335system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
336system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
337system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
338system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
339system.cpu.icache.overall_hits::total 4365 # number of overall hits
340system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
341system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

394system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
395system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
396system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
397system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
398system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
399system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
400system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
401system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency

345system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
346system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
347system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
348system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
349system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
350system.cpu.icache.overall_hits::total 4365 # number of overall hits
351system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
352system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses

--- 52 unchanged lines hidden (view full) ---

405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
406system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
410system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
412system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency

413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

402system.cpu.l2cache.tags.replacements 0 # number of replacements
403system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
404system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
405system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
406system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
407system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
408system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
409system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
410system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
411system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
412system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
413system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
414system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
415system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
416system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
417system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
418system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses

414system.cpu.l2cache.tags.replacements 0 # number of replacements
415system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
416system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
417system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
418system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
419system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
421system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
423system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
424system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
425system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
429system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
430system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses

431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

419system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
420system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
421system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
422system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits
423system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
424system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
425system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
426system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits

--- 114 unchanged lines hidden (view full) ---

541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
542system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
543system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
544system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
545system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
546system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
547system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
548system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

432system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
433system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
434system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
435system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits
436system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
437system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
438system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
439system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits

--- 114 unchanged lines hidden (view full) ---

554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
556system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
557system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
558system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
559system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
560system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
561system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

549system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
550system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
551system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
552system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
553system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
554system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)

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571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
572system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
573system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
574system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
575system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
576system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
577system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
578system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)

563system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
564system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
565system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
569system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
570system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)

--- 14 unchanged lines hidden (view full) ---

585system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
586system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
587system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
588system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
589system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
590system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
591system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
592system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)

593system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states