| stats.txt (11336:b318499f676c) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 286813 # Simulator instruction rate (inst/s) 8host_op_rate 333728 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1769783602 # Simulator tick rate (ticks/s) 10host_mem_usage 267436 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host | 7host_inst_rate 441317 # Simulator instruction rate (inst/s) 8host_op_rate 514292 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2726097982 # Simulator tick rate (ticks/s) 10host_mem_usage 267744 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory --- 259 unchanged lines hidden (view full) --- 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory --- 259 unchanged lines hidden (view full) --- 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 287system.cpu.dcache.fast_writes 0 # number of fast writes performed 288system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 318system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 320system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency | 287system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 288system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 289system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 290system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 291system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 292system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 293system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 294system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses --- 16 unchanged lines hidden (view full) --- 311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 312system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 314system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 315system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 316system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 317system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 318system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency |
| 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 322system.cpu.icache.tags.replacements 1 # number of replacements 323system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 328system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 329system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 319system.cpu.icache.tags.replacements 1 # number of replacements 320system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 321system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 322system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 323system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 324system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 325system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 326system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 368system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 369system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency 370system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 381system.cpu.icache.writebacks::writebacks 1 # number of writebacks 382system.cpu.icache.writebacks::total 1 # number of writebacks 383system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 384system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 385system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 386system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 387system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 388system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 399system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 400system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 401system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 402system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 403system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 404system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 405system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 406system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency | 376system.cpu.icache.writebacks::writebacks 1 # number of writebacks 377system.cpu.icache.writebacks::total 1 # number of writebacks 378system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 379system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 380system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 381system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 382system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 383system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses --- 10 unchanged lines hidden (view full) --- 394system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 395system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 396system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 397system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 398system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 399system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 400system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 401system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency |
| 407system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 408system.cpu.l2cache.tags.replacements 0 # number of replacements 409system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 410system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 411system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 412system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 413system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 414system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 415system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 493system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 494system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency 495system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 496system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 497system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 498system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 499system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 500system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 402system.cpu.l2cache.tags.replacements 0 # number of replacements 403system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 404system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 405system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 406system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 407system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 408system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 409system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 487system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 488system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency 489system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 490system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 491system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 492system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 493system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 494system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 501system.cpu.l2cache.fast_writes 0 # number of fast writes performed 502system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 503system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 504system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 505system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses 506system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses 507system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses 508system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses 509system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 510system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 543system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 544system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 545system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 546system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 547system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 548system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 549system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 550system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency | 495system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 496system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 497system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses 498system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses 499system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses 500system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses 501system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 502system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 535system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 536system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 537system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 538system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 539system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 540system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 542system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency |
| 551system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 552system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 553system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 554system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 555system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 556system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 557system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 558system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution --- 53 unchanged lines hidden --- | 543system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 544system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 545system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 546system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 547system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 548system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 549system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution --- 53 unchanged lines hidden --- |