| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated |
| 4sim_ticks 25816500 # Number of ticks simulated 5final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 25848500 # Number of ticks simulated 5final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 428411 # Simulator instruction rate (inst/s) 8host_op_rate 499438 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2416370273 # Simulator tick rate (ticks/s) 10host_mem_usage 308620 # Number of bytes of host memory used | 7host_inst_rate 341128 # Simulator instruction rate (inst/s) 8host_op_rate 397821 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1927554064 # Simulator tick rate (ticks/s) 10host_mem_usage 312280 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s) |
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls |
| 150system.cpu.numCycles 51633 # number of cpu cycles simulated | 150system.cpu.numCycles 51697 # number of cpu cycles simulated |
| 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 167system.cpu.num_mem_refs 1965 # number of memory refs 168system.cpu.num_load_insts 1027 # Number of load instructions 169system.cpu.num_store_insts 938 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles | 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls --- 4 unchanged lines hidden (view full) --- 163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 167system.cpu.num_mem_refs 1965 # number of memory refs 168system.cpu.num_load_insts 1027 # Number of load instructions 169system.cpu.num_store_insts 938 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| 171system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles | 171system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles |
| 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 1008 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction 210system.cpu.dcache.tags.replacements 0 # number of replacements | 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 1008 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction 210system.cpu.dcache.tags.replacements 0 # number of replacements |
| 211system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use | 211system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use |
| 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy | 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy |
| 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses 225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 244system.cpu.dcache.overall_misses::total 141 # number of overall misses | 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses 225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits --- 10 unchanged lines hidden (view full) --- 237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 244system.cpu.dcache.overall_misses::total 141 # number of overall misses |
| 245system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 246system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles | 245system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles 246system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles |
| 247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 248system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles | 247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 248system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles |
| 249system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 250system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 251system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 252system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles | 249system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles 250system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles 251system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles 252system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles |
| 253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses | 253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 4 unchanged lines hidden (view full) --- 265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses |
| 273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 274system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency | 273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency 274system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency |
| 275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 276system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency | 275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 276system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency |
| 277system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 278system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency | 277system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency 278system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency |
| 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.dcache.fast_writes 0 # number of fast writes performed 288system.cpu.dcache.cache_copies 0 # number of cache copies performed 289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses | 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.dcache.fast_writes 0 # number of fast writes performed 288system.cpu.dcache.cache_copies 0 # number of cache copies performed 289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses |
| 297system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles 298system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles | 297system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles 298system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles |
| 299system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles 300system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles | 299system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2322000 # number of WriteReq MSHR miss cycles 300system.cpu.dcache.WriteReq_mshr_miss_latency::total 2322000 # number of WriteReq MSHR miss cycles |
| 301system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles 302system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles 303system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles 304system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles | 301system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles 302system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles 303system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles 304system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles |
| 305system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 306system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 307system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 308system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 309system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 310system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 311system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 312system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses | 305system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 306system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 307system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 308system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 309system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 310system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 311system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 312system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses |
| 313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency 314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency | 313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency 314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency |
| 315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency | 315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54000 # average WriteReq mshr miss latency 316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54000 # average WriteReq mshr miss latency |
| 317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency 318system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency 319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency 320system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency | 317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency 318system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency 319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency 320system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency |
| 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 322system.cpu.icache.tags.replacements 1 # number of replacements | 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 322system.cpu.icache.tags.replacements 1 # number of replacements |
| 323system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use | 323system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use |
| 324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 328system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor 329system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy 330system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy | 328system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor 329system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy 330system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy |
| 331system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 332system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 333system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 334system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 335system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 336system.cpu.icache.tags.data_accesses 9453 # Number of data accesses 337system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 338system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 339system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 340system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 341system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 342system.cpu.icache.overall_hits::total 4365 # number of overall hits 343system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 344system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 345system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 346system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 347system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 348system.cpu.icache.overall_misses::total 241 # number of overall misses | 331system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 332system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 333system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 334system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 335system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 336system.cpu.icache.tags.data_accesses 9453 # Number of data accesses 337system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 338system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 339system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 340system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 341system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 342system.cpu.icache.overall_hits::total 4365 # number of overall hits 343system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 344system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 345system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 346system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 347system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 348system.cpu.icache.overall_misses::total 241 # number of overall misses |
| 349system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles 350system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles 351system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles 352system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles 353system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles 354system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles | 349system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles 350system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles 351system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles 352system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles 353system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles 354system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles |
| 355system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 356system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 357system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 358system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 359system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 360system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 361system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 362system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 363system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 364system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 365system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 366system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses | 355system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 356system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 357system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 358system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 359system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 360system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 361system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 362system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 363system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 364system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 365system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 366system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses |
| 367system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency 368system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency 369system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 370system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency | 367system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency 368system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency 369system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency 370system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency |
| 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 382system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 383system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 384system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 385system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 386system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses | 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 382system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 383system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 384system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 385system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 386system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses |
| 387system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles 388system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles 389system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles 390system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles 392system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles | 387system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles 388system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles 389system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles 390system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles 392system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles |
| 393system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 395system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 396system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 397system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 398system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses | 393system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 395system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 396system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 397system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 398system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses |
| 399system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency 400system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency 401system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency 402system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency 404system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency | 399system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency 400system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency 401system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency 402system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency 404system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency |
| 405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cpu.l2cache.tags.replacements 0 # number of replacements | 405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 407system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use | 407system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use |
| 408system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 409system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 410system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 411system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 408system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 409system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 410system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 411system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 412system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor 413system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor | 412system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor 413system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor |
| 414system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 416system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 420system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 421system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses --- 120 unchanged lines hidden (view full) --- 542system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 543system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency 544system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 545system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency 546system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency 547system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 548system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency 549system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 414system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003225 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 416system.cpu.l2cache.tags.occ_percent::total 0.004694 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 420system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 421system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses --- 120 unchanged lines hidden (view full) --- 542system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 543system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency 544system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 545system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency 546system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42524.444444 # average overall mshr miss latency 547system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 548system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42515.714286 # average overall mshr miss latency 549system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 550system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 551system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 552system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 553system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 554system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 555system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 550system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.snoops 0 # Total snoops (count) 562system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram | 556system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 557system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 558system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 559system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 560system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 561system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 562system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 563system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 564system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 565system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 566system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 567system.cpu.toL2Bus.snoops 0 # Total snoops (count) 568system.cpu.toL2Bus.snoop_fanout::samples 383 # Request fanout histogram |
| 563system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 564system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram | 569system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram |
| 565system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 571system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 566system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 567system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram | 572system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram 573system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram |
| 568system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 569system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 574system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 575system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 570system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram | 576system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| 571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram 573system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) 574system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 575system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 576system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- | 577system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 578system.cpu.toL2Bus.snoop_fanout::total 383 # Request fanout histogram 579system.cpu.toL2Bus.reqLayer0.occupancy 191500 # Layer occupancy (ticks) 580system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 581system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 582system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 583system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 584system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) --- 25 unchanged lines hidden --- |