3,5c3,5
< sim_seconds 0.000028 # Number of seconds simulated
< sim_ticks 28298500 # Number of ticks simulated
< final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000029 # Number of seconds simulated
> sim_ticks 28648500 # Number of ticks simulated
> final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 246555 # Simulator instruction rate (inst/s)
< host_op_rate 287459 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1524533550 # Simulator tick rate (ticks/s)
< host_mem_usage 264352 # Number of bytes of host memory used
---
> host_inst_rate 192730 # Simulator instruction rate (inst/s)
> host_op_rate 224907 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1208517164 # Simulator tick rate (ticks/s)
> host_mem_usage 267456 # Number of bytes of host memory used
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 56597 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 57297 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy
228,229c228,229
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
233c233
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
254,261c254,261
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles
282,289c282,289
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency
304,311c304,311
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles
320,328c320,328
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
330c330
< system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use
335,337c335,337
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy
339,340c339,340
< system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
344c344
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
357,362c357,362
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles
375,380c375,380
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency
395,400c395,400
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles
407,413c407,413
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
415c415
< system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use
417,418c417,418
< system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks.
420,428c420,428
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
431c431
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
454,465c454,465
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles
490,501c490,501
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency
520,531c520,531
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
544,555c544,555
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
562c562
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
594c594,600
< system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
616c622
< system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
618c624
< system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 6.1 # Layer utilization (%)
< sim_seconds 0.000028 # Number of seconds simulated
< sim_ticks 28298500 # Number of ticks simulated
< final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000029 # Number of seconds simulated
> sim_ticks 28648500 # Number of ticks simulated
> final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 246555 # Simulator instruction rate (inst/s)
< host_op_rate 287459 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1524533550 # Simulator tick rate (ticks/s)
< host_mem_usage 264352 # Number of bytes of host memory used
---
> host_inst_rate 192730 # Simulator instruction rate (inst/s)
> host_op_rate 224907 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1208517164 # Simulator tick rate (ticks/s)
> host_mem_usage 267456 # Number of bytes of host memory used
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
35c35
< system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
65c65
< system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
95c95
< system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
125c125
< system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
156,157c156,157
< system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 56597 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 28648500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 57297 # number of cpu cycles simulated
178c178
< system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 57296.998000 # Number of busy cycles
217c217
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
219c219
< system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.616265 # Cycle average of tags in use
224,226c224,226
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.616265 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020170 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020170 # Average percentage of cache occupancy
228,229c228,229
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
233c233
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
254,261c254,261
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5390000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5390000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2709000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2709000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8099000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8099000 # number of overall miss cycles
282,289c282,289
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 57439.716312 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 57439.716312 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 57439.716312 # average overall miss latency
304,311c304,311
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5292000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5292000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2666000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2666000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7958000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7958000 # number of overall MSHR miss cycles
320,328c320,328
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56439.716312 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 56439.716312 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
330c330
< system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 113.995886 # Cycle average of tags in use
335,337c335,337
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 113.995886 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055662 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055662 # Average percentage of cache occupancy
339,340c339,340
< system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 145 # Occupied blocks per task id
344c344
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
357,362c357,362
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 14404500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 14404500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 14404500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 14404500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 14404500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 14404500 # number of overall miss cycles
375,380c375,380
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59769.709544 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 59769.709544 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 59769.709544 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 59769.709544 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 59769.709544 # average overall miss latency
395,400c395,400
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14163500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 14163500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14163500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 14163500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14163500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 14163500 # number of overall MSHR miss cycles
407,413c407,413
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 58769.709544 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 58769.709544 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 58769.709544 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 58769.709544 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
415c415
< system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 180.559791 # Cycle average of tags in use
417,418c417,418
< system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.091429 # Average number of references to valid blocks.
420,428c420,428
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.285464 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 75.274327 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003213 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002297 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.005510 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id
431c431
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
454,465c454,465
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2601500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2601500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13618000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 13618000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4961000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 4961000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 13618000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7562500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 21180500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 13618000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7562500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 21180500 # number of overall miss cycles
490,501c490,501
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60524.444444 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60524.444444 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60515.714286 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60524.444444 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60515.714286 # average overall miss latency
520,531c520,531
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2171500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2171500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11368000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11368000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4141000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4141000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11368000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6312500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17680500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11368000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6312500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17680500 # number of overall MSHR miss cycles
544,555c544,555
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50524.444444 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50524.444444 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50524.444444 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50515.714286 # average overall mshr miss latency
562c562
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
594c594,600
< system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 350 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states
616c622
< system.membus.reqLayer0.utilization 1.3 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
618c624
< system.membus.respLayer1.utilization 6.2 # Layer utilization (%)
---
> system.membus.respLayer1.utilization 6.1 # Layer utilization (%)