4,5c4,5
< sim_ticks 25816500 # Number of ticks simulated
< final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25848500 # Number of ticks simulated
> final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 428411 # Simulator instruction rate (inst/s)
< host_op_rate 499438 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2416370273 # Simulator tick rate (ticks/s)
< host_mem_usage 308620 # Number of bytes of host memory used
---
> host_inst_rate 341128 # Simulator instruction rate (inst/s)
> host_op_rate 397821 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1927554064 # Simulator tick rate (ticks/s)
> host_mem_usage 312280 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 51633 # number of cpu cycles simulated
---
> system.cpu.numCycles 51697 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use
216,218c216,218
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy
245,246c245,246
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles
249,252c249,252
< system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles
273,274c273,274
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency
277,280c277,280
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency
297,298c297,298
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles
301,304c301,304
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles
313,314c313,314
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency
317,320c317,320
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
323c323
< system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use
328,330c328,330
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy
349,354c349,354
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles
367,372c367,372
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency
387,392c387,392
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
407c407
< system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use
412,413c412,413
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor
549a550,555
> system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
563,564c569,570
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram
566,567c572,573
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram
570c576
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
< sim_ticks 25816500 # Number of ticks simulated
< final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25848500 # Number of ticks simulated
> final_tick 25848500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 428411 # Simulator instruction rate (inst/s)
< host_op_rate 499438 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2416370273 # Simulator tick rate (ticks/s)
< host_mem_usage 308620 # Number of bytes of host memory used
---
> host_inst_rate 341128 # Simulator instruction rate (inst/s)
> host_op_rate 397821 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1927554064 # Simulator tick rate (ticks/s)
> host_mem_usage 312280 # Number of bytes of host memory used
24,31c24,31
< system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 557092288 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 309495715 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 866588003 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 557092288 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 557092288 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 557092288 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 309495715 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 866588003 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 51633 # number of cpu cycles simulated
---
> system.cpu.numCycles 51697 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 51696.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 82.893462 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.887597 # Cycle average of tags in use
216,218c216,218
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.893462 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.887597 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020236 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020236 # Average percentage of cache occupancy
245,246c245,246
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4734000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4734000 # number of ReadReq miss cycles
249,252c249,252
< system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 7099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7099000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7099000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7099000 # number of overall miss cycles
273,274c273,274
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48306.122449 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 48306.122449 # average ReadReq miss latency
277,280c277,280
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 50347.517730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 50347.517730 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 50347.517730 # average overall miss latency
297,298c297,298
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4620000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4620000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4636000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4636000 # number of ReadReq MSHR miss cycles
301,304c301,304
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6942000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6942000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6942000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6942000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6958000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6958000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6958000 # number of overall MSHR miss cycles
313,314c313,314
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47142.857143 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47306.122449 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47306.122449 # average ReadReq mshr miss latency
317,320c317,320
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 49234.042553 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49347.517730 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 49347.517730 # average overall mshr miss latency
323c323
< system.cpu.icache.tags.tagsinuse 114.412880 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 114.411093 # Cycle average of tags in use
328,330c328,330
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.412880 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055866 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055866 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 114.411093 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055865 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055865 # Average percentage of cache occupancy
349,354c349,354
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12604500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12604500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12604500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12604500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12604500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12604500 # number of overall miss cycles
367,372c367,372
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52300.829876 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 52300.829876 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 52300.829876 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 52300.829876 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 52300.829876 # average overall miss latency
387,392c387,392
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12347500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12347500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12347500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12347500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12347500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12347500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12363500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12363500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12363500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12363500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12363500 # number of overall MSHR miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51234.439834 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51234.439834 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51234.439834 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 51234.439834 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51300.829876 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51300.829876 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51300.829876 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 51300.829876 # average overall mshr miss latency
407c407
< system.cpu.l2cache.tags.tagsinuse 153.810302 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 153.806088 # Cycle average of tags in use
412,413c412,413
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.682127 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48.128175 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.680973 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48.125115 # Average occupied blocks per requestor
549a550,555
> system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
563,564c569,570
< system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 0.086162 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0.280970 # Request fanout histogram
566,567c572,573
< system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::1 383 100.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::0 350 91.38% 91.38% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 33 8.62% 100.00% # Request fanout histogram
570c576
< system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram