4,5c4,5
< sim_ticks 25815000 # Number of ticks simulated
< final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25815500 # Number of ticks simulated
> final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 376930 # Simulator instruction rate (inst/s)
< host_op_rate 439541 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2127142386 # Simulator tick rate (ticks/s)
< host_mem_usage 307352 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 263675 # Simulator instruction rate (inst/s)
> host_op_rate 307555 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1488783160 # Simulator tick rate (ticks/s)
> host_mem_usage 306760 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 51630 # number of cpu cycles simulated
---
> system.cpu.numCycles 51631 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use
216,218c216,218
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
297,304c297,304
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles
313,320c313,320
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
323c323
< system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use
328,330c328,330
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy
349,354c349,354
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
367,372c367,372
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
387,392c387,392
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
407c407
< system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use
412,413c412,413
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor
443,453c443,453
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles
476,486c476,486
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency
506,516c506,516
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles
528,538c528,538
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
552c552
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
558,561c558,559
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
563,564c561,562
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
591c589
< system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)
593,594c591,592
< system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.8 # Layer utilization (%)
< sim_ticks 25815000 # Number of ticks simulated
< final_tick 25815000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 25815500 # Number of ticks simulated
> final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 376930 # Simulator instruction rate (inst/s)
< host_op_rate 439541 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 2127142386 # Simulator tick rate (ticks/s)
< host_mem_usage 307352 # Number of bytes of host memory used
< host_seconds 0.01 # Real time elapsed on the host
---
> host_inst_rate 263675 # Simulator instruction rate (inst/s)
> host_op_rate 307555 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1488783160 # Simulator tick rate (ticks/s)
> host_mem_usage 306760 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 557815224 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 309897347 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 867712570 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 557815224 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 557815224 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 557815224 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 309897347 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 867712570 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s)
150c150
< system.cpu.numCycles 51630 # number of cpu cycles simulated
---
> system.cpu.numCycles 51631 # number of cpu cycles simulated
171c171
< system.cpu.num_busy_cycles 51629.998000 # Number of busy cycles
---
> system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles
211c211
< system.cpu.dcache.tags.tagsinuse 82.900177 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use
216,218c216,218
< system.cpu.dcache.tags.occ_blocks::cpu.data 82.900177 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.020239 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.020239 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
297,304c297,304
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles
313,320c313,320
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46142.857143 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 48234.042553 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
323c323
< system.cpu.icache.tags.tagsinuse 114.428477 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use
328,330c328,330
< system.cpu.icache.tags.occ_blocks::cpu.inst 114.428477 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.055873 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.055873 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy
349,354c349,354
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 12588000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 12588000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 12588000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 12588000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 12588000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
367,372c367,372
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52232.365145 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 52232.365145 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 52232.365145 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 52232.365145 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 52232.365145 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
387,392c387,392
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12106000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 12106000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12106000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 12106000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12106000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 12106000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles
399,404c399,404
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50232.365145 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50232.365145 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50232.365145 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 50232.365145 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
407c407
< system.cpu.l2cache.tags.tagsinuse 153.844437 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use
412,413c412,413
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.714938 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 48.129500 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor
443,453c443,453
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11705000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 15969000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 11705000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 18205000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 11705000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 18205000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles
476,486c476,486
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52022.222222 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52016.286645 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52014.285714 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52022.222222 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52014.285714 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency
506,516c506,516
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles
528,538c528,538
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
552c552
< system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
558,561c558,559
< system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::5 382 100.00% 100.00% # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
563,564c561,562
< system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
< system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram
---
> system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
591c589
< system.membus.reqLayer0.occupancy 355000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks)
593,594c591,592
< system.membus.respLayer1.occupancy 3155000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.2 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 6.8 # Layer utilization (%)