1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28648500 # Number of ticks simulated 5final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 484095 # Simulator instruction rate (inst/s) 8host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3030833923 # Simulator tick rate (ticks/s) 10host_mem_usage 267516 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.inst_hits 0 # ITB inst hits 75system.cpu.dtb.inst_misses 0 # ITB inst misses 76system.cpu.dtb.read_hits 0 # DTB read hits 77system.cpu.dtb.read_misses 0 # DTB read misses 78system.cpu.dtb.write_hits 0 # DTB write hits 79system.cpu.dtb.write_misses 0 # DTB write misses 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses 95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000029 # Number of seconds simulated 4sim_ticks 28648500 # Number of ticks simulated 5final_tick 28648500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 484095 # Simulator instruction rate (inst/s) 8host_op_rate 564461 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3030833923 # Simulator tick rate (ticks/s) 10host_mem_usage 267516 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 502644117 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 279246732 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 781890849 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 502644117 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 502644117 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 502644117 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 279246732 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 781890849 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.inst_hits 0 # ITB inst hits 75system.cpu.dtb.inst_misses 0 # ITB inst misses 76system.cpu.dtb.read_hits 0 # DTB read hits 77system.cpu.dtb.read_misses 0 # DTB read misses 78system.cpu.dtb.write_hits 0 # DTB write hits 79system.cpu.dtb.write_misses 0 # DTB write misses 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses 95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28648500 # Cumulative time (in ticks) in various power states 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses
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