Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

stats.txt (11515:c48c7cc5a522)	stats.txt (11530:6e143fd2cabf)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000028 # Number of seconds simulated 4sim_ticks 28298500 # Number of ticks simulated 5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 311400 # Simulator instruction rate (inst/s) 8host_op_rate 363255 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1927478424 # Simulator tick rate (ticks/s) 10host_mem_usage 306584 # Number of bytes of host memory used	7host_inst_rate 377704 # Simulator instruction rate (inst/s) 8host_op_rate 440559 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2337429945 # Simulator tick rate (ticks/s) 10host_mem_usage 308268 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks	11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks
	16system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)	17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)
	33system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
32system.cpu_clk_domain.clock 500 # Clock period in ticks	34system.cpu_clk_domain.clock 500 # Clock period in ticks
	35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses	36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses	66system.cpu.dtb.walker.walks 0 # Table walker walks requested 67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.inst_hits 0 # ITB inst hits 75system.cpu.dtb.inst_misses 0 # ITB inst misses 76system.cpu.dtb.read_hits 0 # DTB read hits 77system.cpu.dtb.read_misses 0 # DTB read misses 78system.cpu.dtb.write_hits 0 # DTB write hits 79system.cpu.dtb.write_misses 0 # DTB write misses 80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 89system.cpu.dtb.read_accesses 0 # DTB read accesses 90system.cpu.dtb.write_accesses 0 # DTB write accesses 91system.cpu.dtb.inst_accesses 0 # ITB inst accesses 92system.cpu.dtb.hits 0 # DTB hits 93system.cpu.dtb.misses 0 # DTB misses 94system.cpu.dtb.accesses 0 # DTB accesses
	95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses	96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
	125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls	126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.itb.read_accesses 0 # DTB read accesses 150system.cpu.itb.write_accesses 0 # DTB write accesses 151system.cpu.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.itb.hits 0 # DTB hits 153system.cpu.itb.misses 0 # DTB misses 154system.cpu.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 13 # Number of system calls
	156system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states
150system.cpu.numCycles 56597 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 159system.cpu.num_int_insts 4624 # number of integer instructions 160system.cpu.num_fp_insts 16 # number of float instructions 161system.cpu.num_int_register_reads 7538 # number of times the integer registers were read 162system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 167system.cpu.num_mem_refs 1965 # number of memory refs 168system.cpu.num_load_insts 1027 # Number of load instructions 169system.cpu.num_store_insts 938 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 1008 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction	157system.cpu.numCycles 56597 # number of cpu cycles simulated 158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 160system.cpu.committedInsts 4566 # Number of instructions committed 161system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 162system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 164system.cpu.num_func_calls 203 # number of times a function call or return occured 165system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 166system.cpu.num_int_insts 4624 # number of integer instructions 167system.cpu.num_fp_insts 16 # number of float instructions 168system.cpu.num_int_register_reads 7538 # number of times the integer registers were read 169system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 172system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 173system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 174system.cpu.num_mem_refs 1965 # number of memory refs 175system.cpu.num_load_insts 1027 # Number of load instructions 176system.cpu.num_store_insts 938 # Number of store instructions 177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 178system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles 179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 181system.cpu.Branches 1008 # Number of branches fetched 182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 183system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 184system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 185system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 193system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 194system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 195system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 196system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 197system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 198system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 199system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 200system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 201system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 202system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 203system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 204system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 205system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 206system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 207system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 208system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 209system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 211system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 212system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 213system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 216system.cpu.op_class::total 5391 # Class of executed instruction
	217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
210system.cpu.dcache.tags.replacements 0 # number of replacements 211system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses	218system.cpu.dcache.tags.replacements 0 # number of replacements 219system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use 220system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 221system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 222system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 224system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor 225system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy 226system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy 227system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 228system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 229system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 230system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 231system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 232system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
	233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 233system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits 234system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits 235system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits 236system.cpu.dcache.overall_hits::total 1764 # number of overall hits 237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 244system.cpu.dcache.overall_misses::total 141 # number of overall misses 245system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles 246system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles 247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles 248system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles 249system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles 250system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles 251system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles 252system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles 253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 261system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 262system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses 263system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 264system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses 265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses 273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency 274system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency 275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 276system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 277system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 278system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 288system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 289system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 290system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 291system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 292system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 293system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 294system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 295system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles 296system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles 297system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles 298system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles 299system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles 300system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles 301system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles 302system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles 303system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 304system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 305system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 306system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 307system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 308system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 309system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 310system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses 311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 312system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 314system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 315system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 316system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 317system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 318system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency	234system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 235system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 236system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 237system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 238system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 239system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 240system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 241system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 242system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits 243system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits 244system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits 245system.cpu.dcache.overall_hits::total 1764 # number of overall hits 246system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 247system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 248system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 249system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 250system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 251system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 252system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 253system.cpu.dcache.overall_misses::total 141 # number of overall misses 254system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles 255system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles 256system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles 257system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles 258system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles 259system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles 260system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles 261system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles 262system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 263system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 264system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 265system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 267system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 268system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 269system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 270system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 271system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses 272system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 273system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses 274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 275system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 277system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 278system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 279system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 280system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 281system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses 282system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency 283system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency 284system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 285system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 286system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 287system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency 288system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency 289system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency 290system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 291system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 292system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 293system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 294system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 295system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 296system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 297system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 298system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 299system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 300system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 301system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 302system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 303system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 304system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles 305system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles 306system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles 307system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles 308system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles 309system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles 310system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles 311system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles 312system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 313system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 314system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 315system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 316system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 317system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 318system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 319system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses 320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency 321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency 322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 325system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency 326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency 327system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
	328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
319system.cpu.icache.tags.replacements 1 # number of replacements 320system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 321system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 322system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 323system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 324system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 325system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 326system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy 327system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy 328system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 329system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 330system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 331system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 332system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 333system.cpu.icache.tags.data_accesses 9453 # Number of data accesses	329system.cpu.icache.tags.replacements 1 # number of replacements 330system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use 331system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 332system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 333system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 334system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 335system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor 336system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy 337system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy 338system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 339system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id 340system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id 341system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 342system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 343system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
	344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
334system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 335system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 336system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 337system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 338system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 339system.cpu.icache.overall_hits::total 4365 # number of overall hits 340system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 341system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 342system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 343system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 344system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 345system.cpu.icache.overall_misses::total 241 # number of overall misses 346system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles 347system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles 348system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles 349system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles 350system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles 351system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles 352system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 353system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 354system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 355system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 356system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 357system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 358system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 359system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 360system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 361system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 362system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 363system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses 364system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency 365system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency 366system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 367system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency 368system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 369system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency 370system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 371system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 372system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 373system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 374system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 375system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 376system.cpu.icache.writebacks::writebacks 1 # number of writebacks 377system.cpu.icache.writebacks::total 1 # number of writebacks 378system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 379system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 380system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 381system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 382system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 383system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 384system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles 385system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles 386system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles 387system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles 388system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles 389system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles 390system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 391system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 392system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 393system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 394system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 395system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 396system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 397system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 398system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 399system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 400system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 401system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency	345system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 346system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 347system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 348system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 349system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 350system.cpu.icache.overall_hits::total 4365 # number of overall hits 351system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 352system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 353system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 354system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 355system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 356system.cpu.icache.overall_misses::total 241 # number of overall misses 357system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles 358system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles 359system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles 360system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles 361system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles 362system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles 363system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 364system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 365system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 366system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 367system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 368system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 369system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 370system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 371system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 372system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 373system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 374system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses 375system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency 376system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency 377system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 378system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency 379system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency 380system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency 381system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 382system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 383system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 384system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 385system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 386system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 387system.cpu.icache.writebacks::writebacks 1 # number of writebacks 388system.cpu.icache.writebacks::total 1 # number of writebacks 389system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 390system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 391system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 392system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 393system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 394system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles 396system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles 397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles 398system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles 399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles 400system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles 401system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 402system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 404system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 406system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency 408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency 409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 410system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency 411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency 412system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
	413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
402system.cpu.l2cache.tags.replacements 0 # number of replacements 403system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 404system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 405system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 406system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 407system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 408system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 409system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor 410system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy 411system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy 412system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy 413system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 414system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 415system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 416system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 417system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 418system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses	414system.cpu.l2cache.tags.replacements 0 # number of replacements 415system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use 416system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 417system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 418system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 419system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor 421system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor 422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy 423system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy 424system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy 425system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id 427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id 428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 429system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 430system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
	431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
419system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits 420system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits 421system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 422system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits 423system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 424system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 425system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 426system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 427system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 428system.cpu.l2cache.overall_hits::total 32 # number of overall hits 429system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 430system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 431system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses 432system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses 433system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses 434system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses 435system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 436system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 437system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 438system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 439system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 440system.cpu.l2cache.overall_misses::total 350 # number of overall misses 441system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles 442system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles 443system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles 444system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles 445system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles 446system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles 447system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles 448system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles 449system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles 450system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles 451system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles 452system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles 453system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 454system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 455system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) 456system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) 457system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) 458system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) 459system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 460system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 461system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 462system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 463system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 464system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 465system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 466system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 467system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses 468system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses 469system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses 470system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses 471system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 472system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 473system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 474system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 475system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 476system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 477system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 478system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 479system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency 480system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency 481system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 482system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 483system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency 484system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 485system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency 486system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency 487system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 488system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency 489system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 490system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 491system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 492system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 493system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 494system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 495system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 496system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 497system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses 498system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses 499system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses 500system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses 501system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 502system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 503system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 504system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 505system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 506system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 507system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles 508system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles 509system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles 510system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles 511system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles 512system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles 513system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles 514system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles 515system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles 516system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles 517system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles 518system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles 519system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 520system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 521system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses 522system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses 523system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses 524system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses 525system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 526system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 527system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 528system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 529system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 530system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 531system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 532system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 533system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency 534system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency 535system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 536system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 537system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 538system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 539system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 540system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 542system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 543system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 544system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 545system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 546system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 547system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 548system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.	432system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits 433system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits 434system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits 435system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits 436system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 437system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 438system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 439system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 440system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 441system.cpu.l2cache.overall_hits::total 32 # number of overall hits 442system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 443system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 444system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses 445system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses 446system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses 447system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses 448system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 449system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 450system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 451system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 452system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 453system.cpu.l2cache.overall_misses::total 350 # number of overall misses 454system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles 455system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles 456system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles 457system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles 458system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles 459system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles 460system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles 461system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles 462system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles 463system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles 464system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles 465system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles 466system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 467system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 468system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses) 469system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses) 470system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses) 471system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses) 472system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 473system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 474system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 475system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 476system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 477system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 478system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 479system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 480system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses 481system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses 482system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses 483system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses 484system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 485system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 486system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 487system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 488system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 489system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 490system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 491system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 492system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency 493system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency 494system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 495system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 496system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency 497system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 498system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency 499system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency 500system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 501system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency 502system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 503system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 504system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 505system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 506system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 507system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 508system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 509system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 510system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses 511system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses 512system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses 513system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses 514system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 515system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 516system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 517system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 518system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 519system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 520system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles 521system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles 522system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles 523system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles 524system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles 525system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles 526system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles 527system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles 528system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles 529system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles 530system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles 531system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles 532system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 533system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 534system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses 535system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses 536system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses 537system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses 538system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 539system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 540system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 541system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 542system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 543system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 544system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 545system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 546system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency 547system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency 548system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 549system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 550system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 552system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 553system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency 554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency 556system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter. 557system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data. 558system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 559system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 560system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 561system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
	562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
549system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 550system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 551system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 552system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 553system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 554system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) 556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 557system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) 558system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) 559system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 560system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) 561system.cpu.toL2Bus.snoops 0 # Total snoops (count) 562system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram 563system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram 564system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram 565system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 566system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram 567system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram 568system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 569system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 570system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 572system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 573system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) 574system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 575system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 576system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 577system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 578system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)	563system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 564system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution 565system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 566system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution 569system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes) 570system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes) 573system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.snoops 0 # Total snoops (count) 576system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram 577system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram 578system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram 579system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 580system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram 581system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram 582system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 583system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 584system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 587system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks) 588system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 589system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 590system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 591system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 592system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)
	593system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states
579system.membus.trans_dist::ReadResp 307 # Transaction distribution 580system.membus.trans_dist::ReadExReq 43 # Transaction distribution 581system.membus.trans_dist::ReadExResp 43 # Transaction distribution 582system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution 583system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 584system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 585system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 586system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 587system.membus.snoops 0 # Total snoops (count) 588system.membus.snoop_fanout::samples 350 # Request fanout histogram 589system.membus.snoop_fanout::mean 0 # Request fanout histogram 590system.membus.snoop_fanout::stdev 0 # Request fanout histogram 591system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 592system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram 593system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 594system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 595system.membus.snoop_fanout::min_value 0 # Request fanout histogram 596system.membus.snoop_fanout::max_value 0 # Request fanout histogram 597system.membus.snoop_fanout::total 350 # Request fanout histogram 598system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) 599system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 600system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) 601system.membus.respLayer1.utilization 6.2 # Layer utilization (%) 602 603---------- End Simulation Statistics ----------	594system.membus.trans_dist::ReadResp 307 # Transaction distribution 595system.membus.trans_dist::ReadExReq 43 # Transaction distribution 596system.membus.trans_dist::ReadExResp 43 # Transaction distribution 597system.membus.trans_dist::ReadSharedReq 307 # Transaction distribution 598system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 599system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 600system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 601system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 602system.membus.snoops 0 # Total snoops (count) 603system.membus.snoop_fanout::samples 350 # Request fanout histogram 604system.membus.snoop_fanout::mean 0 # Request fanout histogram 605system.membus.snoop_fanout::stdev 0 # Request fanout histogram 606system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 607system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram 608system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 609system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 610system.membus.snoop_fanout::min_value 0 # Request fanout histogram 611system.membus.snoop_fanout::max_value 0 # Request fanout histogram 612system.membus.snoop_fanout::total 350 # Request fanout histogram 613system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) 614system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) 615system.membus.respLayer1.occupancy 1750000 # Layer occupancy (ticks) 616system.membus.respLayer1.utilization 6.2 # Layer utilization (%) 617 618---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000028 # Number of seconds simulated
4sim_ticks 28298500 # Number of ticks simulated
5final_tick 28298500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 311400 # Simulator instruction rate (inst/s)
8host_op_rate 363255 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1927478424 # Simulator tick rate (ticks/s)
10host_mem_usage 306584 # Number of bytes of host memory used

7host_inst_rate 377704 # Simulator instruction rate (inst/s)
8host_op_rate 440559 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2337429945 # Simulator tick rate (ticks/s)
10host_mem_usage 308268 # Number of bytes of host memory used

11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4566 # Number of instructions simulated
13sim_ops 5330 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks

16system.physmem.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)

17system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
18system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
19system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
20system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
21system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
22system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
23system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
24system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
25system.physmem.bw_read::cpu.inst 508860894 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::cpu.data 282700496 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::total 791561390 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::cpu.inst 508860894 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::total 508860894 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_total::cpu.inst 508860894 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::cpu.data 282700496 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.bw_total::total 791561390 # Total bandwidth to/from this memory (bytes/s)

33system.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

32system.cpu_clk_domain.clock 500 # Clock period in ticks

34system.cpu_clk_domain.clock 500 # Clock period in ticks

35system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

36system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
44system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
45system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
46system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
47system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
48system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
49system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
51system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
52system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
54system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
55system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
56system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
57system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
58system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
59system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
60system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
61system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
62system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
63system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
64system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses

65system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.inst_hits 0 # ITB inst hits
71system.cpu.dtb.inst_misses 0 # ITB inst misses
72system.cpu.dtb.read_hits 0 # DTB read hits
73system.cpu.dtb.read_misses 0 # DTB read misses
74system.cpu.dtb.write_hits 0 # DTB write hits
75system.cpu.dtb.write_misses 0 # DTB write misses
76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses

66system.cpu.dtb.walker.walks 0 # Table walker walks requested
67system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
71system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
72system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
73system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
74system.cpu.dtb.inst_hits 0 # ITB inst hits
75system.cpu.dtb.inst_misses 0 # ITB inst misses
76system.cpu.dtb.read_hits 0 # DTB read hits
77system.cpu.dtb.read_misses 0 # DTB read misses
78system.cpu.dtb.write_hits 0 # DTB write hits
79system.cpu.dtb.write_misses 0 # DTB write misses
80system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
81system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
82system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
83system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
84system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
85system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
86system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
87system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
88system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
89system.cpu.dtb.read_accesses 0 # DTB read accesses
90system.cpu.dtb.write_accesses 0 # DTB write accesses
91system.cpu.dtb.inst_accesses 0 # ITB inst accesses
92system.cpu.dtb.hits 0 # DTB hits
93system.cpu.dtb.misses 0 # DTB misses
94system.cpu.dtb.accesses 0 # DTB accesses

95system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

96system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
104system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
105system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
106system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
107system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
108system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
109system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
110system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
111system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
113system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
114system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
115system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
116system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
117system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
118system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
119system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
120system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
121system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
122system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
123system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
124system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses

125system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.inst_hits 0 # ITB inst hits
129system.cpu.itb.inst_misses 0 # ITB inst misses
130system.cpu.itb.read_hits 0 # DTB read hits
131system.cpu.itb.read_misses 0 # DTB read misses
132system.cpu.itb.write_hits 0 # DTB write hits
133system.cpu.itb.write_misses 0 # DTB write misses
134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 13 # Number of system calls

126system.cpu.itb.walker.walks 0 # Table walker walks requested
127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134system.cpu.itb.inst_hits 0 # ITB inst hits
135system.cpu.itb.inst_misses 0 # ITB inst misses
136system.cpu.itb.read_hits 0 # DTB read hits
137system.cpu.itb.read_misses 0 # DTB read misses
138system.cpu.itb.write_hits 0 # DTB write hits
139system.cpu.itb.write_misses 0 # DTB write misses
140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.itb.read_accesses 0 # DTB read accesses
150system.cpu.itb.write_accesses 0 # DTB write accesses
151system.cpu.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.itb.hits 0 # DTB hits
153system.cpu.itb.misses 0 # DTB misses
154system.cpu.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 13 # Number of system calls

156system.cpu.pwrStateResidencyTicks::ON 28298500 # Cumulative time (in ticks) in various power states

150system.cpu.numCycles 56597 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 4566 # Number of instructions committed
154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
157system.cpu.num_func_calls 203 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
159system.cpu.num_int_insts 4624 # number of integer instructions
160system.cpu.num_fp_insts 16 # number of float instructions
161system.cpu.num_int_register_reads 7538 # number of times the integer registers were read
162system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
167system.cpu.num_mem_refs 1965 # number of memory refs
168system.cpu.num_load_insts 1027 # Number of load instructions
169system.cpu.num_store_insts 938 # Number of store instructions
170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
171system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174system.cpu.Branches 1008 # Number of branches fetched
175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
180system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
181system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
182system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
183system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
184system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
185system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
186system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
187system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
188system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
189system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
190system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
191system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
192system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
193system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
194system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
195system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
196system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
197system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
198system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
199system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
200system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
201system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 5391 # Class of executed instruction

157system.cpu.numCycles 56597 # number of cpu cycles simulated
158system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
159system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
160system.cpu.committedInsts 4566 # Number of instructions committed
161system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
162system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
163system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
164system.cpu.num_func_calls 203 # number of times a function call or return occured
165system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
166system.cpu.num_int_insts 4624 # number of integer instructions
167system.cpu.num_fp_insts 16 # number of float instructions
168system.cpu.num_int_register_reads 7538 # number of times the integer registers were read
169system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
170system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
171system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
172system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read
173system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
174system.cpu.num_mem_refs 1965 # number of memory refs
175system.cpu.num_load_insts 1027 # Number of load instructions
176system.cpu.num_store_insts 938 # Number of store instructions
177system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
178system.cpu.num_busy_cycles 56596.998000 # Number of busy cycles
179system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
180system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
181system.cpu.Branches 1008 # Number of branches fetched
182system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
183system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
184system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
185system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
186system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
187system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
188system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
189system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
190system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
191system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
192system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
193system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
194system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
195system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
196system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
197system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
198system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
199system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
200system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
201system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
202system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
203system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
204system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
205system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
206system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
207system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
208system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
209system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
210system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
211system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
212system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
213system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
214system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
215system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
216system.cpu.op_class::total 5391 # Class of executed instruction

217system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

210system.cpu.dcache.tags.replacements 0 # number of replacements
211system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses

218system.cpu.dcache.tags.replacements 0 # number of replacements
219system.cpu.dcache.tags.tagsinuse 82.647245 # Cycle average of tags in use
220system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
221system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
222system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
223system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
224system.cpu.dcache.tags.occ_blocks::cpu.data 82.647245 # Average occupied blocks per requestor
225system.cpu.dcache.tags.occ_percent::cpu.data 0.020178 # Average percentage of cache occupancy
226system.cpu.dcache.tags.occ_percent::total 0.020178 # Average percentage of cache occupancy
227system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
228system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id
229system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id
230system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
231system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
232system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses

233system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
233system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits
234system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits
235system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits
236system.cpu.dcache.overall_hits::total 1764 # number of overall hits
237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
244system.cpu.dcache.overall_misses::total 141 # number of overall misses
245system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
246system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
248system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
249system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
250system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
251system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
252system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
261system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
262system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses
263system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
264system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses
265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses
266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses
267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses
270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
274system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
276system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
277system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
278system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
279system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
280system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
287system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
288system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
289system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
290system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
291system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
292system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
293system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
294system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
295system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
296system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
297system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
298system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
299system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
300system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
301system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
302system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
303system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
304system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
305system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
306system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
307system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses
308system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
309system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
310system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
311system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
312system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
313system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
314system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
315system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
316system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
317system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
318system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency

234system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
235system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
236system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
237system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
238system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
239system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
240system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
241system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
242system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits
243system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits
244system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits
245system.cpu.dcache.overall_hits::total 1764 # number of overall hits
246system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
247system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
248system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
249system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
250system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
251system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
252system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
253system.cpu.dcache.overall_misses::total 141 # number of overall misses
254system.cpu.dcache.ReadReq_miss_latency::cpu.data 5308000 # number of ReadReq miss cycles
255system.cpu.dcache.ReadReq_miss_latency::total 5308000 # number of ReadReq miss cycles
256system.cpu.dcache.WriteReq_miss_latency::cpu.data 2666000 # number of WriteReq miss cycles
257system.cpu.dcache.WriteReq_miss_latency::total 2666000 # number of WriteReq miss cycles
258system.cpu.dcache.demand_miss_latency::cpu.data 7974000 # number of demand (read+write) miss cycles
259system.cpu.dcache.demand_miss_latency::total 7974000 # number of demand (read+write) miss cycles
260system.cpu.dcache.overall_miss_latency::cpu.data 7974000 # number of overall miss cycles
261system.cpu.dcache.overall_miss_latency::total 7974000 # number of overall miss cycles
262system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
263system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
264system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
265system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
266system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
267system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
268system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
269system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
270system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
271system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses
272system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
273system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses
274system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses
275system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses
276system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
277system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
278system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses
279system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
280system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
281system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
282system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54163.265306 # average ReadReq miss latency
283system.cpu.dcache.ReadReq_avg_miss_latency::total 54163.265306 # average ReadReq miss latency
284system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
285system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
286system.cpu.dcache.demand_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
287system.cpu.dcache.demand_avg_miss_latency::total 56553.191489 # average overall miss latency
288system.cpu.dcache.overall_avg_miss_latency::cpu.data 56553.191489 # average overall miss latency
289system.cpu.dcache.overall_avg_miss_latency::total 56553.191489 # average overall miss latency
290system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
291system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
292system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
293system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
294system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
295system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
296system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
297system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
298system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
299system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
300system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
301system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
302system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
303system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
304system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5210000 # number of ReadReq MSHR miss cycles
305system.cpu.dcache.ReadReq_mshr_miss_latency::total 5210000 # number of ReadReq MSHR miss cycles
306system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2623000 # number of WriteReq MSHR miss cycles
307system.cpu.dcache.WriteReq_mshr_miss_latency::total 2623000 # number of WriteReq MSHR miss cycles
308system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7833000 # number of demand (read+write) MSHR miss cycles
309system.cpu.dcache.demand_mshr_miss_latency::total 7833000 # number of demand (read+write) MSHR miss cycles
310system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7833000 # number of overall MSHR miss cycles
311system.cpu.dcache.overall_mshr_miss_latency::total 7833000 # number of overall MSHR miss cycles
312system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
313system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
314system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
315system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
316system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses
317system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
318system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
319system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
320system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53163.265306 # average ReadReq mshr miss latency
321system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53163.265306 # average ReadReq mshr miss latency
322system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
323system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
324system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
325system.cpu.dcache.demand_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency
326system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55553.191489 # average overall mshr miss latency
327system.cpu.dcache.overall_avg_mshr_miss_latency::total 55553.191489 # average overall mshr miss latency

328system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

319system.cpu.icache.tags.replacements 1 # number of replacements
320system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
321system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
322system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
323system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
324system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
325system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
326system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
327system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
328system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
329system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
330system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
331system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
332system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
333system.cpu.icache.tags.data_accesses 9453 # Number of data accesses

329system.cpu.icache.tags.replacements 1 # number of replacements
330system.cpu.icache.tags.tagsinuse 114.043293 # Cycle average of tags in use
331system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
332system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
333system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
334system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
335system.cpu.icache.tags.occ_blocks::cpu.inst 114.043293 # Average occupied blocks per requestor
336system.cpu.icache.tags.occ_percent::cpu.inst 0.055685 # Average percentage of cache occupancy
337system.cpu.icache.tags.occ_percent::total 0.055685 # Average percentage of cache occupancy
338system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
339system.cpu.icache.tags.age_task_id_blocks_1024::0 96 # Occupied blocks per task id
340system.cpu.icache.tags.age_task_id_blocks_1024::1 144 # Occupied blocks per task id
341system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
342system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
343system.cpu.icache.tags.data_accesses 9453 # Number of data accesses

344system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

334system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
335system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
336system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
337system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
338system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
339system.cpu.icache.overall_hits::total 4365 # number of overall hits
340system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
341system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
342system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
343system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
344system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
345system.cpu.icache.overall_misses::total 241 # number of overall misses
346system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
347system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
348system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
349system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
350system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
351system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
352system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
353system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
354system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
355system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses
356system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses
357system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses
358system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses
359system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses
360system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses
361system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
362system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
363system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
364system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
365system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
366system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
367system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
368system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
369system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
370system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
371system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
372system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
373system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
374system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
375system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
376system.cpu.icache.writebacks::writebacks 1 # number of writebacks
377system.cpu.icache.writebacks::total 1 # number of writebacks
378system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
379system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
380system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
381system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
382system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
383system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
384system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
385system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
386system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
387system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
388system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
389system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
390system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
391system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
392system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
393system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
394system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
395system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
396system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
397system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
398system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
399system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
400system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
401system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency

345system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
346system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
347system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
348system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
349system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
350system.cpu.icache.overall_hits::total 4365 # number of overall hits
351system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
352system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
353system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
354system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
355system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
356system.cpu.icache.overall_misses::total 241 # number of overall misses
357system.cpu.icache.ReadReq_miss_latency::cpu.inst 14179500 # number of ReadReq miss cycles
358system.cpu.icache.ReadReq_miss_latency::total 14179500 # number of ReadReq miss cycles
359system.cpu.icache.demand_miss_latency::cpu.inst 14179500 # number of demand (read+write) miss cycles
360system.cpu.icache.demand_miss_latency::total 14179500 # number of demand (read+write) miss cycles
361system.cpu.icache.overall_miss_latency::cpu.inst 14179500 # number of overall miss cycles
362system.cpu.icache.overall_miss_latency::total 14179500 # number of overall miss cycles
363system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
364system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
365system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
366system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses
367system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses
368system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses
369system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses
370system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses
371system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses
372system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
373system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
374system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
375system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 58836.099585 # average ReadReq miss latency
376system.cpu.icache.ReadReq_avg_miss_latency::total 58836.099585 # average ReadReq miss latency
377system.cpu.icache.demand_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
378system.cpu.icache.demand_avg_miss_latency::total 58836.099585 # average overall miss latency
379system.cpu.icache.overall_avg_miss_latency::cpu.inst 58836.099585 # average overall miss latency
380system.cpu.icache.overall_avg_miss_latency::total 58836.099585 # average overall miss latency
381system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
382system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
383system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
384system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
385system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
386system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
387system.cpu.icache.writebacks::writebacks 1 # number of writebacks
388system.cpu.icache.writebacks::total 1 # number of writebacks
389system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
390system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
391system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
392system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
393system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
394system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
395system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 13938500 # number of ReadReq MSHR miss cycles
396system.cpu.icache.ReadReq_mshr_miss_latency::total 13938500 # number of ReadReq MSHR miss cycles
397system.cpu.icache.demand_mshr_miss_latency::cpu.inst 13938500 # number of demand (read+write) MSHR miss cycles
398system.cpu.icache.demand_mshr_miss_latency::total 13938500 # number of demand (read+write) MSHR miss cycles
399system.cpu.icache.overall_mshr_miss_latency::cpu.inst 13938500 # number of overall MSHR miss cycles
400system.cpu.icache.overall_mshr_miss_latency::total 13938500 # number of overall MSHR miss cycles
401system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
402system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
403system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
404system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
405system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
406system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
407system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 57836.099585 # average ReadReq mshr miss latency
408system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 57836.099585 # average ReadReq mshr miss latency
409system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
410system.cpu.icache.demand_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency
411system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 57836.099585 # average overall mshr miss latency
412system.cpu.icache.overall_avg_mshr_miss_latency::total 57836.099585 # average overall mshr miss latency

413system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

402system.cpu.l2cache.tags.replacements 0 # number of replacements
403system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
404system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
405system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
406system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
407system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
408system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
409system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
410system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
411system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
412system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
413system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
414system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
415system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
416system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
417system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
418system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses

414system.cpu.l2cache.tags.replacements 0 # number of replacements
415system.cpu.l2cache.tags.tagsinuse 153.328645 # Cycle average of tags in use
416system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
417system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
418system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
419system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
420system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.330622 # Average occupied blocks per requestor
421system.cpu.l2cache.tags.occ_blocks::cpu.data 47.998022 # Average occupied blocks per requestor
422system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003214 # Average percentage of cache occupancy
423system.cpu.l2cache.tags.occ_percent::cpu.data 0.001465 # Average percentage of cache occupancy
424system.cpu.l2cache.tags.occ_percent::total 0.004679 # Average percentage of cache occupancy
425system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
426system.cpu.l2cache.tags.age_task_id_blocks_1024::0 116 # Occupied blocks per task id
427system.cpu.l2cache.tags.age_task_id_blocks_1024::1 191 # Occupied blocks per task id
428system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
429system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
430system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses

431system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

419system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
420system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
421system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
422system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits
423system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
424system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
425system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
426system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
427system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
428system.cpu.l2cache.overall_hits::total 32 # number of overall hits
429system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
430system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
431system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
432system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses
433system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses
434system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses
435system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
436system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
437system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
438system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
439system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
440system.cpu.l2cache.overall_misses::total 350 # number of overall misses
441system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
442system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
443system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
444system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
445system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
446system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
447system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
448system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
449system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
450system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
451system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
452system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
453system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
454system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
455system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
456system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses)
457system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses)
458system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses)
459system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
460system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
461system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
462system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
463system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
464system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
465system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
466system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
467system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses
468system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses
469system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses
470system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses
471system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
472system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
473system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
474system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
475system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
476system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
477system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
478system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
479system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
480system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
481system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
482system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
483system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
484system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
485system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
486system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
487system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
488system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
489system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
490system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
491system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
492system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
493system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
494system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
495system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
496system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
497system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
498system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses
499system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses
500system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses
501system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
502system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
503system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
504system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
505system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
506system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
507system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
508system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
509system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
510system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
511system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
512system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
513system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
514system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
515system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
516system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
517system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
518system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
519system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
520system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
521system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
522system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses
523system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses
524system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses
525system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
526system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
527system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
528system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
529system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
530system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
531system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
532system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
533system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
534system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
535system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
536system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
537system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
538system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
539system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
540system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
541system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
542system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
543system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
544system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
545system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
546system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
547system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
548system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

432system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 16 # number of ReadCleanReq hits
433system.cpu.l2cache.ReadCleanReq_hits::total 16 # number of ReadCleanReq hits
434system.cpu.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits
435system.cpu.l2cache.ReadSharedReq_hits::total 16 # number of ReadSharedReq hits
436system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
437system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
438system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
439system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
440system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
441system.cpu.l2cache.overall_hits::total 32 # number of overall hits
442system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
443system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
444system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 225 # number of ReadCleanReq misses
445system.cpu.l2cache.ReadCleanReq_misses::total 225 # number of ReadCleanReq misses
446system.cpu.l2cache.ReadSharedReq_misses::cpu.data 82 # number of ReadSharedReq misses
447system.cpu.l2cache.ReadSharedReq_misses::total 82 # number of ReadSharedReq misses
448system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
449system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
450system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
451system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
452system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
453system.cpu.l2cache.overall_misses::total 350 # number of overall misses
454system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2558500 # number of ReadExReq miss cycles
455system.cpu.l2cache.ReadExReq_miss_latency::total 2558500 # number of ReadExReq miss cycles
456system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 13393000 # number of ReadCleanReq miss cycles
457system.cpu.l2cache.ReadCleanReq_miss_latency::total 13393000 # number of ReadCleanReq miss cycles
458system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 4879000 # number of ReadSharedReq miss cycles
459system.cpu.l2cache.ReadSharedReq_miss_latency::total 4879000 # number of ReadSharedReq miss cycles
460system.cpu.l2cache.demand_miss_latency::cpu.inst 13393000 # number of demand (read+write) miss cycles
461system.cpu.l2cache.demand_miss_latency::cpu.data 7437500 # number of demand (read+write) miss cycles
462system.cpu.l2cache.demand_miss_latency::total 20830500 # number of demand (read+write) miss cycles
463system.cpu.l2cache.overall_miss_latency::cpu.inst 13393000 # number of overall miss cycles
464system.cpu.l2cache.overall_miss_latency::cpu.data 7437500 # number of overall miss cycles
465system.cpu.l2cache.overall_miss_latency::total 20830500 # number of overall miss cycles
466system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
467system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
468system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 241 # number of ReadCleanReq accesses(hits+misses)
469system.cpu.l2cache.ReadCleanReq_accesses::total 241 # number of ReadCleanReq accesses(hits+misses)
470system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 98 # number of ReadSharedReq accesses(hits+misses)
471system.cpu.l2cache.ReadSharedReq_accesses::total 98 # number of ReadSharedReq accesses(hits+misses)
472system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
473system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
474system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
475system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
476system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
477system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
478system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
479system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
480system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadCleanReq accesses
481system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.933610 # miss rate for ReadCleanReq accesses
482system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.836735 # miss rate for ReadSharedReq accesses
483system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.836735 # miss rate for ReadSharedReq accesses
484system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
485system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
486system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
487system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
488system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
489system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
490system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
491system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
492system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59524.444444 # average ReadCleanReq miss latency
493system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59524.444444 # average ReadCleanReq miss latency
494system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
495system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
496system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
497system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
498system.cpu.l2cache.demand_avg_miss_latency::total 59515.714286 # average overall miss latency
499system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59524.444444 # average overall miss latency
500system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
501system.cpu.l2cache.overall_avg_miss_latency::total 59515.714286 # average overall miss latency
502system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
503system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
504system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
505system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
506system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
507system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
508system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
509system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
510system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 225 # number of ReadCleanReq MSHR misses
511system.cpu.l2cache.ReadCleanReq_mshr_misses::total 225 # number of ReadCleanReq MSHR misses
512system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 82 # number of ReadSharedReq MSHR misses
513system.cpu.l2cache.ReadSharedReq_mshr_misses::total 82 # number of ReadSharedReq MSHR misses
514system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
515system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
516system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
517system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
518system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
519system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
520system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2128500 # number of ReadExReq MSHR miss cycles
521system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2128500 # number of ReadExReq MSHR miss cycles
522system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 11143000 # number of ReadCleanReq MSHR miss cycles
523system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 11143000 # number of ReadCleanReq MSHR miss cycles
524system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4059000 # number of ReadSharedReq MSHR miss cycles
525system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4059000 # number of ReadSharedReq MSHR miss cycles
526system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11143000 # number of demand (read+write) MSHR miss cycles
527system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6187500 # number of demand (read+write) MSHR miss cycles
528system.cpu.l2cache.demand_mshr_miss_latency::total 17330500 # number of demand (read+write) MSHR miss cycles
529system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11143000 # number of overall MSHR miss cycles
530system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6187500 # number of overall MSHR miss cycles
531system.cpu.l2cache.overall_mshr_miss_latency::total 17330500 # number of overall MSHR miss cycles
532system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
533system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
534system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadCleanReq accesses
535system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.933610 # mshr miss rate for ReadCleanReq accesses
536system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadSharedReq accesses
537system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.836735 # mshr miss rate for ReadSharedReq accesses
538system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
539system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
540system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
541system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
542system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
543system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
544system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
545system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
546system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49524.444444 # average ReadCleanReq mshr miss latency
547system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49524.444444 # average ReadCleanReq mshr miss latency
548system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
549system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
550system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
551system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
552system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
553system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49524.444444 # average overall mshr miss latency
554system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
555system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49515.714286 # average overall mshr miss latency
556system.cpu.toL2Bus.snoop_filter.tot_requests 383 # Total number of requests made to the snoop filter.
557system.cpu.toL2Bus.snoop_filter.hit_single_requests 32 # Number of requests hitting in the snoop filter with a single holder of the requested data.
558system.cpu.toL2Bus.snoop_filter.hit_multi_requests 1 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
559system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
560system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
561system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.

562system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states

549system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
550system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
551system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
552system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
553system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
554system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
555system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
556system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
557system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes)
558system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes)
559system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
560system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes)
561system.cpu.toL2Bus.snoops 0 # Total snoops (count)
562system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
563system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram
564system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram
565system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
566system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram
567system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram
568system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
569system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
570system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
571system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
572system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
573system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
574system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
575system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
576system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
577system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
578system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)

563system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
564system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
565system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
566system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
567system.cpu.toL2Bus.trans_dist::ReadCleanReq 241 # Transaction distribution
568system.cpu.toL2Bus.trans_dist::ReadSharedReq 98 # Transaction distribution
569system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 483 # Packet count per connected master and slave (bytes)
570system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
571system.cpu.toL2Bus.pkt_count::total 765 # Packet count per connected master and slave (bytes)
572system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15488 # Cumulative packet size per connected master and slave (bytes)
573system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
574system.cpu.toL2Bus.pkt_size::total 24512 # Cumulative packet size per connected master and slave (bytes)
575system.cpu.toL2Bus.snoops 0 # Total snoops (count)
576system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
577system.cpu.toL2Bus.snoop_fanout::mean 0.083770 # Request fanout histogram
578system.cpu.toL2Bus.snoop_fanout::stdev 0.277405 # Request fanout histogram
579system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
580system.cpu.toL2Bus.snoop_fanout::0 350 91.62% 91.62% # Request fanout histogram
581system.cpu.toL2Bus.snoop_fanout::1 32 8.38% 100.00% # Request fanout histogram
582system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
583system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
584system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
585system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
586system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram
587system.cpu.toL2Bus.reqLayer0.occupancy 192500 # Layer occupancy (ticks)
588system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%)
589system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks)
590system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%)
591system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
592system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%)

593system.membus.pwrStateResidencyTicks::UNDEFINED 28298500 # Cumulative time (in ticks) in various power states