Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt

stats.txt (10812:bacaefeb126a)	stats.txt (10827:7f5467f2f8b8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25816500 # Number of ticks simulated 5final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 77759 # Simulator instruction rate (inst/s) 8host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 439383785 # Simulator tick rate (ticks/s) 10host_mem_usage 301384 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls 150system.cpu.numCycles 51633 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 159system.cpu.num_int_insts 4624 # number of integer instructions 160system.cpu.num_fp_insts 16 # number of float instructions 161system.cpu.num_int_register_reads 7573 # number of times the integer registers were read 162system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 167system.cpu.num_mem_refs 1965 # number of memory refs 168system.cpu.num_load_insts 1027 # Number of load instructions 169system.cpu.num_store_insts 938 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 1008 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction 210system.cpu.dcache.tags.replacements 0 # number of replacements 211system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses 225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 233system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits 234system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits 235system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits 236system.cpu.dcache.overall_hits::total 1764 # number of overall hits 237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 244system.cpu.dcache.overall_misses::total 141 # number of overall misses 245system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 246system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 248system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 249system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 250system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 251system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 252system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 261system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 262system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses 263system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 264system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses 265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses 273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 274system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 276system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 277system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 278system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.dcache.fast_writes 0 # number of fast writes performed 288system.cpu.dcache.cache_copies 0 # number of cache copies performed 289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 297system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles 298system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles 299system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles 300system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles 301system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles 302system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles 303system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles 304system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles 305system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 306system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 307system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 308system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 309system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 310system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 311system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 312system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses 313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency 314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency 315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency 316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency 317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency 318system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency 319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency 320system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 322system.cpu.icache.tags.replacements 1 # number of replacements 323system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use 324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 328system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor 329system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy 330system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy 331system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 332system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 333system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 334system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 335system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 336system.cpu.icache.tags.data_accesses 9453 # Number of data accesses 337system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 338system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 339system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 340system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 341system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 342system.cpu.icache.overall_hits::total 4365 # number of overall hits 343system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 344system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 345system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 346system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 347system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 348system.cpu.icache.overall_misses::total 241 # number of overall misses 349system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles 350system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles 351system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles 352system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles 353system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles 354system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles 355system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 356system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 357system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 358system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 359system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 360system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 361system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 362system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 363system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 364system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 365system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 366system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses 367system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency 368system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency 369system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 370system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 382system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 383system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 384system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 385system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 386system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 387system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles 388system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles 389system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles 390system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles 392system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles 393system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 395system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 396system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 397system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 398system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 399system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency 400system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency 401system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency 402system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency 404system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency 405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cpu.l2cache.tags.replacements 0 # number of replacements 407system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use 408system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 409system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 410system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 411system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 412system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor 413system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor 414system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 416system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 420system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 421system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 422system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses 423system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 424system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 425system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 426system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 427system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 428system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 429system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 430system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 431system.cpu.l2cache.overall_hits::total 32 # number of overall hits 432system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 433system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 434system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 435system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 436system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 437system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 438system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 439system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 440system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 441system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 442system.cpu.l2cache.overall_misses::total 350 # number of overall misses 443system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles 444system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles 445system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles 446system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles 447system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles 448system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles 449system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles 450system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles 451system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles 452system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles 453system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles 454system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 455system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 456system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 457system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 458system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 459system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 460system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 461system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 462system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 463system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 464system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 465system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 466system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 467system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 468system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 469system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 470system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 471system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 472system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 473system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 474system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 475system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency 477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency 479system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 480system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 481system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency 482system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 483system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency 484system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency 485system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 486system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency 487system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 488system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 489system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 490system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 491system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 492system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 493system.cpu.l2cache.fast_writes 0 # number of fast writes performed 494system.cpu.l2cache.cache_copies 0 # number of cache copies performed 495system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 496system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 497system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 498system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 499system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 500system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 501system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 502system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 503system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 504system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 505system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 506system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles 507system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles 508system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles 509system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles 510system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles 511system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles 512system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles 513system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles 514system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles 515system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles 516system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles 517system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 518system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 519system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 520system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 521system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 522system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 523system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 524system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 525system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 526system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 527system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 528system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 529system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 530system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 531system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 532system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 533system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 534system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 535system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 536system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 537system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 538system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 539system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 541system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 542system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 544system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 545system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 546system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 547system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 548system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 549system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 550system.cpu.toL2Bus.snoops 0 # Total snoops (count) 551system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000026 # Number of seconds simulated 4sim_ticks 25816500 # Number of ticks simulated 5final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 77759 # Simulator instruction rate (inst/s) 8host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 439383785 # Simulator tick rate (ticks/s) 10host_mem_usage 301384 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4566 # Number of instructions simulated 13sim_ops 5330 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 62system.cpu.dtb.walker.walks 0 # Table walker walks requested 63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.inst_hits 0 # ITB inst hits 71system.cpu.dtb.inst_misses 0 # ITB inst misses 72system.cpu.dtb.read_hits 0 # DTB read hits 73system.cpu.dtb.read_misses 0 # DTB read misses 74system.cpu.dtb.write_hits 0 # DTB write hits 75system.cpu.dtb.write_misses 0 # DTB write misses 76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 85system.cpu.dtb.read_accesses 0 # DTB read accesses 86system.cpu.dtb.write_accesses 0 # DTB write accesses 87system.cpu.dtb.inst_accesses 0 # ITB inst accesses 88system.cpu.dtb.hits 0 # DTB hits 89system.cpu.dtb.misses 0 # DTB misses 90system.cpu.dtb.accesses 0 # DTB accesses 91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 120system.cpu.itb.walker.walks 0 # Table walker walks requested 121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.inst_hits 0 # ITB inst hits 129system.cpu.itb.inst_misses 0 # ITB inst misses 130system.cpu.itb.read_hits 0 # DTB read hits 131system.cpu.itb.read_misses 0 # DTB read misses 132system.cpu.itb.write_hits 0 # DTB write hits 133system.cpu.itb.write_misses 0 # DTB write misses 134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 143system.cpu.itb.read_accesses 0 # DTB read accesses 144system.cpu.itb.write_accesses 0 # DTB write accesses 145system.cpu.itb.inst_accesses 0 # ITB inst accesses 146system.cpu.itb.hits 0 # DTB hits 147system.cpu.itb.misses 0 # DTB misses 148system.cpu.itb.accesses 0 # DTB accesses 149system.cpu.workload.num_syscalls 13 # Number of system calls 150system.cpu.numCycles 51633 # number of cpu cycles simulated 151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 153system.cpu.committedInsts 4566 # Number of instructions committed 154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed 155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 157system.cpu.num_func_calls 203 # number of times a function call or return occured 158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 159system.cpu.num_int_insts 4624 # number of integer instructions 160system.cpu.num_fp_insts 16 # number of float instructions 161system.cpu.num_int_register_reads 7573 # number of times the integer registers were read 162system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read 166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 167system.cpu.num_mem_refs 1965 # number of memory refs 168system.cpu.num_load_insts 1027 # Number of load instructions 169system.cpu.num_store_insts 938 # Number of store instructions 170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 171system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles 172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 174system.cpu.Branches 1008 # Number of branches fetched 175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 180system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 181system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 182system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 183system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 184system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 185system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 186system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 187system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 188system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 189system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 190system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 191system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 192system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 193system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 194system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 195system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 196system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 197system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 198system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 199system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 200system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 201system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 209system.cpu.op_class::total 5391 # Class of executed instruction 210system.cpu.dcache.tags.replacements 0 # number of replacements 211system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use 212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. 213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. 214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. 215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 216system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor 217system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy 218system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy 219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 220system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id 221system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id 222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id 223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses 224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses 225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits 226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits 227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits 228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits 229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 233system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits 234system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits 235system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits 236system.cpu.dcache.overall_hits::total 1764 # number of overall hits 237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses 238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses 239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses 240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses 241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses 242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses 243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses 244system.cpu.dcache.overall_misses::total 141 # number of overall misses 245system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles 246system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles 247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles 248system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles 249system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles 250system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles 251system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles 252system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles 253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) 254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) 255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 261system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses 262system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses 263system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses 264system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses 265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses 266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses 267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses 268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses 269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses 270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses 271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses 272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses 273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency 274system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency 275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 276system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 277system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 278system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency 279system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency 280system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency 281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 287system.cpu.dcache.fast_writes 0 # number of fast writes performed 288system.cpu.dcache.cache_copies 0 # number of cache copies performed 289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses 290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses 291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses 292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses 293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses 297system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles 298system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles 299system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles 300system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles 301system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles 302system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles 303system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles 304system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles 305system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses 306system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses 307system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses 308system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses 309system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses 310system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses 311system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses 312system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses 313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency 314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency 315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency 316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency 317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency 318system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency 319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency 320system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency 321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 322system.cpu.icache.tags.replacements 1 # number of replacements 323system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use 324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. 325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. 326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. 327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 328system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor 329system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy 330system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy 331system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id 332system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id 333system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id 334system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id 335system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses 336system.cpu.icache.tags.data_accesses 9453 # Number of data accesses 337system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits 338system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits 339system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits 340system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits 341system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits 342system.cpu.icache.overall_hits::total 4365 # number of overall hits 343system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses 344system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses 345system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses 346system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses 347system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses 348system.cpu.icache.overall_misses::total 241 # number of overall misses 349system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles 350system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles 351system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles 352system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles 353system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles 354system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles 355system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) 356system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) 357system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses 358system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses 359system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses 360system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses 361system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses 362system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses 363system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses 364system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses 365system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses 366system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses 367system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency 368system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency 369system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 370system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses 382system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses 383system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses 384system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses 385system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses 386system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses 387system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles 388system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles 389system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles 390system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles 391system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles 392system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles 393system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses 394system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses 395system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses 396system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses 397system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses 398system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses 399system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency 400system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency 401system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency 402system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency 404system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency 405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cpu.l2cache.tags.replacements 0 # number of replacements 407system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use 408system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. 409system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. 410system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. 411system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 412system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor 413system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor 414system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy 415system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy 416system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy 417system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id 418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id 419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id 420system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id 421system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses 422system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses 423system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits 424system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits 425system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits 426system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits 427system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits 428system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits 429system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits 430system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits 431system.cpu.l2cache.overall_hits::total 32 # number of overall hits 432system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses 433system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses 434system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses 435system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses 436system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses 437system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses 438system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses 439system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses 440system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses 441system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses 442system.cpu.l2cache.overall_misses::total 350 # number of overall misses 443system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles 444system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles 445system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles 446system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles 447system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles 448system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles 449system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles 450system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles 451system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles 452system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles 453system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles 454system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) 455system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) 456system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) 457system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) 458system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) 459system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses 460system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 461system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses 462system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses 463system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses 464system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses 465system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses 466system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses 467system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses 468system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 469system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 470system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses 471system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses 472system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses 473system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses 474system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses 475system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses 476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency 477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency 479system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 480system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 481system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency 482system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 483system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency 484system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency 485system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 486system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency 487system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 488system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 489system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 490system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 491system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 492system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 493system.cpu.l2cache.fast_writes 0 # number of fast writes performed 494system.cpu.l2cache.cache_copies 0 # number of cache copies performed 495system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses 496system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 497system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses 498system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses 499system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses 500system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses 501system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 502system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 503system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses 504system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 505system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses 506system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles 507system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles 508system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles 509system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles 510system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles 511system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles 512system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles 513system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles 514system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles 515system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles 516system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles 517system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses 518system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses 519system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses 520system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 521system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 522system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses 523system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses 524system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses 525system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses 526system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses 527system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses 528system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 529system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 530system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 531system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 532system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 533system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 534system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 535system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 536system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 537system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 538system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 539system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 540system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution 541system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution 542system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution 543system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution 544system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) 545system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 546system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) 547system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) 548system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) 549system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) 550system.cpu.toL2Bus.snoops 0 # Total snoops (count) 551system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram
552system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram	552system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
553system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 554system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 555system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram	553system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 554system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 555system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
556system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 557system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 558system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram 559system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram	556system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram 557system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
560system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	558system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
561system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 562system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram	559system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 560system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
563system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 564system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 565system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 566system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 567system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 568system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 569system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 570system.membus.trans_dist::ReadReq 307 # Transaction distribution 571system.membus.trans_dist::ReadResp 307 # Transaction distribution 572system.membus.trans_dist::ReadExReq 43 # Transaction distribution 573system.membus.trans_dist::ReadExResp 43 # Transaction distribution 574system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 575system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 576system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 577system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 578system.membus.snoops 0 # Total snoops (count) 579system.membus.snoop_fanout::samples 350 # Request fanout histogram 580system.membus.snoop_fanout::mean 0 # Request fanout histogram 581system.membus.snoop_fanout::stdev 0 # Request fanout histogram 582system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 583system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram 584system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 585system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 586system.membus.snoop_fanout::min_value 0 # Request fanout histogram 587system.membus.snoop_fanout::max_value 0 # Request fanout histogram 588system.membus.snoop_fanout::total 350 # Request fanout histogram 589system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) 590system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 591system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) 592system.membus.respLayer1.utilization 6.8 # Layer utilization (%) 593 594---------- End Simulation Statistics ----------	561system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram 562system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) 563system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 564system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) 565system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 566system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) 567system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) 568system.membus.trans_dist::ReadReq 307 # Transaction distribution 569system.membus.trans_dist::ReadResp 307 # Transaction distribution 570system.membus.trans_dist::ReadExReq 43 # Transaction distribution 571system.membus.trans_dist::ReadExResp 43 # Transaction distribution 572system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) 573system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) 574system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) 575system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) 576system.membus.snoops 0 # Total snoops (count) 577system.membus.snoop_fanout::samples 350 # Request fanout histogram 578system.membus.snoop_fanout::mean 0 # Request fanout histogram 579system.membus.snoop_fanout::stdev 0 # Request fanout histogram 580system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 581system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram 582system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 583system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 584system.membus.snoop_fanout::min_value 0 # Request fanout histogram 585system.membus.snoop_fanout::max_value 0 # Request fanout histogram 586system.membus.snoop_fanout::total 350 # Request fanout histogram 587system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) 588system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 589system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) 590system.membus.respLayer1.utilization 6.8 # Layer utilization (%) 591 592---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000026 # Number of seconds simulated
4sim_ticks 25816500 # Number of ticks simulated
5final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 77759 # Simulator instruction rate (inst/s)
8host_op_rate 90742 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 439383785 # Simulator tick rate (ticks/s)
10host_mem_usage 301384 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host
12sim_insts 4566 # Number of instructions simulated
13sim_ops 5330 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
18system.physmem.bytes_read::total 22400 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 350 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s)
32system.cpu_clk_domain.clock 500 # Clock period in ticks
33system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
34system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
35system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
36system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
37system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
38system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
39system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
41system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
42system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
43system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
44system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
45system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
46system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
47system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
48system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
49system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
50system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
51system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
52system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
53system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
54system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
55system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
56system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
57system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
58system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
59system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
60system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
61system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
62system.cpu.dtb.walker.walks 0 # Table walker walks requested
63system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
64system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
65system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
66system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
67system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
68system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
69system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
70system.cpu.dtb.inst_hits 0 # ITB inst hits
71system.cpu.dtb.inst_misses 0 # ITB inst misses
72system.cpu.dtb.read_hits 0 # DTB read hits
73system.cpu.dtb.read_misses 0 # DTB read misses
74system.cpu.dtb.write_hits 0 # DTB write hits
75system.cpu.dtb.write_misses 0 # DTB write misses
76system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
77system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
78system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
79system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
80system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
81system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
82system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
83system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
84system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
85system.cpu.dtb.read_accesses 0 # DTB read accesses
86system.cpu.dtb.write_accesses 0 # DTB write accesses
87system.cpu.dtb.inst_accesses 0 # ITB inst accesses
88system.cpu.dtb.hits 0 # DTB hits
89system.cpu.dtb.misses 0 # DTB misses
90system.cpu.dtb.accesses 0 # DTB accesses
91system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
92system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
93system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
94system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
95system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
96system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
97system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
99system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
100system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
101system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
102system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
103system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
104system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
105system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
106system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
107system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
108system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
109system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
110system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
111system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
112system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
113system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
114system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
115system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
116system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
117system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
118system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
119system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
120system.cpu.itb.walker.walks 0 # Table walker walks requested
121system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
122system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
123system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
124system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
125system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
126system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
127system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
128system.cpu.itb.inst_hits 0 # ITB inst hits
129system.cpu.itb.inst_misses 0 # ITB inst misses
130system.cpu.itb.read_hits 0 # DTB read hits
131system.cpu.itb.read_misses 0 # DTB read misses
132system.cpu.itb.write_hits 0 # DTB write hits
133system.cpu.itb.write_misses 0 # DTB write misses
134system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
135system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
136system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
137system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
138system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
139system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
140system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
141system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
142system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
143system.cpu.itb.read_accesses 0 # DTB read accesses
144system.cpu.itb.write_accesses 0 # DTB write accesses
145system.cpu.itb.inst_accesses 0 # ITB inst accesses
146system.cpu.itb.hits 0 # DTB hits
147system.cpu.itb.misses 0 # DTB misses
148system.cpu.itb.accesses 0 # DTB accesses
149system.cpu.workload.num_syscalls 13 # Number of system calls
150system.cpu.numCycles 51633 # number of cpu cycles simulated
151system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
152system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
153system.cpu.committedInsts 4566 # Number of instructions committed
154system.cpu.committedOps 5330 # Number of ops (including micro ops) committed
155system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
156system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
157system.cpu.num_func_calls 203 # number of times a function call or return occured
158system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
159system.cpu.num_int_insts 4624 # number of integer instructions
160system.cpu.num_fp_insts 16 # number of float instructions
161system.cpu.num_int_register_reads 7573 # number of times the integer registers were read
162system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
163system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
164system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
165system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read
166system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
167system.cpu.num_mem_refs 1965 # number of memory refs
168system.cpu.num_load_insts 1027 # Number of load instructions
169system.cpu.num_store_insts 938 # Number of store instructions
170system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
171system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles
172system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
173system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
174system.cpu.Branches 1008 # Number of branches fetched
175system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
176system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction
177system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
178system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
179system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
180system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
181system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
182system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
183system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
184system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
185system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
186system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
187system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
188system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
189system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
190system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
191system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
192system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
193system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
194system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
195system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
196system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
197system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
198system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
199system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
200system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
201system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction
202system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction
203system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction
204system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction
205system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
206system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
207system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
208system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
209system.cpu.op_class::total 5391 # Class of executed instruction
210system.cpu.dcache.tags.replacements 0 # number of replacements
211system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use
212system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks.
213system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
214system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks.
215system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
216system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor
217system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy
218system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy
219system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
220system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
221system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id
222system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
223system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses
224system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses
225system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits
226system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits
227system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits
228system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits
229system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits
230system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits
231system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits
232system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits
233system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits
234system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits
235system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits
236system.cpu.dcache.overall_hits::total 1764 # number of overall hits
237system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses
238system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses
239system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses
240system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses
241system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses
242system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses
243system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses
244system.cpu.dcache.overall_misses::total 141 # number of overall misses
245system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles
246system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles
247system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles
248system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles
249system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles
250system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles
251system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles
252system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles
253system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses)
254system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses)
255system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses)
256system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses)
257system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses)
258system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses)
259system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses)
260system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses)
261system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses
262system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses
263system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses
264system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses
265system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses
266system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses
267system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses
268system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses
269system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses
270system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses
271system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses
272system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses
273system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency
274system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency
275system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
276system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
277system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
278system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency
279system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency
280system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency
281system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
282system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
283system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
284system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
285system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
286system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
287system.cpu.dcache.fast_writes 0 # number of fast writes performed
288system.cpu.dcache.cache_copies 0 # number of cache copies performed
289system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
290system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
291system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
292system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
293system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
294system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
295system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
296system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
297system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles
298system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles
299system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles
300system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles
301system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles
302system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles
303system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles
304system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles
305system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses
306system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses
307system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
308system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses
309system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses
310system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses
311system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses
312system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses
313system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency
314system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency
315system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
316system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
317system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
318system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
319system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency
320system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency
321system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
322system.cpu.icache.tags.replacements 1 # number of replacements
323system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use
324system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks.
325system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks.
326system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks.
327system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
328system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor
329system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy
330system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy
331system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id
332system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id
333system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id
334system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id
335system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses
336system.cpu.icache.tags.data_accesses 9453 # Number of data accesses
337system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits
338system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits
339system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits
340system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits
341system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits
342system.cpu.icache.overall_hits::total 4365 # number of overall hits
343system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
344system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
345system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
346system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
347system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
348system.cpu.icache.overall_misses::total 241 # number of overall misses
349system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles
350system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles
351system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles
352system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles
353system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles
354system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles
355system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses)
356system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses)
357system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses
358system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses
359system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses
360system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses
361system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses
362system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses
363system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses
364system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses
365system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses
366system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses
367system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency
368system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency
369system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
370system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency
371system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency
372system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency
373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
379system.cpu.icache.fast_writes 0 # number of fast writes performed
380system.cpu.icache.cache_copies 0 # number of cache copies performed
381system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
382system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
383system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses
384system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses
385system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses
386system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
387system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles
388system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles
389system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles
390system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles
391system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles
392system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles
393system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses
394system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses
395system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses
396system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses
397system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses
398system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses
399system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency
400system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency
401system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
402system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency
404system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency
405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
406system.cpu.l2cache.tags.replacements 0 # number of replacements
407system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use
408system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks.
409system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks.
410system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks.
411system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
412system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor
413system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor
414system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy
415system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
416system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy
417system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id
418system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id
419system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id
420system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id
421system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses
422system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses
423system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
424system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
425system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
426system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
427system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
428system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
429system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
430system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
431system.cpu.l2cache.overall_hits::total 32 # number of overall hits
432system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
433system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses
434system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses
435system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
436system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
437system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
438system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
439system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
440system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
441system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
442system.cpu.l2cache.overall_misses::total 350 # number of overall misses
443system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles
444system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles
445system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles
446system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles
447system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles
448system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles
449system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles
450system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles
451system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles
452system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles
453system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles
454system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
455system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
456system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
457system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
458system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
459system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
460system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
461system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
462system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
463system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
464system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
465system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses
466system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses
467system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses
468system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
469system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
470system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
471system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
472system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses
473system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
474system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
475system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses
476system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency
477system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
478system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency
479system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
480system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
481system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
482system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
483system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency
484system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency
485system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
486system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency
487system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
488system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
489system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
490system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
491system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
492system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
493system.cpu.l2cache.fast_writes 0 # number of fast writes performed
494system.cpu.l2cache.cache_copies 0 # number of cache copies performed
495system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
496system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
497system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
498system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
499system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
500system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
501system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
502system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
503system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
504system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
505system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
506system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles
507system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles
508system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles
509system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles
510system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles
511system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles
512system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles
513system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles
514system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles
515system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles
516system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles
517system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses
518system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses
519system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses
520system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
521system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
522system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
523system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
524system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses
525system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
526system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
527system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses
528system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
529system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
530system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
531system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
532system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
533system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
534system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
535system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
536system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
537system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
538system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
539system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
540system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution
541system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution
542system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution
543system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution
544system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes)
545system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
546system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes)
547system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes)
548system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
549system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes)
550system.cpu.toL2Bus.snoops 0 # Total snoops (count)
551system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram

552system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram

552system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram

553system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
554system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
555system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram

556system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
557system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
558system.cpu.toL2Bus.snoop_fanout::3 382 100.00% 100.00% # Request fanout histogram
559system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram

556system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram
557system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram

560system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

558system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

561system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
562system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram

559system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
560system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram