25a26
> mmap_using_noreserve=false
86a88
> demand_mshr_reserve=1
120a123
> sys=system
138d140
< port=system.cpu.toL2Bus.slave[5]
162a165
> demand_mshr_reserve=1
222a226
> pmu=Null
229a234
> sys=system
247d251
< port=system.cpu.toL2Bus.slave[4]
271a276
> demand_mshr_reserve=1
305c310,312
< header_cycles=1
---
> forward_latency=0
> frontend_latency=1
> response_latency=1
306a314
> snoop_response_latency=1
311c319
< slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
---
> slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
320a329
> drivers=
328a338
> kvmInSE=false
358c368,370
< header_cycles=1
---
> forward_latency=4
> frontend_latency=3
> response_latency=2
359a372
> snoop_response_latency=4
362c375
< width=8
---
> width=16