Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini

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config.ini (10451:3a87241adfb8)	config.ini (10736:4433fb00fa7d)
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem	1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 9time_sync_spin_threshold=100000000 10 11[system] 12type=System 13children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=timing 24mem_ranges= 25memories=system.physmem
	26mmap_using_noreserve=false
26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 34work_end_exit_count=0 35work_item_id=-1 36system_port=system.membus.slave[0] 37 38[system.clk_domain] 39type=SrcClockDomain 40clock=1000 41domain_id=-1 42eventq_index=0 43init_perf_level=0 44voltage_domain=system.voltage_domain 45 46[system.cpu] 47type=TimingSimpleCPU 48children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 49branchPred=Null 50checker=Null 51clk_domain=system.cpu_clk_domain 52cpu_id=0 53do_checkpoint_insts=true 54do_quiesce=true 55do_statistics_insts=true 56dstage2_mmu=system.cpu.dstage2_mmu 57dtb=system.cpu.dtb 58eventq_index=0 59function_trace=false 60function_trace_start=0 61interrupts=system.cpu.interrupts 62isa=system.cpu.isa 63istage2_mmu=system.cpu.istage2_mmu 64itb=system.cpu.itb 65max_insts_all_threads=0 66max_insts_any_thread=0 67max_loads_all_threads=0 68max_loads_any_thread=0 69numThreads=1 70profile=0 71progress_interval=0 72simpoint_start_insts= 73socket_id=0 74switched_out=false 75system=system 76tracer=system.cpu.tracer 77workload=system.cpu.workload 78dcache_port=system.cpu.dcache.cpu_side 79icache_port=system.cpu.icache.cpu_side 80 81[system.cpu.dcache] 82type=BaseCache 83children=tags 84addr_ranges=0:18446744073709551615 85assoc=2 86clk_domain=system.cpu_clk_domain	27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 35work_end_exit_count=0 36work_item_id=-1 37system_port=system.membus.slave[0] 38 39[system.clk_domain] 40type=SrcClockDomain 41clock=1000 42domain_id=-1 43eventq_index=0 44init_perf_level=0 45voltage_domain=system.voltage_domain 46 47[system.cpu] 48type=TimingSimpleCPU 49children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload 50branchPred=Null 51checker=Null 52clk_domain=system.cpu_clk_domain 53cpu_id=0 54do_checkpoint_insts=true 55do_quiesce=true 56do_statistics_insts=true 57dstage2_mmu=system.cpu.dstage2_mmu 58dtb=system.cpu.dtb 59eventq_index=0 60function_trace=false 61function_trace_start=0 62interrupts=system.cpu.interrupts 63isa=system.cpu.isa 64istage2_mmu=system.cpu.istage2_mmu 65itb=system.cpu.itb 66max_insts_all_threads=0 67max_insts_any_thread=0 68max_loads_all_threads=0 69max_loads_any_thread=0 70numThreads=1 71profile=0 72progress_interval=0 73simpoint_start_insts= 74socket_id=0 75switched_out=false 76system=system 77tracer=system.cpu.tracer 78workload=system.cpu.workload 79dcache_port=system.cpu.dcache.cpu_side 80icache_port=system.cpu.icache.cpu_side 81 82[system.cpu.dcache] 83type=BaseCache 84children=tags 85addr_ranges=0:18446744073709551615 86assoc=2 87clk_domain=system.cpu_clk_domain
	88demand_mshr_reserve=1
87eventq_index=0 88forward_snoops=true 89hit_latency=2 90is_top_level=true 91max_miss_count=0 92mshrs=4 93prefetch_on_access=false 94prefetcher=Null 95response_latency=2 96sequential_access=false 97size=262144 98system=system 99tags=system.cpu.dcache.tags 100tgts_per_mshr=20 101two_queue=false 102write_buffers=8 103cpu_side=system.cpu.dcache_port 104mem_side=system.cpu.toL2Bus.slave[1] 105 106[system.cpu.dcache.tags] 107type=LRU 108assoc=2 109block_size=64 110clk_domain=system.cpu_clk_domain 111eventq_index=0 112hit_latency=2 113sequential_access=false 114size=262144 115 116[system.cpu.dstage2_mmu] 117type=ArmStage2MMU 118children=stage2_tlb 119eventq_index=0 120stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb	89eventq_index=0 90forward_snoops=true 91hit_latency=2 92is_top_level=true 93max_miss_count=0 94mshrs=4 95prefetch_on_access=false 96prefetcher=Null 97response_latency=2 98sequential_access=false 99size=262144 100system=system 101tags=system.cpu.dcache.tags 102tgts_per_mshr=20 103two_queue=false 104write_buffers=8 105cpu_side=system.cpu.dcache_port 106mem_side=system.cpu.toL2Bus.slave[1] 107 108[system.cpu.dcache.tags] 109type=LRU 110assoc=2 111block_size=64 112clk_domain=system.cpu_clk_domain 113eventq_index=0 114hit_latency=2 115sequential_access=false 116size=262144 117 118[system.cpu.dstage2_mmu] 119type=ArmStage2MMU 120children=stage2_tlb 121eventq_index=0 122stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
	123sys=system
121tlb=system.cpu.dtb 122 123[system.cpu.dstage2_mmu.stage2_tlb] 124type=ArmTLB 125children=walker 126eventq_index=0 127is_stage2=true 128size=32 129walker=system.cpu.dstage2_mmu.stage2_tlb.walker 130 131[system.cpu.dstage2_mmu.stage2_tlb.walker] 132type=ArmTableWalker 133clk_domain=system.cpu_clk_domain 134eventq_index=0 135is_stage2=true 136num_squash_per_cycle=2 137sys=system	124tlb=system.cpu.dtb 125 126[system.cpu.dstage2_mmu.stage2_tlb] 127type=ArmTLB 128children=walker 129eventq_index=0 130is_stage2=true 131size=32 132walker=system.cpu.dstage2_mmu.stage2_tlb.walker 133 134[system.cpu.dstage2_mmu.stage2_tlb.walker] 135type=ArmTableWalker 136clk_domain=system.cpu_clk_domain 137eventq_index=0 138is_stage2=true 139num_squash_per_cycle=2 140sys=system
138port=system.cpu.toL2Bus.slave[5]
139 140[system.cpu.dtb] 141type=ArmTLB 142children=walker 143eventq_index=0 144is_stage2=false 145size=64 146walker=system.cpu.dtb.walker 147 148[system.cpu.dtb.walker] 149type=ArmTableWalker 150clk_domain=system.cpu_clk_domain 151eventq_index=0 152is_stage2=false 153num_squash_per_cycle=2 154sys=system 155port=system.cpu.toL2Bus.slave[3] 156 157[system.cpu.icache] 158type=BaseCache 159children=tags 160addr_ranges=0:18446744073709551615 161assoc=2 162clk_domain=system.cpu_clk_domain	141 142[system.cpu.dtb] 143type=ArmTLB 144children=walker 145eventq_index=0 146is_stage2=false 147size=64 148walker=system.cpu.dtb.walker 149 150[system.cpu.dtb.walker] 151type=ArmTableWalker 152clk_domain=system.cpu_clk_domain 153eventq_index=0 154is_stage2=false 155num_squash_per_cycle=2 156sys=system 157port=system.cpu.toL2Bus.slave[3] 158 159[system.cpu.icache] 160type=BaseCache 161children=tags 162addr_ranges=0:18446744073709551615 163assoc=2 164clk_domain=system.cpu_clk_domain
	165demand_mshr_reserve=1
163eventq_index=0 164forward_snoops=true 165hit_latency=2 166is_top_level=true 167max_miss_count=0 168mshrs=4 169prefetch_on_access=false 170prefetcher=Null 171response_latency=2 172sequential_access=false 173size=131072 174system=system 175tags=system.cpu.icache.tags 176tgts_per_mshr=20 177two_queue=false 178write_buffers=8 179cpu_side=system.cpu.icache_port 180mem_side=system.cpu.toL2Bus.slave[0] 181 182[system.cpu.icache.tags] 183type=LRU 184assoc=2 185block_size=64 186clk_domain=system.cpu_clk_domain 187eventq_index=0 188hit_latency=2 189sequential_access=false 190size=131072 191 192[system.cpu.interrupts] 193type=ArmInterrupts 194eventq_index=0 195 196[system.cpu.isa] 197type=ArmISA 198eventq_index=0 199fpsid=1090793632 200id_aa64afr0_el1=0 201id_aa64afr1_el1=0 202id_aa64dfr0_el1=1052678 203id_aa64dfr1_el1=0 204id_aa64isar0_el1=0 205id_aa64isar1_el1=0 206id_aa64mmfr0_el1=15728642 207id_aa64mmfr1_el1=0 208id_aa64pfr0_el1=17 209id_aa64pfr1_el1=0 210id_isar0=34607377 211id_isar1=34677009 212id_isar2=555950401 213id_isar3=17899825 214id_isar4=268501314 215id_isar5=0 216id_mmfr0=270536963 217id_mmfr1=0 218id_mmfr2=19070976 219id_mmfr3=34611729 220id_pfr0=49 221id_pfr1=4113 222midr=1091551472	166eventq_index=0 167forward_snoops=true 168hit_latency=2 169is_top_level=true 170max_miss_count=0 171mshrs=4 172prefetch_on_access=false 173prefetcher=Null 174response_latency=2 175sequential_access=false 176size=131072 177system=system 178tags=system.cpu.icache.tags 179tgts_per_mshr=20 180two_queue=false 181write_buffers=8 182cpu_side=system.cpu.icache_port 183mem_side=system.cpu.toL2Bus.slave[0] 184 185[system.cpu.icache.tags] 186type=LRU 187assoc=2 188block_size=64 189clk_domain=system.cpu_clk_domain 190eventq_index=0 191hit_latency=2 192sequential_access=false 193size=131072 194 195[system.cpu.interrupts] 196type=ArmInterrupts 197eventq_index=0 198 199[system.cpu.isa] 200type=ArmISA 201eventq_index=0 202fpsid=1090793632 203id_aa64afr0_el1=0 204id_aa64afr1_el1=0 205id_aa64dfr0_el1=1052678 206id_aa64dfr1_el1=0 207id_aa64isar0_el1=0 208id_aa64isar1_el1=0 209id_aa64mmfr0_el1=15728642 210id_aa64mmfr1_el1=0 211id_aa64pfr0_el1=17 212id_aa64pfr1_el1=0 213id_isar0=34607377 214id_isar1=34677009 215id_isar2=555950401 216id_isar3=17899825 217id_isar4=268501314 218id_isar5=0 219id_mmfr0=270536963 220id_mmfr1=0 221id_mmfr2=19070976 222id_mmfr3=34611729 223id_pfr0=49 224id_pfr1=4113 225midr=1091551472
	226pmu=Null
223system=system 224 225[system.cpu.istage2_mmu] 226type=ArmStage2MMU 227children=stage2_tlb 228eventq_index=0 229stage2_tlb=system.cpu.istage2_mmu.stage2_tlb	227system=system 228 229[system.cpu.istage2_mmu] 230type=ArmStage2MMU 231children=stage2_tlb 232eventq_index=0 233stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
	234sys=system
230tlb=system.cpu.itb 231 232[system.cpu.istage2_mmu.stage2_tlb] 233type=ArmTLB 234children=walker 235eventq_index=0 236is_stage2=true 237size=32 238walker=system.cpu.istage2_mmu.stage2_tlb.walker 239 240[system.cpu.istage2_mmu.stage2_tlb.walker] 241type=ArmTableWalker 242clk_domain=system.cpu_clk_domain 243eventq_index=0 244is_stage2=true 245num_squash_per_cycle=2 246sys=system	235tlb=system.cpu.itb 236 237[system.cpu.istage2_mmu.stage2_tlb] 238type=ArmTLB 239children=walker 240eventq_index=0 241is_stage2=true 242size=32 243walker=system.cpu.istage2_mmu.stage2_tlb.walker 244 245[system.cpu.istage2_mmu.stage2_tlb.walker] 246type=ArmTableWalker 247clk_domain=system.cpu_clk_domain 248eventq_index=0 249is_stage2=true 250num_squash_per_cycle=2 251sys=system
247port=system.cpu.toL2Bus.slave[4]
248 249[system.cpu.itb] 250type=ArmTLB 251children=walker 252eventq_index=0 253is_stage2=false 254size=64 255walker=system.cpu.itb.walker 256 257[system.cpu.itb.walker] 258type=ArmTableWalker 259clk_domain=system.cpu_clk_domain 260eventq_index=0 261is_stage2=false 262num_squash_per_cycle=2 263sys=system 264port=system.cpu.toL2Bus.slave[2] 265 266[system.cpu.l2cache] 267type=BaseCache 268children=tags 269addr_ranges=0:18446744073709551615 270assoc=8 271clk_domain=system.cpu_clk_domain	252 253[system.cpu.itb] 254type=ArmTLB 255children=walker 256eventq_index=0 257is_stage2=false 258size=64 259walker=system.cpu.itb.walker 260 261[system.cpu.itb.walker] 262type=ArmTableWalker 263clk_domain=system.cpu_clk_domain 264eventq_index=0 265is_stage2=false 266num_squash_per_cycle=2 267sys=system 268port=system.cpu.toL2Bus.slave[2] 269 270[system.cpu.l2cache] 271type=BaseCache 272children=tags 273addr_ranges=0:18446744073709551615 274assoc=8 275clk_domain=system.cpu_clk_domain
	276demand_mshr_reserve=1
272eventq_index=0 273forward_snoops=true 274hit_latency=20 275is_top_level=false 276max_miss_count=0 277mshrs=20 278prefetch_on_access=false 279prefetcher=Null 280response_latency=20 281sequential_access=false 282size=2097152 283system=system 284tags=system.cpu.l2cache.tags 285tgts_per_mshr=12 286two_queue=false 287write_buffers=8 288cpu_side=system.cpu.toL2Bus.master[0] 289mem_side=system.membus.slave[1] 290 291[system.cpu.l2cache.tags] 292type=LRU 293assoc=8 294block_size=64 295clk_domain=system.cpu_clk_domain 296eventq_index=0 297hit_latency=20 298sequential_access=false 299size=2097152 300 301[system.cpu.toL2Bus] 302type=CoherentXBar 303clk_domain=system.cpu_clk_domain 304eventq_index=0	277eventq_index=0 278forward_snoops=true 279hit_latency=20 280is_top_level=false 281max_miss_count=0 282mshrs=20 283prefetch_on_access=false 284prefetcher=Null 285response_latency=20 286sequential_access=false 287size=2097152 288system=system 289tags=system.cpu.l2cache.tags 290tgts_per_mshr=12 291two_queue=false 292write_buffers=8 293cpu_side=system.cpu.toL2Bus.master[0] 294mem_side=system.membus.slave[1] 295 296[system.cpu.l2cache.tags] 297type=LRU 298assoc=8 299block_size=64 300clk_domain=system.cpu_clk_domain 301eventq_index=0 302hit_latency=20 303sequential_access=false 304size=2097152 305 306[system.cpu.toL2Bus] 307type=CoherentXBar 308clk_domain=system.cpu_clk_domain 309eventq_index=0
305header_cycles=1	310forward_latency=0 311frontend_latency=1 312response_latency=1
306snoop_filter=Null	313snoop_filter=Null
	314snoop_response_latency=1
307system=system 308use_default_range=false 309width=32 310master=system.cpu.l2cache.cpu_side	315system=system 316use_default_range=false 317width=32 318master=system.cpu.l2cache.cpu_side
311slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port	319slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port
312 313[system.cpu.tracer] 314type=ExeTracer 315eventq_index=0 316 317[system.cpu.workload] 318type=LiveProcess 319cmd=hello 320cwd=	320 321[system.cpu.tracer] 322type=ExeTracer 323eventq_index=0 324 325[system.cpu.workload] 326type=LiveProcess 327cmd=hello 328cwd=
	329drivers=
321egid=100 322env= 323errout=cerr 324euid=100 325eventq_index=0 326executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 327gid=100 328input=cin	330egid=100 331env= 332errout=cerr 333euid=100 334eventq_index=0 335executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 336gid=100 337input=cin
	338kvmInSE=false
329max_stack_size=67108864 330output=cout 331pid=100 332ppid=99 333simpoint=0 334system=system 335uid=100 336useArchPT=false 337 338[system.cpu_clk_domain] 339type=SrcClockDomain 340clock=500 341domain_id=-1 342eventq_index=0 343init_perf_level=0 344voltage_domain=system.voltage_domain 345 346[system.dvfs_handler] 347type=DVFSHandler 348domains= 349enable=false 350eventq_index=0 351sys_clk_domain=system.clk_domain 352transition_latency=100000000 353 354[system.membus] 355type=CoherentXBar 356clk_domain=system.clk_domain 357eventq_index=0	339max_stack_size=67108864 340output=cout 341pid=100 342ppid=99 343simpoint=0 344system=system 345uid=100 346useArchPT=false 347 348[system.cpu_clk_domain] 349type=SrcClockDomain 350clock=500 351domain_id=-1 352eventq_index=0 353init_perf_level=0 354voltage_domain=system.voltage_domain 355 356[system.dvfs_handler] 357type=DVFSHandler 358domains= 359enable=false 360eventq_index=0 361sys_clk_domain=system.clk_domain 362transition_latency=100000000 363 364[system.membus] 365type=CoherentXBar 366clk_domain=system.clk_domain 367eventq_index=0
358header_cycles=1	368forward_latency=4 369frontend_latency=3 370response_latency=2
359snoop_filter=Null	371snoop_filter=Null
	372snoop_response_latency=4
360system=system 361use_default_range=false	373system=system 374use_default_range=false
362width=8	375width=16
363master=system.physmem.port 364slave=system.system_port system.cpu.l2cache.mem_side 365 366[system.physmem] 367type=SimpleMemory 368bandwidth=73.000000 369clk_domain=system.clk_domain 370conf_table_reported=true 371eventq_index=0 372in_addr_map=true 373latency=30000 374latency_var=0 375null=false 376range=0:134217727 377port=system.membus.master[0] 378 379[system.voltage_domain] 380type=VoltageDomain 381eventq_index=0 382voltage=1.000000 383	376master=system.physmem.port 377slave=system.system_port system.cpu.l2cache.mem_side 378 379[system.physmem] 380type=SimpleMemory 381bandwidth=73.000000 382clk_domain=system.clk_domain 383conf_table_reported=true 384eventq_index=0 385in_addr_map=true 386latency=30000 387latency_var=0 388null=false 389range=0:134217727 390port=system.membus.master[0] 391 392[system.voltage_domain] 393type=VoltageDomain 394eventq_index=0 395voltage=1.000000 396