1[root]
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 9 unchanged lines hidden (view full) ---
18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0
--- 45 unchanged lines hidden (view full) ---
79icache_port=system.cpu.icache.cpu_side
80
81[system.cpu.dcache]
82type=BaseCache
83children=tags
84addr_ranges=0:18446744073709551615
85assoc=2
86clk_domain=system.cpu_clk_domain
87eventq_index=0
88forward_snoops=true
89hit_latency=2
90is_top_level=true
91max_miss_count=0
92mshrs=4
93prefetch_on_access=false
94prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
113sequential_access=false
114size=262144
115
116[system.cpu.dstage2_mmu]
117type=ArmStage2MMU
118children=stage2_tlb
119eventq_index=0
120stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
121tlb=system.cpu.dtb
122
123[system.cpu.dstage2_mmu.stage2_tlb]
124type=ArmTLB
125children=walker
126eventq_index=0
127is_stage2=true
128size=32
129walker=system.cpu.dstage2_mmu.stage2_tlb.walker
130
131[system.cpu.dstage2_mmu.stage2_tlb.walker]
132type=ArmTableWalker
133clk_domain=system.cpu_clk_domain
134eventq_index=0
135is_stage2=true
136num_squash_per_cycle=2
137sys=system
138port=system.cpu.toL2Bus.slave[5]
139
140[system.cpu.dtb]
141type=ArmTLB
142children=walker
143eventq_index=0
144is_stage2=false
145size=64
146walker=system.cpu.dtb.walker
--- 8 unchanged lines hidden (view full) ---
155port=system.cpu.toL2Bus.slave[3]
156
157[system.cpu.icache]
158type=BaseCache
159children=tags
160addr_ranges=0:18446744073709551615
161assoc=2
162clk_domain=system.cpu_clk_domain
163eventq_index=0
164forward_snoops=true
165hit_latency=2
166is_top_level=true
167max_miss_count=0
168mshrs=4
169prefetch_on_access=false
170prefetcher=Null
--- 44 unchanged lines hidden (view full) ---
215id_isar5=0
216id_mmfr0=270536963
217id_mmfr1=0
218id_mmfr2=19070976
219id_mmfr3=34611729
220id_pfr0=49
221id_pfr1=4113
222midr=1091551472
223system=system
224
225[system.cpu.istage2_mmu]
226type=ArmStage2MMU
227children=stage2_tlb
228eventq_index=0
229stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
230tlb=system.cpu.itb
231
232[system.cpu.istage2_mmu.stage2_tlb]
233type=ArmTLB
234children=walker
235eventq_index=0
236is_stage2=true
237size=32
238walker=system.cpu.istage2_mmu.stage2_tlb.walker
239
240[system.cpu.istage2_mmu.stage2_tlb.walker]
241type=ArmTableWalker
242clk_domain=system.cpu_clk_domain
243eventq_index=0
244is_stage2=true
245num_squash_per_cycle=2
246sys=system
247port=system.cpu.toL2Bus.slave[4]
248
249[system.cpu.itb]
250type=ArmTLB
251children=walker
252eventq_index=0
253is_stage2=false
254size=64
255walker=system.cpu.itb.walker
--- 8 unchanged lines hidden (view full) ---
264port=system.cpu.toL2Bus.slave[2]
265
266[system.cpu.l2cache]
267type=BaseCache
268children=tags
269addr_ranges=0:18446744073709551615
270assoc=8
271clk_domain=system.cpu_clk_domain
272eventq_index=0
273forward_snoops=true
274hit_latency=20
275is_top_level=false
276max_miss_count=0
277mshrs=20
278prefetch_on_access=false
279prefetcher=Null
--- 17 unchanged lines hidden (view full) ---
297hit_latency=20
298sequential_access=false
299size=2097152
300
301[system.cpu.toL2Bus]
302type=CoherentXBar
303clk_domain=system.cpu_clk_domain
304eventq_index=0
305header_cycles=1
306snoop_filter=Null
307system=system
308use_default_range=false
309width=32
310master=system.cpu.l2cache.cpu_side
311slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
312
313[system.cpu.tracer]
314type=ExeTracer
315eventq_index=0
316
317[system.cpu.workload]
318type=LiveProcess
319cmd=hello
320cwd=
321egid=100
322env=
323errout=cerr
324euid=100
325eventq_index=0
326executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
327gid=100
328input=cin
329max_stack_size=67108864
330output=cout
331pid=100
332ppid=99
333simpoint=0
334system=system
335uid=100
336useArchPT=false
--- 13 unchanged lines hidden (view full) ---
350eventq_index=0
351sys_clk_domain=system.clk_domain
352transition_latency=100000000
353
354[system.membus]
355type=CoherentXBar
356clk_domain=system.clk_domain
357eventq_index=0
358header_cycles=1
359snoop_filter=Null
360system=system
361use_default_range=false
362width=8
363master=system.physmem.port
364slave=system.system_port system.cpu.l2cache.mem_side
365
366[system.physmem]
367type=SimpleMemory
368bandwidth=73.000000
369clk_domain=system.clk_domain
370conf_table_reported=true
--- 13 unchanged lines hidden ---
2type=Root
3children=system
4eventq_index=0
5full_system=false
6sim_quantum=0
7time_sync_enable=false
8time_sync_period=100000000000
--- 9 unchanged lines hidden (view full) ---
18init_param=0
19kernel=
20kernel_addr_check=true
21load_addr_mask=1099511627775
22load_offset=0
23mem_mode=timing
24mem_ranges=
25memories=system.physmem
26num_work_ids=16
27readfile=
28symbolfile=
29work_begin_ckpt_count=0
30work_begin_cpu_id_exit=-1
31work_begin_exit_count=0
32work_cpus_ckpt_count=0
33work_end_ckpt_count=0
--- 45 unchanged lines hidden (view full) ---
79icache_port=system.cpu.icache.cpu_side
80
81[system.cpu.dcache]
82type=BaseCache
83children=tags
84addr_ranges=0:18446744073709551615
85assoc=2
86clk_domain=system.cpu_clk_domain
87eventq_index=0
88forward_snoops=true
89hit_latency=2
90is_top_level=true
91max_miss_count=0
92mshrs=4
93prefetch_on_access=false
94prefetcher=Null
--- 18 unchanged lines hidden (view full) ---
113sequential_access=false
114size=262144
115
116[system.cpu.dstage2_mmu]
117type=ArmStage2MMU
118children=stage2_tlb
119eventq_index=0
120stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb
121tlb=system.cpu.dtb
122
123[system.cpu.dstage2_mmu.stage2_tlb]
124type=ArmTLB
125children=walker
126eventq_index=0
127is_stage2=true
128size=32
129walker=system.cpu.dstage2_mmu.stage2_tlb.walker
130
131[system.cpu.dstage2_mmu.stage2_tlb.walker]
132type=ArmTableWalker
133clk_domain=system.cpu_clk_domain
134eventq_index=0
135is_stage2=true
136num_squash_per_cycle=2
137sys=system
138port=system.cpu.toL2Bus.slave[5]
139
140[system.cpu.dtb]
141type=ArmTLB
142children=walker
143eventq_index=0
144is_stage2=false
145size=64
146walker=system.cpu.dtb.walker
--- 8 unchanged lines hidden (view full) ---
155port=system.cpu.toL2Bus.slave[3]
156
157[system.cpu.icache]
158type=BaseCache
159children=tags
160addr_ranges=0:18446744073709551615
161assoc=2
162clk_domain=system.cpu_clk_domain
163eventq_index=0
164forward_snoops=true
165hit_latency=2
166is_top_level=true
167max_miss_count=0
168mshrs=4
169prefetch_on_access=false
170prefetcher=Null
--- 44 unchanged lines hidden (view full) ---
215id_isar5=0
216id_mmfr0=270536963
217id_mmfr1=0
218id_mmfr2=19070976
219id_mmfr3=34611729
220id_pfr0=49
221id_pfr1=4113
222midr=1091551472
223system=system
224
225[system.cpu.istage2_mmu]
226type=ArmStage2MMU
227children=stage2_tlb
228eventq_index=0
229stage2_tlb=system.cpu.istage2_mmu.stage2_tlb
230tlb=system.cpu.itb
231
232[system.cpu.istage2_mmu.stage2_tlb]
233type=ArmTLB
234children=walker
235eventq_index=0
236is_stage2=true
237size=32
238walker=system.cpu.istage2_mmu.stage2_tlb.walker
239
240[system.cpu.istage2_mmu.stage2_tlb.walker]
241type=ArmTableWalker
242clk_domain=system.cpu_clk_domain
243eventq_index=0
244is_stage2=true
245num_squash_per_cycle=2
246sys=system
247port=system.cpu.toL2Bus.slave[4]
248
249[system.cpu.itb]
250type=ArmTLB
251children=walker
252eventq_index=0
253is_stage2=false
254size=64
255walker=system.cpu.itb.walker
--- 8 unchanged lines hidden (view full) ---
264port=system.cpu.toL2Bus.slave[2]
265
266[system.cpu.l2cache]
267type=BaseCache
268children=tags
269addr_ranges=0:18446744073709551615
270assoc=8
271clk_domain=system.cpu_clk_domain
272eventq_index=0
273forward_snoops=true
274hit_latency=20
275is_top_level=false
276max_miss_count=0
277mshrs=20
278prefetch_on_access=false
279prefetcher=Null
--- 17 unchanged lines hidden (view full) ---
297hit_latency=20
298sequential_access=false
299size=2097152
300
301[system.cpu.toL2Bus]
302type=CoherentXBar
303clk_domain=system.cpu_clk_domain
304eventq_index=0
305header_cycles=1
306snoop_filter=Null
307system=system
308use_default_range=false
309width=32
310master=system.cpu.l2cache.cpu_side
311slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port
312
313[system.cpu.tracer]
314type=ExeTracer
315eventq_index=0
316
317[system.cpu.workload]
318type=LiveProcess
319cmd=hello
320cwd=
321egid=100
322env=
323errout=cerr
324euid=100
325eventq_index=0
326executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello
327gid=100
328input=cin
329max_stack_size=67108864
330output=cout
331pid=100
332ppid=99
333simpoint=0
334system=system
335uid=100
336useArchPT=false
--- 13 unchanged lines hidden (view full) ---
350eventq_index=0
351sys_clk_domain=system.clk_domain
352transition_latency=100000000
353
354[system.membus]
355type=CoherentXBar
356clk_domain=system.clk_domain
357eventq_index=0
358header_cycles=1
359snoop_filter=Null
360system=system
361use_default_range=false
362width=8
363master=system.physmem.port
364slave=system.system_port system.cpu.l2cache.mem_side
365
366[system.physmem]
367type=SimpleMemory
368bandwidth=73.000000
369clk_domain=system.clk_domain
370conf_table_reported=true
--- 13 unchanged lines hidden ---