| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 685428 # Simulator instruction rate (inst/s) 8host_op_rate 801222 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 400788339 # Simulator tick rate (ticks/s) 10host_mem_usage 292412 # Number of bytes of host memory used | 7host_inst_rate 370272 # Simulator instruction rate (inst/s) 8host_op_rate 433210 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 216878622 # Simulator tick rate (ticks/s) 10host_mem_usage 297624 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) |
| 38system.membus.trans_dist::ReadReq 5596 # Transaction distribution 39system.membus.trans_dist::ReadResp 5607 # Transaction distribution 40system.membus.trans_dist::WriteReq 913 # Transaction distribution 41system.membus.trans_dist::WriteResp 913 # Transaction distribution 42system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 43system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 44system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 45system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 50system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 51system.membus.snoops 0 # Total snoops (count) 52system.membus.snoop_fanout::samples 6531 # Request fanout histogram 53system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram 54system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 55system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 56system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 57system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 58system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 59system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 60system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 61system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram 62system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63system.membus.snoop_fanout::min_value 4 # Request fanout histogram 64system.membus.snoop_fanout::max_value 5 # Request fanout histogram 65system.membus.snoop_fanout::total 6531 # Request fanout histogram | |
| 66system.cpu_clk_domain.clock 500 # Clock period in ticks | 38system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 39system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 67system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 69system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 70system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 73system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 74system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 80system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 81system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 82system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 83system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 84system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 85system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 86system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 87system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 47system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 60system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 68system.cpu.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 88system.cpu.dtb.inst_hits 0 # ITB inst hits 89system.cpu.dtb.inst_misses 0 # ITB inst misses 90system.cpu.dtb.read_hits 0 # DTB read hits 91system.cpu.dtb.read_misses 0 # DTB read misses 92system.cpu.dtb.write_hits 0 # DTB write hits 93system.cpu.dtb.write_misses 0 # DTB write misses 94system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 95system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 101system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 102system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 103system.cpu.dtb.read_accesses 0 # DTB read accesses 104system.cpu.dtb.write_accesses 0 # DTB write accesses 105system.cpu.dtb.inst_accesses 0 # ITB inst accesses 106system.cpu.dtb.hits 0 # DTB hits 107system.cpu.dtb.misses 0 # DTB misses 108system.cpu.dtb.accesses 0 # DTB accesses | 76system.cpu.dtb.inst_hits 0 # ITB inst hits 77system.cpu.dtb.inst_misses 0 # ITB inst misses 78system.cpu.dtb.read_hits 0 # DTB read hits 79system.cpu.dtb.read_misses 0 # DTB read misses 80system.cpu.dtb.write_hits 0 # DTB write hits 81system.cpu.dtb.write_misses 0 # DTB write misses 82system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 89system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.dtb.read_accesses 0 # DTB read accesses 92system.cpu.dtb.write_accesses 0 # DTB write accesses 93system.cpu.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.dtb.hits 0 # DTB hits 95system.cpu.dtb.misses 0 # DTB misses 96system.cpu.dtb.accesses 0 # DTB accesses |
| 97system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 109system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 110system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 111system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 112system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 113system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 114system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 115system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 116system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 122system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 123system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 124system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 125system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 126system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 127system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 128system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 129system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 105system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 118system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 126system.cpu.itb.walker.walks 0 # Table walker walks requested 127system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 130system.cpu.itb.inst_hits 0 # ITB inst hits 131system.cpu.itb.inst_misses 0 # ITB inst misses 132system.cpu.itb.read_hits 0 # DTB read hits 133system.cpu.itb.read_misses 0 # DTB read misses 134system.cpu.itb.write_hits 0 # DTB write hits 135system.cpu.itb.write_misses 0 # DTB write misses 136system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 137system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 204system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 205system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 206system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 207system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 208system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 209system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 210system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 211system.cpu.op_class::total 5390 # Class of executed instruction | 134system.cpu.itb.inst_hits 0 # ITB inst hits 135system.cpu.itb.inst_misses 0 # ITB inst misses 136system.cpu.itb.read_hits 0 # DTB read hits 137system.cpu.itb.read_misses 0 # DTB read misses 138system.cpu.itb.write_hits 0 # DTB write hits 139system.cpu.itb.write_misses 0 # DTB write misses 140system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 66 unchanged lines hidden (view full) --- 208system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 209system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 210system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 211system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 212system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 213system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 214system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 215system.cpu.op_class::total 5390 # Class of executed instruction |
| 216system.membus.trans_dist::ReadReq 5596 # Transaction distribution 217system.membus.trans_dist::ReadResp 5607 # Transaction distribution 218system.membus.trans_dist::WriteReq 913 # Transaction distribution 219system.membus.trans_dist::WriteResp 913 # Transaction distribution 220system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 221system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 222system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 223system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 224system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 225system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 226system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 227system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 228system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 229system.membus.snoops 0 # Total snoops (count) 230system.membus.snoop_fanout::samples 6531 # Request fanout histogram 231system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram 232system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 233system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 234system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 235system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 236system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 237system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 238system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 239system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram 240system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 241system.membus.snoop_fanout::min_value 4 # Request fanout histogram 242system.membus.snoop_fanout::max_value 5 # Request fanout histogram 243system.membus.snoop_fanout::total 6531 # Request fanout histogram |
|
| 212 213---------- End Simulation Statistics ---------- | 244 245---------- End Simulation Statistics ---------- |