1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2870500 # Number of ticks simulated
5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2870500 # Number of ticks simulated
5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 122854 # Simulator instruction rate (inst/s)
8host_op_rate 153228 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 76735417 # Simulator tick rate (ticks/s)
10host_mem_usage 275692 # Number of bytes of host memory used
11host_seconds 0.04 # Real time elapsed on the host
| 7host_inst_rate 723203 # Simulator instruction rate (inst/s)
8host_op_rate 900650 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 450384934 # Simulator tick rate (ticks/s)
10host_mem_usage 232532 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
|
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
16system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
20system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
24system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
| 12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
16system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
19system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
20system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
21system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
24system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
25system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
26system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
28system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
30system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
31system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
32system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
33system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
34system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
35system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
|
| 36system.membus.throughput 9251001568 # Throughput (bytes/s)
37system.membus.data_through_bus 26555 # Total data (bytes)
38system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
|
36system.cpu.dtb.inst_hits 0 # ITB inst hits
37system.cpu.dtb.inst_misses 0 # ITB inst misses
38system.cpu.dtb.read_hits 0 # DTB read hits
39system.cpu.dtb.read_misses 0 # DTB read misses
40system.cpu.dtb.write_hits 0 # DTB write hits
41system.cpu.dtb.write_misses 0 # DTB write misses
42system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
43system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
44system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
45system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
46system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
47system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
48system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
49system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
50system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
51system.cpu.dtb.read_accesses 0 # DTB read accesses
52system.cpu.dtb.write_accesses 0 # DTB write accesses
53system.cpu.dtb.inst_accesses 0 # ITB inst accesses
54system.cpu.dtb.hits 0 # DTB hits
55system.cpu.dtb.misses 0 # DTB misses
56system.cpu.dtb.accesses 0 # DTB accesses
57system.cpu.itb.inst_hits 0 # ITB inst hits
58system.cpu.itb.inst_misses 0 # ITB inst misses
59system.cpu.itb.read_hits 0 # DTB read hits
60system.cpu.itb.read_misses 0 # DTB read misses
61system.cpu.itb.write_hits 0 # DTB write hits
62system.cpu.itb.write_misses 0 # DTB write misses
63system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
64system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
65system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
66system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
67system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
68system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
69system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
70system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
71system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
72system.cpu.itb.read_accesses 0 # DTB read accesses
73system.cpu.itb.write_accesses 0 # DTB write accesses
74system.cpu.itb.inst_accesses 0 # ITB inst accesses
75system.cpu.itb.hits 0 # DTB hits
76system.cpu.itb.misses 0 # DTB misses
77system.cpu.itb.accesses 0 # DTB accesses
78system.cpu.workload.num_syscalls 13 # Number of system calls
79system.cpu.numCycles 5742 # number of cpu cycles simulated
80system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
81system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
82system.cpu.committedInsts 4591 # Number of instructions committed
83system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
84system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
85system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
86system.cpu.num_func_calls 203 # number of times a function call or return occured
87system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
88system.cpu.num_int_insts 4976 # number of integer instructions
89system.cpu.num_fp_insts 16 # number of float instructions
90system.cpu.num_int_register_reads 25195 # number of times the integer registers were read
91system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
92system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
93system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
94system.cpu.num_mem_refs 2138 # number of memory refs
95system.cpu.num_load_insts 1200 # Number of load instructions
96system.cpu.num_store_insts 938 # Number of store instructions
97system.cpu.num_idle_cycles 0 # Number of idle cycles
98system.cpu.num_busy_cycles 5742 # Number of busy cycles
99system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
100system.cpu.idle_fraction 0 # Percentage of idle cycles
101
102---------- End Simulation Statistics ----------
| 39system.cpu.dtb.inst_hits 0 # ITB inst hits
40system.cpu.dtb.inst_misses 0 # ITB inst misses
41system.cpu.dtb.read_hits 0 # DTB read hits
42system.cpu.dtb.read_misses 0 # DTB read misses
43system.cpu.dtb.write_hits 0 # DTB write hits
44system.cpu.dtb.write_misses 0 # DTB write misses
45system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
46system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
47system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
48system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
49system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
50system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
51system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
52system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
53system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
54system.cpu.dtb.read_accesses 0 # DTB read accesses
55system.cpu.dtb.write_accesses 0 # DTB write accesses
56system.cpu.dtb.inst_accesses 0 # ITB inst accesses
57system.cpu.dtb.hits 0 # DTB hits
58system.cpu.dtb.misses 0 # DTB misses
59system.cpu.dtb.accesses 0 # DTB accesses
60system.cpu.itb.inst_hits 0 # ITB inst hits
61system.cpu.itb.inst_misses 0 # ITB inst misses
62system.cpu.itb.read_hits 0 # DTB read hits
63system.cpu.itb.read_misses 0 # DTB read misses
64system.cpu.itb.write_hits 0 # DTB write hits
65system.cpu.itb.write_misses 0 # DTB write misses
66system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
67system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
68system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
69system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
70system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
71system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
72system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
73system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
74system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
75system.cpu.itb.read_accesses 0 # DTB read accesses
76system.cpu.itb.write_accesses 0 # DTB write accesses
77system.cpu.itb.inst_accesses 0 # ITB inst accesses
78system.cpu.itb.hits 0 # DTB hits
79system.cpu.itb.misses 0 # DTB misses
80system.cpu.itb.accesses 0 # DTB accesses
81system.cpu.workload.num_syscalls 13 # Number of system calls
82system.cpu.numCycles 5742 # number of cpu cycles simulated
83system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
84system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
85system.cpu.committedInsts 4591 # Number of instructions committed
86system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
87system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
88system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
89system.cpu.num_func_calls 203 # number of times a function call or return occured
90system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
91system.cpu.num_int_insts 4976 # number of integer instructions
92system.cpu.num_fp_insts 16 # number of float instructions
93system.cpu.num_int_register_reads 25195 # number of times the integer registers were read
94system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
95system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
96system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
97system.cpu.num_mem_refs 2138 # number of memory refs
98system.cpu.num_load_insts 1200 # Number of load instructions
99system.cpu.num_store_insts 938 # Number of store instructions
100system.cpu.num_idle_cycles 0 # Number of idle cycles
101system.cpu.num_busy_cycles 5742 # Number of busy cycles
102system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
103system.cpu.idle_fraction 0 # Percentage of idle cycles
104
105---------- End Simulation Statistics ----------
|