1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2875500 # Number of ticks simulated
5final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2875500 # Number of ticks simulated
5final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 126142 # Simulator instruction rate (inst/s)
8host_op_rate 157316 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 78793699 # Simulator tick rate (ticks/s)
10host_mem_usage 212180 # Number of bytes of host memory used
11host_seconds 0.04 # Real time elapsed on the host
| 7host_inst_rate 249779 # Simulator instruction rate (inst/s)
8host_op_rate 311187 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 155712783 # Simulator tick rate (ticks/s)
10host_mem_usage 219320 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
|
12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 22944 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 3648 # Number of bytes written to this memory
17system.physmem.num_reads 5771 # Number of read requests responded to by this memory
18system.physmem.num_writes 924 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39system.cpu.dtb.read_accesses 0 # DTB read accesses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42system.cpu.dtb.hits 0 # DTB hits
43system.cpu.dtb.misses 0 # DTB misses
44system.cpu.dtb.accesses 0 # DTB accesses
45system.cpu.itb.inst_hits 0 # ITB inst hits
46system.cpu.itb.inst_misses 0 # ITB inst misses
47system.cpu.itb.read_hits 0 # DTB read hits
48system.cpu.itb.read_misses 0 # DTB read misses
49system.cpu.itb.write_hits 0 # DTB write hits
50system.cpu.itb.write_misses 0 # DTB write misses
51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 13 # Number of system calls
67system.cpu.numCycles 5752 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.committedInsts 4600 # Number of instructions committed
71system.cpu.committedOps 5739 # Number of ops (including micro ops) committed
72system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
73system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
74system.cpu.num_func_calls 185 # number of times a function call or return occured
75system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
76system.cpu.num_int_insts 4985 # number of integer instructions
77system.cpu.num_fp_insts 16 # number of float instructions
78system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
79system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
80system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
81system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
82system.cpu.num_mem_refs 2139 # number of memory refs
83system.cpu.num_load_insts 1201 # Number of load instructions
84system.cpu.num_store_insts 938 # Number of store instructions
85system.cpu.num_idle_cycles 0 # Number of idle cycles
86system.cpu.num_busy_cycles 5752 # Number of busy cycles
87system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88system.cpu.idle_fraction 0 # Percentage of idle cycles
89
90---------- End Simulation Statistics ----------
| 12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 22944 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 3648 # Number of bytes written to this memory
17system.physmem.num_reads 5771 # Number of read requests responded to by this memory
18system.physmem.num_writes 924 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.dtb.inst_hits 0 # ITB inst hits
25system.cpu.dtb.inst_misses 0 # ITB inst misses
26system.cpu.dtb.read_hits 0 # DTB read hits
27system.cpu.dtb.read_misses 0 # DTB read misses
28system.cpu.dtb.write_hits 0 # DTB write hits
29system.cpu.dtb.write_misses 0 # DTB write misses
30system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
32system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
33system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
34system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
35system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
36system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
37system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
38system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
39system.cpu.dtb.read_accesses 0 # DTB read accesses
40system.cpu.dtb.write_accesses 0 # DTB write accesses
41system.cpu.dtb.inst_accesses 0 # ITB inst accesses
42system.cpu.dtb.hits 0 # DTB hits
43system.cpu.dtb.misses 0 # DTB misses
44system.cpu.dtb.accesses 0 # DTB accesses
45system.cpu.itb.inst_hits 0 # ITB inst hits
46system.cpu.itb.inst_misses 0 # ITB inst misses
47system.cpu.itb.read_hits 0 # DTB read hits
48system.cpu.itb.read_misses 0 # DTB read misses
49system.cpu.itb.write_hits 0 # DTB write hits
50system.cpu.itb.write_misses 0 # DTB write misses
51system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
52system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
53system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
54system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
55system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
56system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
57system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
58system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
59system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
60system.cpu.itb.read_accesses 0 # DTB read accesses
61system.cpu.itb.write_accesses 0 # DTB write accesses
62system.cpu.itb.inst_accesses 0 # ITB inst accesses
63system.cpu.itb.hits 0 # DTB hits
64system.cpu.itb.misses 0 # DTB misses
65system.cpu.itb.accesses 0 # DTB accesses
66system.cpu.workload.num_syscalls 13 # Number of system calls
67system.cpu.numCycles 5752 # number of cpu cycles simulated
68system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
69system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
70system.cpu.committedInsts 4600 # Number of instructions committed
71system.cpu.committedOps 5739 # Number of ops (including micro ops) committed
72system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
73system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
74system.cpu.num_func_calls 185 # number of times a function call or return occured
75system.cpu.num_conditional_control_insts 775 # number of instructions that are conditional controls
76system.cpu.num_int_insts 4985 # number of integer instructions
77system.cpu.num_fp_insts 16 # number of float instructions
78system.cpu.num_int_register_reads 25237 # number of times the integer registers were read
79system.cpu.num_int_register_writes 5345 # number of times the integer registers were written
80system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
81system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
82system.cpu.num_mem_refs 2139 # number of memory refs
83system.cpu.num_load_insts 1201 # Number of load instructions
84system.cpu.num_store_insts 938 # Number of store instructions
85system.cpu.num_idle_cycles 0 # Number of idle cycles
86system.cpu.num_busy_cycles 5752 # Number of busy cycles
87system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
88system.cpu.idle_fraction 0 # Percentage of idle cycles
89
90---------- End Simulation Statistics ----------
|