| config.ini (10451:3a87241adfb8) | config.ini (10736:4433fb00fa7d) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=atomic 24mem_ranges= 25memories=system.physmem | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 9 unchanged lines hidden (view full) --- 18init_param=0 19kernel= 20kernel_addr_check=true 21load_addr_mask=1099511627775 22load_offset=0 23mem_mode=atomic 24mem_ranges= 25memories=system.physmem |
| 26mmap_using_noreserve=false |
|
| 26num_work_ids=16 27readfile= 28symbolfile= 29work_begin_ckpt_count=0 30work_begin_cpu_id_exit=-1 31work_begin_exit_count=0 32work_cpus_ckpt_count=0 33work_end_ckpt_count=0 --- 48 unchanged lines hidden (view full) --- 82dcache_port=system.membus.slave[2] 83icache_port=system.membus.slave[1] 84 85[system.cpu.dstage2_mmu] 86type=ArmStage2MMU 87children=stage2_tlb 88eventq_index=0 89stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb | 27num_work_ids=16 28readfile= 29symbolfile= 30work_begin_ckpt_count=0 31work_begin_cpu_id_exit=-1 32work_begin_exit_count=0 33work_cpus_ckpt_count=0 34work_end_ckpt_count=0 --- 48 unchanged lines hidden (view full) --- 83dcache_port=system.membus.slave[2] 84icache_port=system.membus.slave[1] 85 86[system.cpu.dstage2_mmu] 87type=ArmStage2MMU 88children=stage2_tlb 89eventq_index=0 90stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| 91sys=system |
|
| 90tlb=system.cpu.dtb 91 92[system.cpu.dstage2_mmu.stage2_tlb] 93type=ArmTLB 94children=walker 95eventq_index=0 96is_stage2=true 97size=32 98walker=system.cpu.dstage2_mmu.stage2_tlb.walker 99 100[system.cpu.dstage2_mmu.stage2_tlb.walker] 101type=ArmTableWalker 102clk_domain=system.cpu_clk_domain 103eventq_index=0 104is_stage2=true 105num_squash_per_cycle=2 106sys=system | 92tlb=system.cpu.dtb 93 94[system.cpu.dstage2_mmu.stage2_tlb] 95type=ArmTLB 96children=walker 97eventq_index=0 98is_stage2=true 99size=32 100walker=system.cpu.dstage2_mmu.stage2_tlb.walker 101 102[system.cpu.dstage2_mmu.stage2_tlb.walker] 103type=ArmTableWalker 104clk_domain=system.cpu_clk_domain 105eventq_index=0 106is_stage2=true 107num_squash_per_cycle=2 108sys=system |
| 107port=system.membus.slave[6] | |
| 108 109[system.cpu.dtb] 110type=ArmTLB 111children=walker 112eventq_index=0 113is_stage2=false 114size=64 115walker=system.cpu.dtb.walker --- 33 unchanged lines hidden (view full) --- 149id_isar5=0 150id_mmfr0=270536963 151id_mmfr1=0 152id_mmfr2=19070976 153id_mmfr3=34611729 154id_pfr0=49 155id_pfr1=4113 156midr=1091551472 | 109 110[system.cpu.dtb] 111type=ArmTLB 112children=walker 113eventq_index=0 114is_stage2=false 115size=64 116walker=system.cpu.dtb.walker --- 33 unchanged lines hidden (view full) --- 150id_isar5=0 151id_mmfr0=270536963 152id_mmfr1=0 153id_mmfr2=19070976 154id_mmfr3=34611729 155id_pfr0=49 156id_pfr1=4113 157midr=1091551472 |
| 158pmu=Null |
|
| 157system=system 158 159[system.cpu.istage2_mmu] 160type=ArmStage2MMU 161children=stage2_tlb 162eventq_index=0 163stage2_tlb=system.cpu.istage2_mmu.stage2_tlb | 159system=system 160 161[system.cpu.istage2_mmu] 162type=ArmStage2MMU 163children=stage2_tlb 164eventq_index=0 165stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| 166sys=system |
|
| 164tlb=system.cpu.itb 165 166[system.cpu.istage2_mmu.stage2_tlb] 167type=ArmTLB 168children=walker 169eventq_index=0 170is_stage2=true 171size=32 172walker=system.cpu.istage2_mmu.stage2_tlb.walker 173 174[system.cpu.istage2_mmu.stage2_tlb.walker] 175type=ArmTableWalker 176clk_domain=system.cpu_clk_domain 177eventq_index=0 178is_stage2=true 179num_squash_per_cycle=2 180sys=system | 167tlb=system.cpu.itb 168 169[system.cpu.istage2_mmu.stage2_tlb] 170type=ArmTLB 171children=walker 172eventq_index=0 173is_stage2=true 174size=32 175walker=system.cpu.istage2_mmu.stage2_tlb.walker 176 177[system.cpu.istage2_mmu.stage2_tlb.walker] 178type=ArmTableWalker 179clk_domain=system.cpu_clk_domain 180eventq_index=0 181is_stage2=true 182num_squash_per_cycle=2 183sys=system |
| 181port=system.membus.slave[5] | |
| 182 183[system.cpu.itb] 184type=ArmTLB 185children=walker 186eventq_index=0 187is_stage2=false 188size=64 189walker=system.cpu.itb.walker --- 10 unchanged lines hidden (view full) --- 200[system.cpu.tracer] 201type=ExeTracer 202eventq_index=0 203 204[system.cpu.workload] 205type=LiveProcess 206cmd=hello 207cwd= | 184 185[system.cpu.itb] 186type=ArmTLB 187children=walker 188eventq_index=0 189is_stage2=false 190size=64 191walker=system.cpu.itb.walker --- 10 unchanged lines hidden (view full) --- 202[system.cpu.tracer] 203type=ExeTracer 204eventq_index=0 205 206[system.cpu.workload] 207type=LiveProcess 208cmd=hello 209cwd= |
| 210drivers= |
|
| 208egid=100 209env= 210errout=cerr 211euid=100 212eventq_index=0 213executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 214gid=100 215input=cin | 211egid=100 212env= 213errout=cerr 214euid=100 215eventq_index=0 216executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/arm/linux/hello 217gid=100 218input=cin |
| 219kvmInSE=false |
|
| 216max_stack_size=67108864 217output=cout 218pid=100 219ppid=99 220simpoint=0 221system=system 222uid=100 223useArchPT=false --- 13 unchanged lines hidden (view full) --- 237eventq_index=0 238sys_clk_domain=system.clk_domain 239transition_latency=100000000 240 241[system.membus] 242type=CoherentXBar 243clk_domain=system.clk_domain 244eventq_index=0 | 220max_stack_size=67108864 221output=cout 222pid=100 223ppid=99 224simpoint=0 225system=system 226uid=100 227useArchPT=false --- 13 unchanged lines hidden (view full) --- 241eventq_index=0 242sys_clk_domain=system.clk_domain 243transition_latency=100000000 244 245[system.membus] 246type=CoherentXBar 247clk_domain=system.clk_domain 248eventq_index=0 |
| 245header_cycles=1 | 249forward_latency=4 250frontend_latency=3 251response_latency=2 |
| 246snoop_filter=Null | 252snoop_filter=Null |
| 253snoop_response_latency=4 |
|
| 247system=system 248use_default_range=false | 254system=system 255use_default_range=false |
| 249width=8 | 256width=16 |
| 250master=system.physmem.port | 257master=system.physmem.port |
| 251slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.istage2_mmu.stage2_tlb.walker.port system.cpu.dstage2_mmu.stage2_tlb.walker.port | 258slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| 252 253[system.physmem] 254type=SimpleMemory 255bandwidth=73.000000 256clk_domain=system.clk_domain 257conf_table_reported=true 258eventq_index=0 259in_addr_map=true 260latency=30000 261latency_var=0 262null=false 263range=0:134217727 264port=system.membus.master[0] 265 266[system.voltage_domain] 267type=VoltageDomain 268eventq_index=0 269voltage=1.000000 270 | 259 260[system.physmem] 261type=SimpleMemory 262bandwidth=73.000000 263clk_domain=system.clk_domain 264conf_table_reported=true 265eventq_index=0 266in_addr_map=true 267latency=30000 268latency_var=0 269null=false 270range=0:134217727 271port=system.membus.master[0] 272 273[system.voltage_domain] 274type=VoltageDomain 275eventq_index=0 276voltage=1.000000 277 |