| stats.txt (11687:b3d5f0e9e258) | stats.txt (11955:1170d039b31e) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2695000 # Number of ticks simulated 5final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 707147 # Simulator instruction rate (inst/s) 8host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) --- 144 unchanged lines hidden (view full) --- 153system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.checker.itb.read_accesses 0 # DTB read accesses 156system.cpu.checker.itb.write_accesses 0 # DTB write accesses 157system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.checker.itb.hits 0 # DTB hits 159system.cpu.checker.itb.misses 0 # DTB misses 160system.cpu.checker.itb.accesses 0 # DTB accesses | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2695000 # Number of ticks simulated 5final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 707147 # Simulator instruction rate (inst/s) 8host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) --- 144 unchanged lines hidden (view full) --- 153system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.checker.itb.read_accesses 0 # DTB read accesses 156system.cpu.checker.itb.write_accesses 0 # DTB write accesses 157system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.checker.itb.hits 0 # DTB hits 159system.cpu.checker.itb.misses 0 # DTB misses 160system.cpu.checker.itb.accesses 0 # DTB accesses |
| 161system.cpu.workload.num_syscalls 13 # Number of system calls | 161system.cpu.workload.numSyscalls 13 # Number of system calls |
| 162system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 163system.cpu.checker.numCycles 0 # number of cpu cycles simulated 164system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 167system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 168system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 169system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst --- 215 unchanged lines hidden --- | 162system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 163system.cpu.checker.numCycles 0 # number of cpu cycles simulated 164system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 167system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 168system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 169system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst --- 215 unchanged lines hidden --- |