| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 582910 # Simulator instruction rate (inst/s) 8host_op_rate 681582 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 341032781 # Simulator tick rate (ticks/s) 10host_mem_usage 293692 # Number of bytes of host memory used | 7host_inst_rate 396323 # Simulator instruction rate (inst/s) 8host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 232084410 # Simulator tick rate (ticks/s) 10host_mem_usage 298640 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory --- 11 unchanged lines hidden (view full) --- 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) |
| 38system.membus.trans_dist::ReadReq 5596 # Transaction distribution 39system.membus.trans_dist::ReadResp 5607 # Transaction distribution 40system.membus.trans_dist::WriteReq 913 # Transaction distribution 41system.membus.trans_dist::WriteResp 913 # Transaction distribution 42system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 43system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 44system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 45system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 46system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 47system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 48system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 49system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 50system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 51system.membus.snoops 0 # Total snoops (count) 52system.membus.snoop_fanout::samples 6531 # Request fanout histogram 53system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram 54system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 55system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 56system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 57system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 58system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 59system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 60system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 61system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram 62system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 63system.membus.snoop_fanout::min_value 4 # Request fanout histogram 64system.membus.snoop_fanout::max_value 5 # Request fanout histogram 65system.membus.snoop_fanout::total 6531 # Request fanout histogram | |
| 66system.cpu_clk_domain.clock 500 # Clock period in ticks | 38system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 39system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 67system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 68system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 69system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 70system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 71system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 72system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 73system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 74system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 80system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 81system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 82system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 83system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 84system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 85system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 86system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 87system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 47system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 60system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 68system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 88system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 89system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 90system.cpu.checker.dtb.read_hits 0 # DTB read hits 91system.cpu.checker.dtb.read_misses 0 # DTB read misses 92system.cpu.checker.dtb.write_hits 0 # DTB write hits 93system.cpu.checker.dtb.write_misses 0 # DTB write misses 94system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 95system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 101system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 102system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 103system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 104system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 105system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 106system.cpu.checker.dtb.hits 0 # DTB hits 107system.cpu.checker.dtb.misses 0 # DTB misses 108system.cpu.checker.dtb.accesses 0 # DTB accesses | 76system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 77system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 78system.cpu.checker.dtb.read_hits 0 # DTB read hits 79system.cpu.checker.dtb.read_misses 0 # DTB read misses 80system.cpu.checker.dtb.write_hits 0 # DTB write hits 81system.cpu.checker.dtb.write_misses 0 # DTB write misses 82system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 89system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 92system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 93system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.checker.dtb.hits 0 # DTB hits 95system.cpu.checker.dtb.misses 0 # DTB misses 96system.cpu.checker.dtb.accesses 0 # DTB accesses |
| 97system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 109system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 110system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 111system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 112system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 113system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 114system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 115system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 116system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 122system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 123system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 124system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 125system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 126system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 127system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 128system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 129system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 105system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 118system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 126system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 127system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 130system.cpu.checker.itb.inst_hits 0 # ITB inst hits 131system.cpu.checker.itb.inst_misses 0 # ITB inst misses 132system.cpu.checker.itb.read_hits 0 # DTB read hits 133system.cpu.checker.itb.read_misses 0 # DTB read misses 134system.cpu.checker.itb.write_hits 0 # DTB write hits 135system.cpu.checker.itb.write_misses 0 # DTB write misses 136system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 137system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 147system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 148system.cpu.checker.itb.hits 0 # DTB hits 149system.cpu.checker.itb.misses 0 # DTB misses 150system.cpu.checker.itb.accesses 0 # DTB accesses 151system.cpu.workload.num_syscalls 13 # Number of system calls 152system.cpu.checker.numCycles 0 # number of cpu cycles simulated 153system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 154system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed | 134system.cpu.checker.itb.inst_hits 0 # ITB inst hits 135system.cpu.checker.itb.inst_misses 0 # ITB inst misses 136system.cpu.checker.itb.read_hits 0 # DTB read hits 137system.cpu.checker.itb.read_misses 0 # DTB read misses 138system.cpu.checker.itb.write_hits 0 # DTB write hits 139system.cpu.checker.itb.write_misses 0 # DTB write misses 140system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 9 unchanged lines hidden (view full) --- 151system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.checker.itb.hits 0 # DTB hits 153system.cpu.checker.itb.misses 0 # DTB misses 154system.cpu.checker.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 13 # Number of system calls 156system.cpu.checker.numCycles 0 # number of cpu cycles simulated 157system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 159system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 160system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 161system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 162system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 163system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 164system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 165system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 166system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 155system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 156system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 157system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 158system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 159system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 160system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 161system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 162system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 168system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 169system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 170system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 171system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 172system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 173system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 174system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 175system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 167system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 168system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 173system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 174system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 180system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 181system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 182system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 183system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 184system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 185system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 186system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 187system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 188system.cpu.dtb.walker.walks 0 # Table walker walks requested 189system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 190system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 191system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 192system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 193system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 194system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 195system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 176system.cpu.dtb.inst_hits 0 # ITB inst hits 177system.cpu.dtb.inst_misses 0 # ITB inst misses 178system.cpu.dtb.read_hits 0 # DTB read hits 179system.cpu.dtb.read_misses 0 # DTB read misses 180system.cpu.dtb.write_hits 0 # DTB write hits 181system.cpu.dtb.write_misses 0 # DTB write misses 182system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 183system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 189system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 190system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 191system.cpu.dtb.read_accesses 0 # DTB read accesses 192system.cpu.dtb.write_accesses 0 # DTB write accesses 193system.cpu.dtb.inst_accesses 0 # ITB inst accesses 194system.cpu.dtb.hits 0 # DTB hits 195system.cpu.dtb.misses 0 # DTB misses 196system.cpu.dtb.accesses 0 # DTB accesses | 196system.cpu.dtb.inst_hits 0 # ITB inst hits 197system.cpu.dtb.inst_misses 0 # ITB inst misses 198system.cpu.dtb.read_hits 0 # DTB read hits 199system.cpu.dtb.read_misses 0 # DTB read misses 200system.cpu.dtb.write_hits 0 # DTB write hits 201system.cpu.dtb.write_misses 0 # DTB write misses 202system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 203system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 209system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 210system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 211system.cpu.dtb.read_accesses 0 # DTB read accesses 212system.cpu.dtb.write_accesses 0 # DTB write accesses 213system.cpu.dtb.inst_accesses 0 # ITB inst accesses 214system.cpu.dtb.hits 0 # DTB hits 215system.cpu.dtb.misses 0 # DTB misses 216system.cpu.dtb.accesses 0 # DTB accesses |
| 217system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 218system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 219system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 220system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 221system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 222system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 223system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 224system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
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| 197system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 198system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 199system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 200system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 201system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 202system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 203system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 204system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 210system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 211system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 212system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 213system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 214system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 215system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 216system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 217system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 225system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 226system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 227system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 228system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 229system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 230system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 231system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 232system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 238system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 239system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 240system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 241system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 242system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 243system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 244system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 245system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 246system.cpu.itb.walker.walks 0 # Table walker walks requested 247system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 248system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 249system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 250system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 251system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 252system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 253system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 218system.cpu.itb.inst_hits 0 # ITB inst hits 219system.cpu.itb.inst_misses 0 # ITB inst misses 220system.cpu.itb.read_hits 0 # DTB read hits 221system.cpu.itb.read_misses 0 # DTB read misses 222system.cpu.itb.write_hits 0 # DTB write hits 223system.cpu.itb.write_misses 0 # DTB write misses 224system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 225system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 65 unchanged lines hidden (view full) --- 291system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 292system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 293system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 294system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 295system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 296system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 297system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 298system.cpu.op_class::total 5390 # Class of executed instruction | 254system.cpu.itb.inst_hits 0 # ITB inst hits 255system.cpu.itb.inst_misses 0 # ITB inst misses 256system.cpu.itb.read_hits 0 # DTB read hits 257system.cpu.itb.read_misses 0 # DTB read misses 258system.cpu.itb.write_hits 0 # DTB write hits 259system.cpu.itb.write_misses 0 # DTB write misses 260system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 65 unchanged lines hidden (view full) --- 327system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 328system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 329system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 330system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 331system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 332system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 333system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 334system.cpu.op_class::total 5390 # Class of executed instruction |
| 335system.membus.trans_dist::ReadReq 5596 # Transaction distribution 336system.membus.trans_dist::ReadResp 5607 # Transaction distribution 337system.membus.trans_dist::WriteReq 913 # Transaction distribution 338system.membus.trans_dist::WriteResp 913 # Transaction distribution 339system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 340system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 341system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 342system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 345system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 348system.membus.snoops 0 # Total snoops (count) 349system.membus.snoop_fanout::samples 6531 # Request fanout histogram 350system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram 351system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 354system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 355system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 356system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 357system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 358system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram 359system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 360system.membus.snoop_fanout::min_value 4 # Request fanout histogram 361system.membus.snoop_fanout::max_value 5 # Request fanout histogram 362system.membus.snoop_fanout::total 6531 # Request fanout histogram |
|
| 299 300---------- End Simulation Statistics ---------- | 363 364---------- End Simulation Statistics ---------- |