1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2695000 # Number of ticks simulated 5final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 569364 # Simulator instruction rate (inst/s) 8host_op_rate 666035 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 333433301 # Simulator tick rate (ticks/s) 10host_mem_usage 299296 # Number of bytes of host memory used |
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
16system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
17system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22911 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 23system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory --- 6 unchanged lines hidden (view full) --- 31system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) |
39system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
40system.cpu_clk_domain.clock 500 # Clock period in ticks |
41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 63system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
71system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
72system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 93system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 96system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 97system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.checker.dtb.hits 0 # DTB hits 99system.cpu.checker.dtb.misses 0 # DTB misses 100system.cpu.checker.dtb.accesses 0 # DTB accesses |
101system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 123system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
131system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
132system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 133system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 154system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.checker.itb.read_accesses 0 # DTB read accesses 156system.cpu.checker.itb.write_accesses 0 # DTB write accesses 157system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.checker.itb.hits 0 # DTB hits 159system.cpu.checker.itb.misses 0 # DTB misses 160system.cpu.checker.itb.accesses 0 # DTB accesses 161system.cpu.workload.num_syscalls 13 # Number of system calls |
162system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states |
163system.cpu.checker.numCycles 0 # number of cpu cycles simulated 164system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed |
166system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
167system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 168system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 169system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 170system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 171system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 172system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 173system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 174system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 188system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 189system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 190system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 191system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 192system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 193system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 194system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 195system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
196system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
197system.cpu.dtb.walker.walks 0 # Table walker walks requested 198system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 199system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 200system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 201system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 202system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 203system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 204system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 218system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 219system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 220system.cpu.dtb.read_accesses 0 # DTB read accesses 221system.cpu.dtb.write_accesses 0 # DTB write accesses 222system.cpu.dtb.inst_accesses 0 # ITB inst accesses 223system.cpu.dtb.hits 0 # DTB hits 224system.cpu.dtb.misses 0 # DTB misses 225system.cpu.dtb.accesses 0 # DTB accesses |
226system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
227system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 228system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 229system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 230system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 231system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 232system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 233system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 234system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 248system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 249system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 250system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 251system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 252system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 253system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 254system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 255system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
256system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
257system.cpu.itb.walker.walks 0 # Table walker walks requested 258system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 259system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 260system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 261system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 262system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 263system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 264system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 278system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 279system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.inst_accesses 0 # ITB inst accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses |
286system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states |
287system.cpu.numCycles 5391 # number of cpu cycles simulated 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 290system.cpu.committedInsts 4592 # Number of instructions committed 291system.cpu.committedOps 5378 # Number of ops (including micro ops) committed 292system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 293system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 294system.cpu.num_func_calls 203 # number of times a function call or return occured --- 44 unchanged lines hidden (view full) --- 339system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 340system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 341system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 342system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 343system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 344system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 345system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 346system.cpu.op_class::total 5391 # Class of executed instruction |
347system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states |
348system.membus.trans_dist::ReadReq 5597 # Transaction distribution 349system.membus.trans_dist::ReadResp 5608 # Transaction distribution 350system.membus.trans_dist::WriteReq 913 # Transaction distribution 351system.membus.trans_dist::WriteResp 913 # Transaction distribution 352system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 353system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 354system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 355system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) --- 18 unchanged lines hidden --- |