Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

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sdiff udiff text old ( 11687:b3d5f0e9e258 ) new ( 11955:1170d039b31e )

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stats.txt (11687:b3d5f0e9e258)	stats.txt (11955:1170d039b31e)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2695000 # Number of ticks simulated 5final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 707147 # Simulator instruction rate (inst/s) 8host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 413753949 # Simulator tick rate (ticks/s) 10host_mem_usage 259056 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22911 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 23system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 72system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 81system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 82system.cpu.checker.dtb.read_hits 0 # DTB read hits 83system.cpu.checker.dtb.read_misses 0 # DTB read misses 84system.cpu.checker.dtb.write_hits 0 # DTB write hits 85system.cpu.checker.dtb.write_misses 0 # DTB write misses 86system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 96system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 97system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.checker.dtb.hits 0 # DTB hits 99system.cpu.checker.dtb.misses 0 # DTB misses 100system.cpu.checker.dtb.accesses 0 # DTB accesses 101system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 132system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 133system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.checker.itb.inst_hits 0 # ITB inst hits 141system.cpu.checker.itb.inst_misses 0 # ITB inst misses 142system.cpu.checker.itb.read_hits 0 # DTB read hits 143system.cpu.checker.itb.read_misses 0 # DTB read misses 144system.cpu.checker.itb.write_hits 0 # DTB write hits 145system.cpu.checker.itb.write_misses 0 # DTB write misses 146system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.checker.itb.read_accesses 0 # DTB read accesses 156system.cpu.checker.itb.write_accesses 0 # DTB write accesses 157system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.checker.itb.hits 0 # DTB hits 159system.cpu.checker.itb.misses 0 # DTB misses 160system.cpu.checker.itb.accesses 0 # DTB accesses	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2695000 # Number of ticks simulated 5final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 707147 # Simulator instruction rate (inst/s) 8host_op_rate 826854 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 413753949 # Simulator tick rate (ticks/s) 10host_mem_usage 259056 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 19system.physmem.bytes_read::total 22911 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory 22system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 23system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 24system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory 27system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 28system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 29system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) 34system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) 36system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) 38system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) 39system.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 40system.cpu_clk_domain.clock 500 # Clock period in ticks 41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 47system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 48system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 49system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 50system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 51system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 52system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 53system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 54system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 55system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 56system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 57system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 58system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 59system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 60system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 61system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 62system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 63system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 64system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 65system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 66system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 67system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 68system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 69system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 70system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 71system.cpu.checker.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 72system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 73system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 76system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 77system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 78system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 79system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 80system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 81system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 82system.cpu.checker.dtb.read_hits 0 # DTB read hits 83system.cpu.checker.dtb.read_misses 0 # DTB read misses 84system.cpu.checker.dtb.write_hits 0 # DTB write hits 85system.cpu.checker.dtb.write_misses 0 # DTB write misses 86system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 87system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 88system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 89system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 90system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 91system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 92system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 93system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 94system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 95system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 96system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 97system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 98system.cpu.checker.dtb.hits 0 # DTB hits 99system.cpu.checker.dtb.misses 0 # DTB misses 100system.cpu.checker.dtb.accesses 0 # DTB accesses 101system.cpu.checker.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 105system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 106system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 107system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 108system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 109system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 110system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 111system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 112system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 113system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 114system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 115system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 116system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 117system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 118system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 119system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 120system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 121system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 122system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 123system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 124system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 125system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 126system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 127system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 128system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 129system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 130system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 131system.cpu.checker.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 132system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 133system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 134system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 135system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 136system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 137system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 138system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 139system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 140system.cpu.checker.itb.inst_hits 0 # ITB inst hits 141system.cpu.checker.itb.inst_misses 0 # ITB inst misses 142system.cpu.checker.itb.read_hits 0 # DTB read hits 143system.cpu.checker.itb.read_misses 0 # DTB read misses 144system.cpu.checker.itb.write_hits 0 # DTB write hits 145system.cpu.checker.itb.write_misses 0 # DTB write misses 146system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 147system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 148system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 149system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 150system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 151system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 152system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 153system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 154system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 155system.cpu.checker.itb.read_accesses 0 # DTB read accesses 156system.cpu.checker.itb.write_accesses 0 # DTB write accesses 157system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 158system.cpu.checker.itb.hits 0 # DTB hits 159system.cpu.checker.itb.misses 0 # DTB misses 160system.cpu.checker.itb.accesses 0 # DTB accesses
161system.cpu.workload.num_syscalls 13 # Number of system calls	161system.cpu.workload.numSyscalls 13 # Number of system calls
162system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 163system.cpu.checker.numCycles 0 # number of cpu cycles simulated 164system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 167system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 168system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 169system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 170system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 171system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 172system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 173system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 174system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 175system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 176system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 177system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 178system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 179system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 180system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 181system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 182system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 183system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 184system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 185system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 186system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 187system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 188system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 189system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 190system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 191system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 192system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 193system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 194system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 195system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 196system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 197system.cpu.dtb.walker.walks 0 # Table walker walks requested 198system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 199system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 200system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 201system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 202system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 203system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 204system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 205system.cpu.dtb.inst_hits 0 # ITB inst hits 206system.cpu.dtb.inst_misses 0 # ITB inst misses 207system.cpu.dtb.read_hits 0 # DTB read hits 208system.cpu.dtb.read_misses 0 # DTB read misses 209system.cpu.dtb.write_hits 0 # DTB write hits 210system.cpu.dtb.write_misses 0 # DTB write misses 211system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 212system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 213system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 214system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 215system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 216system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 217system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 218system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 219system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 220system.cpu.dtb.read_accesses 0 # DTB read accesses 221system.cpu.dtb.write_accesses 0 # DTB write accesses 222system.cpu.dtb.inst_accesses 0 # ITB inst accesses 223system.cpu.dtb.hits 0 # DTB hits 224system.cpu.dtb.misses 0 # DTB misses 225system.cpu.dtb.accesses 0 # DTB accesses 226system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 227system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 228system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 229system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 230system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 231system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 232system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 233system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 234system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 235system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 236system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 237system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 238system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 239system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 240system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 241system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 242system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 243system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 244system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 245system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 246system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 247system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 248system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 249system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 250system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 251system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 252system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 253system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 254system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 255system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 256system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 257system.cpu.itb.walker.walks 0 # Table walker walks requested 258system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 259system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 260system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 261system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 262system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 263system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 264system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 265system.cpu.itb.inst_hits 0 # ITB inst hits 266system.cpu.itb.inst_misses 0 # ITB inst misses 267system.cpu.itb.read_hits 0 # DTB read hits 268system.cpu.itb.read_misses 0 # DTB read misses 269system.cpu.itb.write_hits 0 # DTB write hits 270system.cpu.itb.write_misses 0 # DTB write misses 271system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 272system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 273system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 274system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 275system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 276system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 277system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 278system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 279system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.inst_accesses 0 # ITB inst accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses 286system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 287system.cpu.numCycles 5391 # number of cpu cycles simulated 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 290system.cpu.committedInsts 4592 # Number of instructions committed 291system.cpu.committedOps 5378 # Number of ops (including micro ops) committed 292system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 293system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 294system.cpu.num_func_calls 203 # number of times a function call or return occured 295system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 296system.cpu.num_int_insts 4624 # number of integer instructions 297system.cpu.num_fp_insts 16 # number of float instructions 298system.cpu.num_int_register_reads 7572 # number of times the integer registers were read 299system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 300system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 301system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 302system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read 303system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 304system.cpu.num_mem_refs 1965 # number of memory refs 305system.cpu.num_load_insts 1027 # Number of load instructions 306system.cpu.num_store_insts 938 # Number of store instructions 307system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 308system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles 309system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 310system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 311system.cpu.Branches 1008 # Number of branches fetched 312system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 313system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 314system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 315system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 316system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 317system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 318system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 319system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 320system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction 321system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 322system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction 323system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 324system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 325system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 326system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 327system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 328system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 329system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 330system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 331system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 332system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 333system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 334system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 335system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 336system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 337system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 338system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 339system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 340system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 341system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 342system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 343system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 344system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 345system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction 346system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction 347system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction 348system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 349system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 350system.cpu.op_class::total 5391 # Class of executed instruction 351system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 352system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 353system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 354system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 355system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 356system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 357system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 358system.membus.trans_dist::ReadReq 5597 # Transaction distribution 359system.membus.trans_dist::ReadResp 5608 # Transaction distribution 360system.membus.trans_dist::WriteReq 913 # Transaction distribution 361system.membus.trans_dist::WriteResp 913 # Transaction distribution 362system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 363system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 364system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 365system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 367system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) 368system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 370system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) 371system.membus.snoops 0 # Total snoops (count) 372system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 373system.membus.snoop_fanout::samples 6532 # Request fanout histogram 374system.membus.snoop_fanout::mean 0 # Request fanout histogram 375system.membus.snoop_fanout::stdev 0 # Request fanout histogram 376system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 377system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram 378system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 379system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 380system.membus.snoop_fanout::min_value 0 # Request fanout histogram 381system.membus.snoop_fanout::max_value 0 # Request fanout histogram 382system.membus.snoop_fanout::total 6532 # Request fanout histogram 383 384---------- End Simulation Statistics ----------	162system.cpu.checker.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 163system.cpu.checker.numCycles 0 # number of cpu cycles simulated 164system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 165system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 166system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 167system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 168system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 169system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 170system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 171system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 172system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 173system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 174system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 175system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 176system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 177system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 178system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 179system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 180system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 181system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 182system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 183system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 184system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 185system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 186system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 187system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 188system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 189system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 190system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 191system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 192system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 193system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 194system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 195system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 196system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 197system.cpu.dtb.walker.walks 0 # Table walker walks requested 198system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 199system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 200system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 201system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 202system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 203system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 204system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 205system.cpu.dtb.inst_hits 0 # ITB inst hits 206system.cpu.dtb.inst_misses 0 # ITB inst misses 207system.cpu.dtb.read_hits 0 # DTB read hits 208system.cpu.dtb.read_misses 0 # DTB read misses 209system.cpu.dtb.write_hits 0 # DTB write hits 210system.cpu.dtb.write_misses 0 # DTB write misses 211system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 212system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 213system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 214system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 215system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 216system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 217system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 218system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 219system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 220system.cpu.dtb.read_accesses 0 # DTB read accesses 221system.cpu.dtb.write_accesses 0 # DTB write accesses 222system.cpu.dtb.inst_accesses 0 # ITB inst accesses 223system.cpu.dtb.hits 0 # DTB hits 224system.cpu.dtb.misses 0 # DTB misses 225system.cpu.dtb.accesses 0 # DTB accesses 226system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 227system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 228system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 229system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 230system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 231system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 232system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 233system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 234system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 235system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 236system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 237system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 238system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 239system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 240system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 241system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 242system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 243system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 244system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 245system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 246system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 247system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 248system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 249system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 250system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 251system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 252system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 253system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 254system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 255system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 256system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 257system.cpu.itb.walker.walks 0 # Table walker walks requested 258system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 259system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 260system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 261system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 262system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 263system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 264system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 265system.cpu.itb.inst_hits 0 # ITB inst hits 266system.cpu.itb.inst_misses 0 # ITB inst misses 267system.cpu.itb.read_hits 0 # DTB read hits 268system.cpu.itb.read_misses 0 # DTB read misses 269system.cpu.itb.write_hits 0 # DTB write hits 270system.cpu.itb.write_misses 0 # DTB write misses 271system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 272system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 273system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 274system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 275system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 276system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 277system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 278system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 279system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 280system.cpu.itb.read_accesses 0 # DTB read accesses 281system.cpu.itb.write_accesses 0 # DTB write accesses 282system.cpu.itb.inst_accesses 0 # ITB inst accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses 286system.cpu.pwrStateResidencyTicks::ON 2695000 # Cumulative time (in ticks) in various power states 287system.cpu.numCycles 5391 # number of cpu cycles simulated 288system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 289system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 290system.cpu.committedInsts 4592 # Number of instructions committed 291system.cpu.committedOps 5378 # Number of ops (including micro ops) committed 292system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 293system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 294system.cpu.num_func_calls 203 # number of times a function call or return occured 295system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 296system.cpu.num_int_insts 4624 # number of integer instructions 297system.cpu.num_fp_insts 16 # number of float instructions 298system.cpu.num_int_register_reads 7572 # number of times the integer registers were read 299system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 300system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 301system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 302system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read 303system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 304system.cpu.num_mem_refs 1965 # number of memory refs 305system.cpu.num_load_insts 1027 # Number of load instructions 306system.cpu.num_store_insts 938 # Number of store instructions 307system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 308system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles 309system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 310system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 311system.cpu.Branches 1008 # Number of branches fetched 312system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 313system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction 314system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 315system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 316system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 317system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 318system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 319system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 320system.cpu.op_class::FloatMultAcc 0 0.00% 63.49% # Class of executed instruction 321system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 322system.cpu.op_class::FloatMisc 0 0.00% 63.49% # Class of executed instruction 323system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 324system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 325system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 326system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 327system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 328system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 329system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 330system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 331system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 332system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 333system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 334system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 335system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 336system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 337system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 338system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 339system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 340system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction 341system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction 342system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction 343system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction 344system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 345system.cpu.op_class::MemWrite 922 17.10% 99.70% # Class of executed instruction 346system.cpu.op_class::FloatMemRead 0 0.00% 99.70% # Class of executed instruction 347system.cpu.op_class::FloatMemWrite 16 0.30% 100.00% # Class of executed instruction 348system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 349system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 350system.cpu.op_class::total 5391 # Class of executed instruction 351system.membus.snoop_filter.tot_requests 0 # Total number of requests made to the snoop filter. 352system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 353system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 354system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 355system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 356system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 357system.membus.pwrStateResidencyTicks::UNDEFINED 2695000 # Cumulative time (in ticks) in various power states 358system.membus.trans_dist::ReadReq 5597 # Transaction distribution 359system.membus.trans_dist::ReadResp 5608 # Transaction distribution 360system.membus.trans_dist::WriteReq 913 # Transaction distribution 361system.membus.trans_dist::WriteResp 913 # Transaction distribution 362system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 363system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 364system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 365system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) 366system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 367system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) 368system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) 369system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 370system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) 371system.membus.snoops 0 # Total snoops (count) 372system.membus.snoopTraffic 0 # Total snoop traffic (bytes) 373system.membus.snoop_fanout::samples 6532 # Request fanout histogram 374system.membus.snoop_fanout::mean 0 # Request fanout histogram 375system.membus.snoop_fanout::stdev 0 # Request fanout histogram 376system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 377system.membus.snoop_fanout::0 6532 100.00% 100.00% # Request fanout histogram 378system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 379system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 380system.membus.snoop_fanout::min_value 0 # Request fanout histogram 381system.membus.snoop_fanout::max_value 0 # Request fanout histogram 382system.membus.snoop_fanout::total 6532 # Request fanout histogram 383 384---------- End Simulation Statistics ----------