Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

stats.txt (10628:c9b7e0c69f88)	stats.txt (10726:8a20e2a1562d)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2694500 # Number of ticks simulated 5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 396323 # Simulator instruction rate (inst/s) 8host_op_rate 463654 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 232084410 # Simulator tick rate (ticks/s) 10host_mem_usage 298640 # Number of bytes of host memory used	7host_inst_rate 771856 # Simulator instruction rate (inst/s) 8host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 450886881 # Simulator tick rate (ticks/s) 10host_mem_usage 297796 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) 38system.cpu_clk_domain.clock 500 # Clock period in ticks 39system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 56system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 58system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 59system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 68system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 76system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 77system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 78system.cpu.checker.dtb.read_hits 0 # DTB read hits 79system.cpu.checker.dtb.read_misses 0 # DTB read misses 80system.cpu.checker.dtb.write_hits 0 # DTB write hits 81system.cpu.checker.dtb.write_misses 0 # DTB write misses 82system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 92system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 93system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.checker.dtb.hits 0 # DTB hits 95system.cpu.checker.dtb.misses 0 # DTB misses 96system.cpu.checker.dtb.accesses 0 # DTB accesses 97system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 105system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 126system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 127system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.checker.itb.inst_hits 0 # ITB inst hits 135system.cpu.checker.itb.inst_misses 0 # ITB inst misses 136system.cpu.checker.itb.read_hits 0 # DTB read hits 137system.cpu.checker.itb.read_misses 0 # DTB read misses 138system.cpu.checker.itb.write_hits 0 # DTB write hits 139system.cpu.checker.itb.write_misses 0 # DTB write misses 140system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.checker.itb.read_accesses 0 # DTB read accesses 150system.cpu.checker.itb.write_accesses 0 # DTB write accesses 151system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.checker.itb.hits 0 # DTB hits 153system.cpu.checker.itb.misses 0 # DTB misses 154system.cpu.checker.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 13 # Number of system calls 156system.cpu.checker.numCycles 0 # number of cpu cycles simulated 157system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 159system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 160system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 161system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 162system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 163system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 164system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 165system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 166system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 167system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 168system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 173system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 174system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 175system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 176system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 177system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 178system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 179system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 180system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 181system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 182system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 183system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 184system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 185system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 186system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 187system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 188system.cpu.dtb.walker.walks 0 # Table walker walks requested 189system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 190system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 191system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 192system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 193system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 194system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 195system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 196system.cpu.dtb.inst_hits 0 # ITB inst hits 197system.cpu.dtb.inst_misses 0 # ITB inst misses 198system.cpu.dtb.read_hits 0 # DTB read hits 199system.cpu.dtb.read_misses 0 # DTB read misses 200system.cpu.dtb.write_hits 0 # DTB write hits 201system.cpu.dtb.write_misses 0 # DTB write misses 202system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 203system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 204system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 205system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 206system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 207system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 208system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 209system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 210system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 211system.cpu.dtb.read_accesses 0 # DTB read accesses 212system.cpu.dtb.write_accesses 0 # DTB write accesses 213system.cpu.dtb.inst_accesses 0 # ITB inst accesses 214system.cpu.dtb.hits 0 # DTB hits 215system.cpu.dtb.misses 0 # DTB misses 216system.cpu.dtb.accesses 0 # DTB accesses 217system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 218system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 219system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 220system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 221system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 222system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 223system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 224system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 225system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 226system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 227system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 228system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 229system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 230system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 231system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 232system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 233system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 234system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 235system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 236system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 237system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 238system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 239system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 240system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 241system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 242system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 243system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 244system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 245system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 246system.cpu.itb.walker.walks 0 # Table walker walks requested 247system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 248system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 249system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 250system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 251system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 252system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 253system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 254system.cpu.itb.inst_hits 0 # ITB inst hits 255system.cpu.itb.inst_misses 0 # ITB inst misses 256system.cpu.itb.read_hits 0 # DTB read hits 257system.cpu.itb.read_misses 0 # DTB read misses 258system.cpu.itb.write_hits 0 # DTB write hits 259system.cpu.itb.write_misses 0 # DTB write misses 260system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 262system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 263system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 264system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 265system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 266system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 267system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 268system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 269system.cpu.itb.read_accesses 0 # DTB read accesses 270system.cpu.itb.write_accesses 0 # DTB write accesses 271system.cpu.itb.inst_accesses 0 # ITB inst accesses 272system.cpu.itb.hits 0 # DTB hits 273system.cpu.itb.misses 0 # DTB misses 274system.cpu.itb.accesses 0 # DTB accesses 275system.cpu.numCycles 5390 # number of cpu cycles simulated 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 278system.cpu.committedInsts 4591 # Number of instructions committed 279system.cpu.committedOps 5377 # Number of ops (including micro ops) committed 280system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 281system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 282system.cpu.num_func_calls 203 # number of times a function call or return occured 283system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 284system.cpu.num_int_insts 4624 # number of integer instructions 285system.cpu.num_fp_insts 16 # number of float instructions 286system.cpu.num_int_register_reads 7607 # number of times the integer registers were read 287system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 288system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 289system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 290system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read 291system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 292system.cpu.num_mem_refs 1965 # number of memory refs 293system.cpu.num_load_insts 1027 # Number of load instructions 294system.cpu.num_store_insts 938 # Number of store instructions 295system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 296system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles 297system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 298system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 299system.cpu.Branches 1007 # Number of branches fetched 300system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 301system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction 302system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 303system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 304system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 305system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 306system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 307system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 308system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 309system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 310system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 311system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 312system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 313system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 314system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 315system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 316system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 317system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 318system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 319system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 320system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 321system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 322system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 323system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 324system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 325system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 326system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction 327system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 328system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 329system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 330system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 331system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 332system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 333system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 334system.cpu.op_class::total 5390 # Class of executed instruction 335system.membus.trans_dist::ReadReq 5596 # Transaction distribution 336system.membus.trans_dist::ReadResp 5607 # Transaction distribution 337system.membus.trans_dist::WriteReq 913 # Transaction distribution 338system.membus.trans_dist::WriteResp 913 # Transaction distribution 339system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 340system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 341system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 342system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 345system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 348system.membus.snoops 0 # Total snoops (count) 349system.membus.snoop_fanout::samples 6531 # Request fanout histogram	11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) 38system.cpu_clk_domain.clock 500 # Clock period in ticks 39system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 40system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 47system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 48system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 49system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 50system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 51system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 52system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 53system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 54system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 55system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 56system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 57system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 58system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 59system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 60system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 61system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 62system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 63system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 64system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 65system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 66system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 67system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 68system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested 69system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 70system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 71system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 72system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 73system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 74system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 75system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 76system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 77system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 78system.cpu.checker.dtb.read_hits 0 # DTB read hits 79system.cpu.checker.dtb.read_misses 0 # DTB read misses 80system.cpu.checker.dtb.write_hits 0 # DTB write hits 81system.cpu.checker.dtb.write_misses 0 # DTB write misses 82system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 83system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 84system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 85system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 86system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 87system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 88system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 89system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 90system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 91system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 92system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 93system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 94system.cpu.checker.dtb.hits 0 # DTB hits 95system.cpu.checker.dtb.misses 0 # DTB misses 96system.cpu.checker.dtb.accesses 0 # DTB accesses 97system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 98system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 99system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 100system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 101system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 105system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 106system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 107system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 108system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 109system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 110system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 111system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 121system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 122system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 123system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 124system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 125system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 126system.cpu.checker.itb.walker.walks 0 # Table walker walks requested 127system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 128system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 129system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 130system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 131system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 132system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 133system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 134system.cpu.checker.itb.inst_hits 0 # ITB inst hits 135system.cpu.checker.itb.inst_misses 0 # ITB inst misses 136system.cpu.checker.itb.read_hits 0 # DTB read hits 137system.cpu.checker.itb.read_misses 0 # DTB read misses 138system.cpu.checker.itb.write_hits 0 # DTB write hits 139system.cpu.checker.itb.write_misses 0 # DTB write misses 140system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 141system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 142system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 143system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 144system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 145system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 146system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 147system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 148system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 149system.cpu.checker.itb.read_accesses 0 # DTB read accesses 150system.cpu.checker.itb.write_accesses 0 # DTB write accesses 151system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 152system.cpu.checker.itb.hits 0 # DTB hits 153system.cpu.checker.itb.misses 0 # DTB misses 154system.cpu.checker.itb.accesses 0 # DTB accesses 155system.cpu.workload.num_syscalls 13 # Number of system calls 156system.cpu.checker.numCycles 0 # number of cpu cycles simulated 157system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 158system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 159system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 160system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 161system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 162system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 163system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 164system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 165system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 166system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 167system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 168system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 173system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 174system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 175system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 176system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 177system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 178system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 179system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 180system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 181system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 182system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 183system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 184system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 185system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 186system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 187system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 188system.cpu.dtb.walker.walks 0 # Table walker walks requested 189system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 190system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 191system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 192system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 193system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 194system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 195system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 196system.cpu.dtb.inst_hits 0 # ITB inst hits 197system.cpu.dtb.inst_misses 0 # ITB inst misses 198system.cpu.dtb.read_hits 0 # DTB read hits 199system.cpu.dtb.read_misses 0 # DTB read misses 200system.cpu.dtb.write_hits 0 # DTB write hits 201system.cpu.dtb.write_misses 0 # DTB write misses 202system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 203system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 204system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 205system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 206system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 207system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 208system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 209system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 210system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 211system.cpu.dtb.read_accesses 0 # DTB read accesses 212system.cpu.dtb.write_accesses 0 # DTB write accesses 213system.cpu.dtb.inst_accesses 0 # ITB inst accesses 214system.cpu.dtb.hits 0 # DTB hits 215system.cpu.dtb.misses 0 # DTB misses 216system.cpu.dtb.accesses 0 # DTB accesses 217system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 218system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 219system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 220system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 221system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 222system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 223system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 224system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 225system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 226system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 227system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 228system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 229system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 230system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 231system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 232system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 233system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 234system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 235system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 236system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 237system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 238system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 239system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 240system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 241system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 242system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 243system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 244system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 245system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 246system.cpu.itb.walker.walks 0 # Table walker walks requested 247system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 248system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 249system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 250system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 251system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 252system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 253system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst 254system.cpu.itb.inst_hits 0 # ITB inst hits 255system.cpu.itb.inst_misses 0 # ITB inst misses 256system.cpu.itb.read_hits 0 # DTB read hits 257system.cpu.itb.read_misses 0 # DTB read misses 258system.cpu.itb.write_hits 0 # DTB write hits 259system.cpu.itb.write_misses 0 # DTB write misses 260system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 262system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 263system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 264system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 265system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 266system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 267system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 268system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 269system.cpu.itb.read_accesses 0 # DTB read accesses 270system.cpu.itb.write_accesses 0 # DTB write accesses 271system.cpu.itb.inst_accesses 0 # ITB inst accesses 272system.cpu.itb.hits 0 # DTB hits 273system.cpu.itb.misses 0 # DTB misses 274system.cpu.itb.accesses 0 # DTB accesses 275system.cpu.numCycles 5390 # number of cpu cycles simulated 276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 278system.cpu.committedInsts 4591 # Number of instructions committed 279system.cpu.committedOps 5377 # Number of ops (including micro ops) committed 280system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses 281system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 282system.cpu.num_func_calls 203 # number of times a function call or return occured 283system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls 284system.cpu.num_int_insts 4624 # number of integer instructions 285system.cpu.num_fp_insts 16 # number of float instructions 286system.cpu.num_int_register_reads 7607 # number of times the integer registers were read 287system.cpu.num_int_register_writes 2728 # number of times the integer registers were written 288system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 289system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 290system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read 291system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written 292system.cpu.num_mem_refs 1965 # number of memory refs 293system.cpu.num_load_insts 1027 # Number of load instructions 294system.cpu.num_store_insts 938 # Number of store instructions 295system.cpu.num_idle_cycles 0.002000 # Number of idle cycles 296system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles 297system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles 298system.cpu.idle_fraction 0.000000 # Percentage of idle cycles 299system.cpu.Branches 1007 # Number of branches fetched 300system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 301system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction 302system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction 303system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction 304system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction 305system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction 306system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction 307system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction 308system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction 309system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction 310system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction 311system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction 312system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction 313system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction 314system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction 315system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction 316system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction 317system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction 318system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction 319system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction 320system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction 321system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction 322system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction 323system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction 324system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction 325system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction 326system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction 327system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction 328system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction 329system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction 330system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction 331system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction 332system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 333system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 334system.cpu.op_class::total 5390 # Class of executed instruction 335system.membus.trans_dist::ReadReq 5596 # Transaction distribution 336system.membus.trans_dist::ReadResp 5607 # Transaction distribution 337system.membus.trans_dist::WriteReq 913 # Transaction distribution 338system.membus.trans_dist::WriteResp 913 # Transaction distribution 339system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution 340system.membus.trans_dist::StoreCondReq 11 # Transaction distribution 341system.membus.trans_dist::StoreCondResp 11 # Transaction distribution 342system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) 343system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) 344system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) 345system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) 346system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) 347system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) 348system.membus.snoops 0 # Total snoops (count) 349system.membus.snoop_fanout::samples 6531 # Request fanout histogram
350system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram	350system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram
351system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 354system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram	351system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram 352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 354system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
355system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 356system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 357system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram 358system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram	355system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram 356system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram
359system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram	357system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
360system.membus.snoop_fanout::min_value 4 # Request fanout histogram 361system.membus.snoop_fanout::max_value 5 # Request fanout histogram	358system.membus.snoop_fanout::min_value 2 # Request fanout histogram 359system.membus.snoop_fanout::max_value 3 # Request fanout histogram
362system.membus.snoop_fanout::total 6531 # Request fanout histogram 363 364---------- End Simulation Statistics ----------	360system.membus.snoop_fanout::total 6531 # Request fanout histogram 361 362---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2694500 # Number of ticks simulated
5final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 396323 # Simulator instruction rate (inst/s)
8host_op_rate 463654 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 232084410 # Simulator tick rate (ticks/s)
10host_mem_usage 298640 # Number of bytes of host memory used

7host_inst_rate 771856 # Simulator instruction rate (inst/s)
8host_op_rate 901727 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 450886881 # Simulator tick rate (ticks/s)
10host_mem_usage 297796 # Number of bytes of host memory used

11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated
13sim_ops 5377 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory
26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s)
38system.cpu_clk_domain.clock 500 # Clock period in ticks
39system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
40system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
41system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
42system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
43system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
44system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
45system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
46system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
47system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
48system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
49system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
50system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
51system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
52system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
53system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
54system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
55system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
56system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
57system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
58system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
59system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
60system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
61system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
62system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
63system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
64system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
65system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
66system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
67system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
68system.cpu.checker.dtb.walker.walks 0 # Table walker walks requested
69system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
70system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
71system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
72system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
73system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
74system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
75system.cpu.checker.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
76system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
77system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
78system.cpu.checker.dtb.read_hits 0 # DTB read hits
79system.cpu.checker.dtb.read_misses 0 # DTB read misses
80system.cpu.checker.dtb.write_hits 0 # DTB write hits
81system.cpu.checker.dtb.write_misses 0 # DTB write misses
82system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
83system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
84system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
85system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
86system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
87system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
88system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
89system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
90system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
91system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
92system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
93system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
94system.cpu.checker.dtb.hits 0 # DTB hits
95system.cpu.checker.dtb.misses 0 # DTB misses
96system.cpu.checker.dtb.accesses 0 # DTB accesses
97system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
98system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
99system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
100system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
101system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
102system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
103system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
104system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
105system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
106system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
107system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
108system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
109system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
110system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
111system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
112system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
116system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
117system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
118system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
119system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
121system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
122system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
123system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
124system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
125system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
126system.cpu.checker.itb.walker.walks 0 # Table walker walks requested
127system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
128system.cpu.checker.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
129system.cpu.checker.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
130system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
131system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
132system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
133system.cpu.checker.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
134system.cpu.checker.itb.inst_hits 0 # ITB inst hits
135system.cpu.checker.itb.inst_misses 0 # ITB inst misses
136system.cpu.checker.itb.read_hits 0 # DTB read hits
137system.cpu.checker.itb.read_misses 0 # DTB read misses
138system.cpu.checker.itb.write_hits 0 # DTB write hits
139system.cpu.checker.itb.write_misses 0 # DTB write misses
140system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
141system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
142system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
143system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
144system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
145system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
146system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
147system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
148system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
149system.cpu.checker.itb.read_accesses 0 # DTB read accesses
150system.cpu.checker.itb.write_accesses 0 # DTB write accesses
151system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
152system.cpu.checker.itb.hits 0 # DTB hits
153system.cpu.checker.itb.misses 0 # DTB misses
154system.cpu.checker.itb.accesses 0 # DTB accesses
155system.cpu.workload.num_syscalls 13 # Number of system calls
156system.cpu.checker.numCycles 0 # number of cpu cycles simulated
157system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
158system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
159system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
160system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
161system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
162system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
163system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
164system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
165system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
166system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
167system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
168system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
169system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
170system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
171system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
172system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
173system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
174system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
175system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
176system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
177system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
178system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
179system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
180system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
181system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
182system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
183system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
184system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
185system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
186system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
187system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
188system.cpu.dtb.walker.walks 0 # Table walker walks requested
189system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
190system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
191system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
192system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
193system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
194system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
195system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
196system.cpu.dtb.inst_hits 0 # ITB inst hits
197system.cpu.dtb.inst_misses 0 # ITB inst misses
198system.cpu.dtb.read_hits 0 # DTB read hits
199system.cpu.dtb.read_misses 0 # DTB read misses
200system.cpu.dtb.write_hits 0 # DTB write hits
201system.cpu.dtb.write_misses 0 # DTB write misses
202system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
203system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
204system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
205system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
206system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
207system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
208system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
209system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
210system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
211system.cpu.dtb.read_accesses 0 # DTB read accesses
212system.cpu.dtb.write_accesses 0 # DTB write accesses
213system.cpu.dtb.inst_accesses 0 # ITB inst accesses
214system.cpu.dtb.hits 0 # DTB hits
215system.cpu.dtb.misses 0 # DTB misses
216system.cpu.dtb.accesses 0 # DTB accesses
217system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
218system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
219system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
220system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
221system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
222system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
223system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
224system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
225system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
226system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
227system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
228system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
229system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
230system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
231system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
232system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
233system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
234system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
235system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
236system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
237system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
238system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
239system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
240system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
241system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
242system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
243system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
244system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
245system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
246system.cpu.itb.walker.walks 0 # Table walker walks requested
247system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
248system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
249system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
250system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
251system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
252system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
253system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
254system.cpu.itb.inst_hits 0 # ITB inst hits
255system.cpu.itb.inst_misses 0 # ITB inst misses
256system.cpu.itb.read_hits 0 # DTB read hits
257system.cpu.itb.read_misses 0 # DTB read misses
258system.cpu.itb.write_hits 0 # DTB write hits
259system.cpu.itb.write_misses 0 # DTB write misses
260system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
261system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
262system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
263system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
264system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
265system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
266system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
267system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
268system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
269system.cpu.itb.read_accesses 0 # DTB read accesses
270system.cpu.itb.write_accesses 0 # DTB write accesses
271system.cpu.itb.inst_accesses 0 # ITB inst accesses
272system.cpu.itb.hits 0 # DTB hits
273system.cpu.itb.misses 0 # DTB misses
274system.cpu.itb.accesses 0 # DTB accesses
275system.cpu.numCycles 5390 # number of cpu cycles simulated
276system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
277system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
278system.cpu.committedInsts 4591 # Number of instructions committed
279system.cpu.committedOps 5377 # Number of ops (including micro ops) committed
280system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses
281system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
282system.cpu.num_func_calls 203 # number of times a function call or return occured
283system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls
284system.cpu.num_int_insts 4624 # number of integer instructions
285system.cpu.num_fp_insts 16 # number of float instructions
286system.cpu.num_int_register_reads 7607 # number of times the integer registers were read
287system.cpu.num_int_register_writes 2728 # number of times the integer registers were written
288system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
289system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
290system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read
291system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written
292system.cpu.num_mem_refs 1965 # number of memory refs
293system.cpu.num_load_insts 1027 # Number of load instructions
294system.cpu.num_store_insts 938 # Number of store instructions
295system.cpu.num_idle_cycles 0.002000 # Number of idle cycles
296system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles
297system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles
298system.cpu.idle_fraction 0.000000 # Percentage of idle cycles
299system.cpu.Branches 1007 # Number of branches fetched
300system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
301system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction
302system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction
303system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction
304system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction
305system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction
306system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction
307system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction
308system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction
309system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction
310system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction
311system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction
312system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction
313system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction
314system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction
315system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction
316system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction
317system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction
318system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction
319system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction
320system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction
321system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction
322system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction
323system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction
324system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction
325system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction
326system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction
327system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction
328system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction
329system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction
330system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction
331system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction
332system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
333system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
334system.cpu.op_class::total 5390 # Class of executed instruction
335system.membus.trans_dist::ReadReq 5596 # Transaction distribution
336system.membus.trans_dist::ReadResp 5607 # Transaction distribution
337system.membus.trans_dist::WriteReq 913 # Transaction distribution
338system.membus.trans_dist::WriteResp 913 # Transaction distribution
339system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution
340system.membus.trans_dist::StoreCondReq 11 # Transaction distribution
341system.membus.trans_dist::StoreCondResp 11 # Transaction distribution
342system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes)
343system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes)
344system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes)
345system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes)
346system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes)
347system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes)
348system.membus.snoops 0 # Total snoops (count)
349system.membus.snoop_fanout::samples 6531 # Request fanout histogram

350system.membus.snoop_fanout::mean 4.704946 # Request fanout histogram

350system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram

351system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram
352system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
353system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
354system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram

355system.membus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
356system.membus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
357system.membus.snoop_fanout::4 1927 29.51% 29.51% # Request fanout histogram
358system.membus.snoop_fanout::5 4604 70.49% 100.00% # Request fanout histogram

355system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram
356system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram

359system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

357system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram

360system.membus.snoop_fanout::min_value 4 # Request fanout histogram
361system.membus.snoop_fanout::max_value 5 # Request fanout histogram

358system.membus.snoop_fanout::min_value 2 # Request fanout histogram
359system.membus.snoop_fanout::max_value 3 # Request fanout histogram