Cross Reference: /gem5/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt

stats.txt (10063:9595c7a1d837)	stats.txt (10220:9eab5efc02e8)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2870500 # Number of ticks simulated 5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000003 # Number of seconds simulated 4sim_ticks 2870500 # Number of ticks simulated 5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 97101 # Simulator instruction rate (inst/s) 8host_op_rate 121123 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60664840 # Simulator tick rate (ticks/s) 10host_mem_usage 311632 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host	7host_inst_rate 790734 # Simulator instruction rate (inst/s) 8host_op_rate 984195 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 492029482 # Simulator tick rate (ticks/s) 10host_mem_usage 297624 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9251001568 # Throughput (bytes/s) 39system.membus.data_through_bus 26555 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 64system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 65system.cpu.checker.dtb.read_hits 0 # DTB read hits 66system.cpu.checker.dtb.read_misses 0 # DTB read misses 67system.cpu.checker.dtb.write_hits 0 # DTB write hits 68system.cpu.checker.dtb.write_misses 0 # DTB write misses 69system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 73system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 74system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 75system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 76system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 79system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 80system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 81system.cpu.checker.dtb.hits 0 # DTB hits 82system.cpu.checker.dtb.misses 0 # DTB misses 83system.cpu.checker.dtb.accesses 0 # DTB accesses 84system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 85system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 86system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 87system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 88system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 90system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 91system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 92system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 93system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 95system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 96system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 97system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 98system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 99system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 100system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 101system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 102system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 103system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 104system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 105system.cpu.checker.itb.inst_hits 0 # ITB inst hits 106system.cpu.checker.itb.inst_misses 0 # ITB inst misses 107system.cpu.checker.itb.read_hits 0 # DTB read hits 108system.cpu.checker.itb.read_misses 0 # DTB read misses 109system.cpu.checker.itb.write_hits 0 # DTB write hits 110system.cpu.checker.itb.write_misses 0 # DTB write misses 111system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.checker.itb.read_accesses 0 # DTB read accesses 121system.cpu.checker.itb.write_accesses 0 # DTB write accesses 122system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 123system.cpu.checker.itb.hits 0 # DTB hits 124system.cpu.checker.itb.misses 0 # DTB misses 125system.cpu.checker.itb.accesses 0 # DTB accesses 126system.cpu.workload.num_syscalls 13 # Number of system calls 127system.cpu.checker.numCycles 0 # number of cpu cycles simulated 128system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 129system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 130system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 131system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 132system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 133system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 134system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 135system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 136system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 137system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 139system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 140system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 141system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 142system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 143system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 144system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 148system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 149system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 150system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 151system.cpu.dtb.inst_hits 0 # ITB inst hits 152system.cpu.dtb.inst_misses 0 # ITB inst misses 153system.cpu.dtb.read_hits 0 # DTB read hits 154system.cpu.dtb.read_misses 0 # DTB read misses 155system.cpu.dtb.write_hits 0 # DTB write hits 156system.cpu.dtb.write_misses 0 # DTB write misses 157system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 158system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 160system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 161system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 162system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 163system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 164system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 165system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 166system.cpu.dtb.read_accesses 0 # DTB read accesses 167system.cpu.dtb.write_accesses 0 # DTB write accesses 168system.cpu.dtb.inst_accesses 0 # ITB inst accesses 169system.cpu.dtb.hits 0 # DTB hits 170system.cpu.dtb.misses 0 # DTB misses 171system.cpu.dtb.accesses 0 # DTB accesses 172system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 173system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 174system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 175system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 176system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 177system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 178system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 179system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 181system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 182system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 183system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 184system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 185system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 186system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 187system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 188system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 189system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 190system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 191system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 192system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 193system.cpu.itb.inst_hits 0 # ITB inst hits 194system.cpu.itb.inst_misses 0 # ITB inst misses 195system.cpu.itb.read_hits 0 # DTB read hits 196system.cpu.itb.read_misses 0 # DTB read misses 197system.cpu.itb.write_hits 0 # DTB write hits 198system.cpu.itb.write_misses 0 # DTB write misses 199system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 200system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 201system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 202system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 203system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 204system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 205system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 206system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 207system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 208system.cpu.itb.read_accesses 0 # DTB read accesses 209system.cpu.itb.write_accesses 0 # DTB write accesses 210system.cpu.itb.inst_accesses 0 # ITB inst accesses 211system.cpu.itb.hits 0 # DTB hits 212system.cpu.itb.misses 0 # DTB misses 213system.cpu.itb.accesses 0 # DTB accesses 214system.cpu.numCycles 5742 # number of cpu cycles simulated 215system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 217system.cpu.committedInsts 4591 # Number of instructions committed 218system.cpu.committedOps 5729 # Number of ops (including micro ops) committed 219system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 220system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 221system.cpu.num_func_calls 203 # number of times a function call or return occured 222system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 223system.cpu.num_int_insts 4976 # number of integer instructions 224system.cpu.num_fp_insts 16 # number of float instructions 225system.cpu.num_int_register_reads 25360 # number of times the integer registers were read 226system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 227system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 228system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 229system.cpu.num_mem_refs 2138 # number of memory refs 230system.cpu.num_load_insts 1200 # Number of load instructions 231system.cpu.num_store_insts 938 # Number of store instructions 232system.cpu.num_idle_cycles 0 # Number of idle cycles 233system.cpu.num_busy_cycles 5742 # Number of busy cycles 234system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 235system.cpu.idle_fraction 0 # Percentage of idle cycles 236system.cpu.Branches 1007 # Number of branches fetched	12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory 18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory 21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory 22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory 23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory 26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory 27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory 28system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s) 34system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s) 35system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s) 38system.membus.throughput 9251001568 # Throughput (bytes/s) 39system.membus.data_through_bus 26555 # Total data (bytes) 40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 41system.cpu_clk_domain.clock 500 # Clock period in ticks 42system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 43system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 44system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 45system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 46system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 47system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 48system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 49system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 50system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 51system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 52system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 53system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 54system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 55system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 56system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 57system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 58system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 59system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 60system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 61system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 62system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 63system.cpu.checker.dtb.inst_hits 0 # ITB inst hits 64system.cpu.checker.dtb.inst_misses 0 # ITB inst misses 65system.cpu.checker.dtb.read_hits 0 # DTB read hits 66system.cpu.checker.dtb.read_misses 0 # DTB read misses 67system.cpu.checker.dtb.write_hits 0 # DTB write hits 68system.cpu.checker.dtb.write_misses 0 # DTB write misses 69system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed 70system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 71system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 72system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 73system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 74system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 75system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 76system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 77system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 78system.cpu.checker.dtb.read_accesses 0 # DTB read accesses 79system.cpu.checker.dtb.write_accesses 0 # DTB write accesses 80system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses 81system.cpu.checker.dtb.hits 0 # DTB hits 82system.cpu.checker.dtb.misses 0 # DTB misses 83system.cpu.checker.dtb.accesses 0 # DTB accesses 84system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 85system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 86system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 87system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 88system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 89system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 90system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 91system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 92system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 93system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 94system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 95system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 96system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 97system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 98system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 99system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 100system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 101system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 102system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits 103system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses 104system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 105system.cpu.checker.itb.inst_hits 0 # ITB inst hits 106system.cpu.checker.itb.inst_misses 0 # ITB inst misses 107system.cpu.checker.itb.read_hits 0 # DTB read hits 108system.cpu.checker.itb.read_misses 0 # DTB read misses 109system.cpu.checker.itb.write_hits 0 # DTB write hits 110system.cpu.checker.itb.write_misses 0 # DTB write misses 111system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed 112system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 113system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 114system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 115system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB 116system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 117system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 118system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 119system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 120system.cpu.checker.itb.read_accesses 0 # DTB read accesses 121system.cpu.checker.itb.write_accesses 0 # DTB write accesses 122system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses 123system.cpu.checker.itb.hits 0 # DTB hits 124system.cpu.checker.itb.misses 0 # DTB misses 125system.cpu.checker.itb.accesses 0 # DTB accesses 126system.cpu.workload.num_syscalls 13 # Number of system calls 127system.cpu.checker.numCycles 0 # number of cpu cycles simulated 128system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started 129system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed 130system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 131system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 132system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 133system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 134system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 135system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 136system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 137system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 138system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 139system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 140system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 141system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 142system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 143system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 144system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 145system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 146system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 147system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 148system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 149system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 150system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses 151system.cpu.dtb.inst_hits 0 # ITB inst hits 152system.cpu.dtb.inst_misses 0 # ITB inst misses 153system.cpu.dtb.read_hits 0 # DTB read hits 154system.cpu.dtb.read_misses 0 # DTB read misses 155system.cpu.dtb.write_hits 0 # DTB write hits 156system.cpu.dtb.write_misses 0 # DTB write misses 157system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 158system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 159system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 160system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 161system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB 162system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions 163system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch 164system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 165system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 166system.cpu.dtb.read_accesses 0 # DTB read accesses 167system.cpu.dtb.write_accesses 0 # DTB write accesses 168system.cpu.dtb.inst_accesses 0 # ITB inst accesses 169system.cpu.dtb.hits 0 # DTB hits 170system.cpu.dtb.misses 0 # DTB misses 171system.cpu.dtb.accesses 0 # DTB accesses 172system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 173system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 174system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 175system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 176system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 177system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 178system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 179system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 180system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 181system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 182system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 183system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 184system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 185system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 186system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 187system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 188system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 189system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 190system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 191system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 192system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses 193system.cpu.itb.inst_hits 0 # ITB inst hits 194system.cpu.itb.inst_misses 0 # ITB inst misses 195system.cpu.itb.read_hits 0 # DTB read hits 196system.cpu.itb.read_misses 0 # DTB read misses 197system.cpu.itb.write_hits 0 # DTB write hits 198system.cpu.itb.write_misses 0 # DTB write misses 199system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 200system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 201system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 202system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 203system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB 204system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions 205system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch 206system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 207system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 208system.cpu.itb.read_accesses 0 # DTB read accesses 209system.cpu.itb.write_accesses 0 # DTB write accesses 210system.cpu.itb.inst_accesses 0 # ITB inst accesses 211system.cpu.itb.hits 0 # DTB hits 212system.cpu.itb.misses 0 # DTB misses 213system.cpu.itb.accesses 0 # DTB accesses 214system.cpu.numCycles 5742 # number of cpu cycles simulated 215system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 217system.cpu.committedInsts 4591 # Number of instructions committed 218system.cpu.committedOps 5729 # Number of ops (including micro ops) committed 219system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses 220system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses 221system.cpu.num_func_calls 203 # number of times a function call or return occured 222system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls 223system.cpu.num_int_insts 4976 # number of integer instructions 224system.cpu.num_fp_insts 16 # number of float instructions 225system.cpu.num_int_register_reads 25360 # number of times the integer registers were read 226system.cpu.num_int_register_writes 5334 # number of times the integer registers were written 227system.cpu.num_fp_register_reads 16 # number of times the floating registers were read 228system.cpu.num_fp_register_writes 0 # number of times the floating registers were written 229system.cpu.num_mem_refs 2138 # number of memory refs 230system.cpu.num_load_insts 1200 # Number of load instructions 231system.cpu.num_store_insts 938 # Number of store instructions 232system.cpu.num_idle_cycles 0 # Number of idle cycles 233system.cpu.num_busy_cycles 5742 # Number of busy cycles 234system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 235system.cpu.idle_fraction 0 # Percentage of idle cycles 236system.cpu.Branches 1007 # Number of branches fetched
	237system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction 238system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction 239system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction 240system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction 241system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction 242system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction 243system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction 244system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction 245system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction 246system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction 247system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction 248system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction 249system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction 250system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction 251system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction 252system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction 253system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction 254system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction 255system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction 256system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction 257system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction 258system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction 259system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction 260system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction 261system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction 262system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction 263system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction 264system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction 265system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction 266system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction 267system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction 268system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction 269system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 270system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 271system.cpu.op_class::total 5742 # Class of executed instruction
237 238---------- End Simulation Statistics ----------	272 273---------- End Simulation Statistics ----------

1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2870500 # Number of ticks simulated
5final_tick 2870500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 97101 # Simulator instruction rate (inst/s)
8host_op_rate 121123 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 60664840 # Simulator tick rate (ticks/s)
10host_mem_usage 311632 # Number of bytes of host memory used
11host_seconds 0.05 # Real time elapsed on the host

7host_inst_rate 790734 # Simulator instruction rate (inst/s)
8host_op_rate 984195 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 492029482 # Simulator tick rate (ticks/s)
10host_mem_usage 297624 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host

12sim_insts 4591 # Number of instructions simulated
13sim_ops 5729 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory
18system.physmem.bytes_read::total 22907 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory
21system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory
22system.physmem.bytes_written::total 3648 # Number of bytes written to this memory
23system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory
24system.physmem.num_reads::cpu.data 1157 # Number of read requests responded to by this memory
25system.physmem.num_reads::total 5761 # Number of read requests responded to by this memory
26system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory
27system.physmem.num_writes::total 924 # Number of write requests responded to by this memory
28system.physmem.bw_read::cpu.inst 6415607037 # Total read bandwidth from this memory (bytes/s)
29system.physmem.bw_read::cpu.data 1564535795 # Total read bandwidth from this memory (bytes/s)
30system.physmem.bw_read::total 7980142832 # Total read bandwidth from this memory (bytes/s)
31system.physmem.bw_inst_read::cpu.inst 6415607037 # Instruction read bandwidth from this memory (bytes/s)
32system.physmem.bw_inst_read::total 6415607037 # Instruction read bandwidth from this memory (bytes/s)
33system.physmem.bw_write::cpu.data 1270858735 # Write bandwidth from this memory (bytes/s)
34system.physmem.bw_write::total 1270858735 # Write bandwidth from this memory (bytes/s)
35system.physmem.bw_total::cpu.inst 6415607037 # Total bandwidth to/from this memory (bytes/s)
36system.physmem.bw_total::cpu.data 2835394531 # Total bandwidth to/from this memory (bytes/s)
37system.physmem.bw_total::total 9251001568 # Total bandwidth to/from this memory (bytes/s)
38system.membus.throughput 9251001568 # Throughput (bytes/s)
39system.membus.data_through_bus 26555 # Total data (bytes)
40system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
41system.cpu_clk_domain.clock 500 # Clock period in ticks
42system.cpu.checker.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
43system.cpu.checker.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
44system.cpu.checker.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
45system.cpu.checker.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
46system.cpu.checker.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
47system.cpu.checker.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
48system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
49system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
50system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
51system.cpu.checker.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
52system.cpu.checker.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
53system.cpu.checker.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
54system.cpu.checker.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
55system.cpu.checker.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
56system.cpu.checker.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
57system.cpu.checker.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
58system.cpu.checker.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
59system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
60system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
61system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
62system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
63system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
64system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
65system.cpu.checker.dtb.read_hits 0 # DTB read hits
66system.cpu.checker.dtb.read_misses 0 # DTB read misses
67system.cpu.checker.dtb.write_hits 0 # DTB write hits
68system.cpu.checker.dtb.write_misses 0 # DTB write misses
69system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
70system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
71system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
72system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
73system.cpu.checker.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
74system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
75system.cpu.checker.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
76system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
77system.cpu.checker.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
78system.cpu.checker.dtb.read_accesses 0 # DTB read accesses
79system.cpu.checker.dtb.write_accesses 0 # DTB write accesses
80system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses
81system.cpu.checker.dtb.hits 0 # DTB hits
82system.cpu.checker.dtb.misses 0 # DTB misses
83system.cpu.checker.dtb.accesses 0 # DTB accesses
84system.cpu.checker.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
85system.cpu.checker.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
86system.cpu.checker.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
87system.cpu.checker.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
88system.cpu.checker.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
89system.cpu.checker.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
90system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
91system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
92system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
93system.cpu.checker.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
94system.cpu.checker.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
95system.cpu.checker.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
96system.cpu.checker.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
97system.cpu.checker.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
98system.cpu.checker.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
99system.cpu.checker.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
100system.cpu.checker.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
101system.cpu.checker.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
102system.cpu.checker.istage2_mmu.stage2_tlb.hits 0 # DTB hits
103system.cpu.checker.istage2_mmu.stage2_tlb.misses 0 # DTB misses
104system.cpu.checker.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
105system.cpu.checker.itb.inst_hits 0 # ITB inst hits
106system.cpu.checker.itb.inst_misses 0 # ITB inst misses
107system.cpu.checker.itb.read_hits 0 # DTB read hits
108system.cpu.checker.itb.read_misses 0 # DTB read misses
109system.cpu.checker.itb.write_hits 0 # DTB write hits
110system.cpu.checker.itb.write_misses 0 # DTB write misses
111system.cpu.checker.itb.flush_tlb 0 # Number of times complete TLB was flushed
112system.cpu.checker.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
113system.cpu.checker.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
114system.cpu.checker.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
115system.cpu.checker.itb.flush_entries 0 # Number of entries that have been flushed from TLB
116system.cpu.checker.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
117system.cpu.checker.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
118system.cpu.checker.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
119system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
120system.cpu.checker.itb.read_accesses 0 # DTB read accesses
121system.cpu.checker.itb.write_accesses 0 # DTB write accesses
122system.cpu.checker.itb.inst_accesses 0 # ITB inst accesses
123system.cpu.checker.itb.hits 0 # DTB hits
124system.cpu.checker.itb.misses 0 # DTB misses
125system.cpu.checker.itb.accesses 0 # DTB accesses
126system.cpu.workload.num_syscalls 13 # Number of system calls
127system.cpu.checker.numCycles 0 # number of cpu cycles simulated
128system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started
129system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed
130system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
131system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
132system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
133system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
134system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
135system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
136system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
137system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
138system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
139system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
140system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
141system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
142system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
143system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
144system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
145system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
146system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
147system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
148system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
149system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
150system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
151system.cpu.dtb.inst_hits 0 # ITB inst hits
152system.cpu.dtb.inst_misses 0 # ITB inst misses
153system.cpu.dtb.read_hits 0 # DTB read hits
154system.cpu.dtb.read_misses 0 # DTB read misses
155system.cpu.dtb.write_hits 0 # DTB write hits
156system.cpu.dtb.write_misses 0 # DTB write misses
157system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
158system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
159system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
160system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
161system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
162system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
163system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
164system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
165system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
166system.cpu.dtb.read_accesses 0 # DTB read accesses
167system.cpu.dtb.write_accesses 0 # DTB write accesses
168system.cpu.dtb.inst_accesses 0 # ITB inst accesses
169system.cpu.dtb.hits 0 # DTB hits
170system.cpu.dtb.misses 0 # DTB misses
171system.cpu.dtb.accesses 0 # DTB accesses
172system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
173system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
174system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
175system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
176system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
177system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
178system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
179system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
180system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
181system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
182system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
183system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
184system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
185system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
186system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
187system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
188system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
189system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
190system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
191system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
192system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
193system.cpu.itb.inst_hits 0 # ITB inst hits
194system.cpu.itb.inst_misses 0 # ITB inst misses
195system.cpu.itb.read_hits 0 # DTB read hits
196system.cpu.itb.read_misses 0 # DTB read misses
197system.cpu.itb.write_hits 0 # DTB write hits
198system.cpu.itb.write_misses 0 # DTB write misses
199system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
200system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
201system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
202system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
203system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
204system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
205system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
206system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
207system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
208system.cpu.itb.read_accesses 0 # DTB read accesses
209system.cpu.itb.write_accesses 0 # DTB write accesses
210system.cpu.itb.inst_accesses 0 # ITB inst accesses
211system.cpu.itb.hits 0 # DTB hits
212system.cpu.itb.misses 0 # DTB misses
213system.cpu.itb.accesses 0 # DTB accesses
214system.cpu.numCycles 5742 # number of cpu cycles simulated
215system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
216system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
217system.cpu.committedInsts 4591 # Number of instructions committed
218system.cpu.committedOps 5729 # Number of ops (including micro ops) committed
219system.cpu.num_int_alu_accesses 4976 # Number of integer alu accesses
220system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
221system.cpu.num_func_calls 203 # number of times a function call or return occured
222system.cpu.num_conditional_control_insts 792 # number of instructions that are conditional controls
223system.cpu.num_int_insts 4976 # number of integer instructions
224system.cpu.num_fp_insts 16 # number of float instructions
225system.cpu.num_int_register_reads 25360 # number of times the integer registers were read
226system.cpu.num_int_register_writes 5334 # number of times the integer registers were written
227system.cpu.num_fp_register_reads 16 # number of times the floating registers were read
228system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
229system.cpu.num_mem_refs 2138 # number of memory refs
230system.cpu.num_load_insts 1200 # Number of load instructions
231system.cpu.num_store_insts 938 # Number of store instructions
232system.cpu.num_idle_cycles 0 # Number of idle cycles
233system.cpu.num_busy_cycles 5742 # Number of busy cycles
234system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
235system.cpu.idle_fraction 0 # Percentage of idle cycles
236system.cpu.Branches 1007 # Number of branches fetched

237system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction
238system.cpu.op_class::IntAlu 3597 62.64% 62.64% # Class of executed instruction
239system.cpu.op_class::IntMult 4 0.07% 62.71% # Class of executed instruction
240system.cpu.op_class::IntDiv 0 0.00% 62.71% # Class of executed instruction
241system.cpu.op_class::FloatAdd 0 0.00% 62.71% # Class of executed instruction
242system.cpu.op_class::FloatCmp 0 0.00% 62.71% # Class of executed instruction
243system.cpu.op_class::FloatCvt 0 0.00% 62.71% # Class of executed instruction
244system.cpu.op_class::FloatMult 0 0.00% 62.71% # Class of executed instruction
245system.cpu.op_class::FloatDiv 0 0.00% 62.71% # Class of executed instruction
246system.cpu.op_class::FloatSqrt 0 0.00% 62.71% # Class of executed instruction
247system.cpu.op_class::SimdAdd 0 0.00% 62.71% # Class of executed instruction
248system.cpu.op_class::SimdAddAcc 0 0.00% 62.71% # Class of executed instruction
249system.cpu.op_class::SimdAlu 0 0.00% 62.71% # Class of executed instruction
250system.cpu.op_class::SimdCmp 0 0.00% 62.71% # Class of executed instruction
251system.cpu.op_class::SimdCvt 0 0.00% 62.71% # Class of executed instruction
252system.cpu.op_class::SimdMisc 0 0.00% 62.71% # Class of executed instruction
253system.cpu.op_class::SimdMult 0 0.00% 62.71% # Class of executed instruction
254system.cpu.op_class::SimdMultAcc 0 0.00% 62.71% # Class of executed instruction
255system.cpu.op_class::SimdShift 0 0.00% 62.71% # Class of executed instruction
256system.cpu.op_class::SimdShiftAcc 0 0.00% 62.71% # Class of executed instruction
257system.cpu.op_class::SimdSqrt 0 0.00% 62.71% # Class of executed instruction
258system.cpu.op_class::SimdFloatAdd 0 0.00% 62.71% # Class of executed instruction
259system.cpu.op_class::SimdFloatAlu 0 0.00% 62.71% # Class of executed instruction
260system.cpu.op_class::SimdFloatCmp 0 0.00% 62.71% # Class of executed instruction
261system.cpu.op_class::SimdFloatCvt 0 0.00% 62.71% # Class of executed instruction
262system.cpu.op_class::SimdFloatDiv 0 0.00% 62.71% # Class of executed instruction
263system.cpu.op_class::SimdFloatMisc 3 0.05% 62.77% # Class of executed instruction
264system.cpu.op_class::SimdFloatMult 0 0.00% 62.77% # Class of executed instruction
265system.cpu.op_class::SimdFloatMultAcc 0 0.00% 62.77% # Class of executed instruction
266system.cpu.op_class::SimdFloatSqrt 0 0.00% 62.77% # Class of executed instruction
267system.cpu.op_class::MemRead 1200 20.90% 83.66% # Class of executed instruction
268system.cpu.op_class::MemWrite 938 16.34% 100.00% # Class of executed instruction
269system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
270system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
271system.cpu.op_class::total 5742 # Class of executed instruction