1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2875500 # Number of ticks simulated
5final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 415244 # Simulator instruction rate (inst/s)
8host_op_rate 516464 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 258032084 # Simulator tick rate (ticks/s)
10host_mem_usage 219364 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 22944 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 3648 # Number of bytes written to this memory
17system.physmem.num_reads 5771 # Number of read requests responded to by this memory
18system.physmem.num_writes 924 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
25system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
26system.cpu.checker.dtb.read_hits 0 # DTB read hits
27system.cpu.checker.dtb.read_misses 0 # DTB read misses
28system.cpu.checker.dtb.write_hits 0 # DTB write hits
29system.cpu.checker.dtb.write_misses 0 # DTB write misses
30system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 104 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000003 # Number of seconds simulated
4sim_ticks 2875500 # Number of ticks simulated
5final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 415244 # Simulator instruction rate (inst/s)
8host_op_rate 516464 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 258032084 # Simulator tick rate (ticks/s)
10host_mem_usage 219364 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 4600 # Number of instructions simulated
13sim_ops 5739 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 22944 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 3648 # Number of bytes written to this memory
17system.physmem.num_reads 5771 # Number of read requests responded to by this memory
18system.physmem.num_writes 924 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 7979134064 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 6416970962 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_write 1268648931 # Write bandwidth from this memory (bytes/s)
23system.physmem.bw_total 9247782994 # Total bandwidth to/from this memory (bytes/s)
24system.cpu.checker.dtb.inst_hits 0 # ITB inst hits
25system.cpu.checker.dtb.inst_misses 0 # ITB inst misses
26system.cpu.checker.dtb.read_hits 0 # DTB read hits
27system.cpu.checker.dtb.read_misses 0 # DTB read misses
28system.cpu.checker.dtb.write_hits 0 # DTB write hits
29system.cpu.checker.dtb.write_misses 0 # DTB write misses
30system.cpu.checker.dtb.flush_tlb 0 # Number of times complete TLB was flushed
31system.cpu.checker.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
--- 104 unchanged lines hidden ---