| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16494000 # Number of ticks simulated 5final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16494000 # Number of ticks simulated 5final_tick 16494000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 66928 # Simulator instruction rate (inst/s) 8host_op_rate 83502 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 240363471 # Simulator tick rate (ticks/s) 10host_mem_usage 244336 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 36590 # Simulator instruction rate (inst/s) 8host_op_rate 45651 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 131406771 # Simulator tick rate (ticks/s) 10host_mem_usage 240696 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 393 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 393 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1051533891 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 473384261 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1524918152 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1051533891 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1051533891 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1051533891 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 473384261 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1524918152 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 393 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady | 30system.physmem.readReqs 393 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 393 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 33system.physmem.bytesRead 25152 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() | 34system.physmem.bytesRead 25152 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q |
| 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 189system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap 41823.16 # Average gap between requests 192system.membus.throughput 1524918152 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 352 # Transaction distribution 194system.membus.trans_dist::ReadResp 352 # Transaction distribution 195system.membus.trans_dist::ReadExReq 41 # Transaction distribution 196system.membus.trans_dist::ReadExResp 41 # Transaction distribution | 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 190system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 41823.16 # Average gap between requests 193system.membus.throughput 1524918152 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 352 # Transaction distribution 195system.membus.trans_dist::ReadResp 352 # Transaction distribution 196system.membus.trans_dist::ReadExReq 41 # Transaction distribution 197system.membus.trans_dist::ReadExResp 41 # Transaction distribution |
| 197system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) | 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 786 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 786 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25152 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 25152 # Cumulative packet size per connected master and slave (bytes) |
| 201system.membus.data_through_bus 25152 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 205system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 22.3 # Layer utilization (%) 207system.cpu.branchPred.lookups 2479 # Number of BP lookups 208system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted --- 304 unchanged lines hidden (view full) --- 513system.cpu.fp_regfile_reads 16 # number of floating regfile reads 514system.cpu.misc_regfile_reads 2975 # number of misc regfile reads 515system.cpu.misc_regfile_writes 24 # number of misc regfile writes 516system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) 517system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 520system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution | 202system.membus.data_through_bus 25152 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 487500 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 206system.membus.respLayer1.occupancy 3671250 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 22.3 # Layer utilization (%) 208system.cpu.branchPred.lookups 2479 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1778 # Number of conditional branches predicted --- 304 unchanged lines hidden (view full) --- 514system.cpu.fp_regfile_reads 16 # number of floating regfile reads 515system.cpu.misc_regfile_reads 2975 # number of misc regfile reads 516system.cpu.misc_regfile_writes 24 # number of misc regfile writes 517system.cpu.toL2Bus.throughput 1695646902 # Throughput (bytes/s) 518system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 520system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 521system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution |
| 521system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) 522system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) 524system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) | 522system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 524system.cpu.toL2Bus.pkt_count::total 875 # Packet count per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 527system.cpu.toL2Bus.tot_pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) |
| 527system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) 528system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 529system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) 530system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 531system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) 532system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 533system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) 534system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) | 528system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) 529system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 530system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) 531system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 532system.cpu.toL2Bus.respLayer0.occupancy 485250 # Layer occupancy (ticks) 533system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) 534system.cpu.toL2Bus.respLayer1.occupancy 231495 # Layer occupancy (ticks) 535system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) |
| 535system.cpu.icache.tags.replacements 4 # number of replacements 536system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use 537system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. 538system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. 539system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. 540system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 541system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor 542system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy 543system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy | 536system.cpu.icache.tags.replacements 4 # number of replacements 537system.cpu.icache.tags.tagsinuse 145.483199 # Cycle average of tags in use 538system.cpu.icache.tags.total_refs 1583 # Total number of references to valid blocks. 539system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. 540system.cpu.icache.tags.avg_refs 5.439863 # Average number of references to valid blocks. 541system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 542system.cpu.icache.tags.occ_blocks::cpu.inst 145.483199 # Average occupied blocks per requestor 543system.cpu.icache.tags.occ_percent::cpu.inst 0.071037 # Average percentage of cache occupancy 544system.cpu.icache.tags.occ_percent::total 0.071037 # Average percentage of cache occupancy |
| 544system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits 545system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits 546system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits 547system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits 548system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits 549system.cpu.icache.overall_hits::total 1583 # number of overall hits 550system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 551system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 611system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 545system.cpu.icache.ReadReq_hits::cpu.inst 1583 # number of ReadReq hits 546system.cpu.icache.ReadReq_hits::total 1583 # number of ReadReq hits 547system.cpu.icache.demand_hits::cpu.inst 1583 # number of demand (read+write) hits 548system.cpu.icache.demand_hits::total 1583 # number of demand (read+write) hits 549system.cpu.icache.overall_hits::cpu.inst 1583 # number of overall hits 550system.cpu.icache.overall_hits::total 1583 # number of overall hits 551system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 552system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 612system.cpu.icache.overall_mshr_miss_rate::total 0.149461 # mshr miss rate for overall accesses 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64263.745704 # average ReadReq mshr miss latency 614system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64263.745704 # average ReadReq mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 616system.cpu.icache.demand_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64263.745704 # average overall mshr miss latency 618system.cpu.icache.overall_avg_mshr_miss_latency::total 64263.745704 # average overall mshr miss latency 619system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 619system.cpu.l2cache.tags.replacements 0 # number of replacements 620system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use 621system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 622system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. 623system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. 624system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 625system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor 626system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor | 620system.cpu.l2cache.tags.replacements 0 # number of replacements 621system.cpu.l2cache.tags.tagsinuse 183.328645 # Cycle average of tags in use 622system.cpu.l2cache.tags.total_refs 40 # Total number of references to valid blocks. 623system.cpu.l2cache.tags.sampled_refs 352 # Sample count of references to valid blocks. 624system.cpu.l2cache.tags.avg_refs 0.113636 # Average number of references to valid blocks. 625system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 626system.cpu.l2cache.tags.occ_blocks::cpu.inst 136.957008 # Average occupied blocks per requestor 627system.cpu.l2cache.tags.occ_blocks::cpu.data 46.371637 # Average occupied blocks per requestor |
| 627system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy 628system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy | 628system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004180 # Average percentage of cache occupancy 629system.cpu.l2cache.tags.occ_percent::cpu.data 0.001415 # Average percentage of cache occupancy |
| 629system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy | 630system.cpu.l2cache.tags.occ_percent::total 0.005595 # Average percentage of cache occupancy |
| 630system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 631system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 632system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 633system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 634system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 635system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 636system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 637system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits --- 107 unchanged lines hidden (view full) --- 745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency 746system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 748system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 749system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 751system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 752system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 631system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 632system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 633system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 634system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 635system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 636system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 637system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 638system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits --- 107 unchanged lines hidden (view full) --- 746system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60786.585366 # average ReadExReq mshr miss latency 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 748system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 749system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54591.328413 # average overall mshr miss latency 751system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60643.442623 # average overall mshr miss latency 752system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56470.101781 # average overall mshr miss latency 753system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 753system.cpu.dcache.tags.replacements 0 # number of replacements 754system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use 755system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. 756system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 757system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. 758system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 759system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor 760system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy 761system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy | 754system.cpu.dcache.tags.replacements 0 # number of replacements 755system.cpu.dcache.tags.tagsinuse 85.893510 # Cycle average of tags in use 756system.cpu.dcache.tags.total_refs 2390 # Total number of references to valid blocks. 757system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 758system.cpu.dcache.tags.avg_refs 16.369863 # Average number of references to valid blocks. 759system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 760system.cpu.dcache.tags.occ_blocks::cpu.data 85.893510 # Average occupied blocks per requestor 761system.cpu.dcache.tags.occ_percent::cpu.data 0.020970 # Average percentage of cache occupancy 762system.cpu.dcache.tags.occ_percent::total 0.020970 # Average percentage of cache occupancy |
| 762system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 763system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits 764system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 765system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 766system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 767system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 768system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 769system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 109 unchanged lines hidden --- | 763system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 764system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits 765system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 766system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 767system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 768system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 769system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 770system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 109 unchanged lines hidden --- |