| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000014 # Number of seconds simulated 4sim_ticks 13706000 # Number of ticks simulated 5final_tick 13706000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16387000 # Number of ticks simulated 5final_tick 16387000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 7143 # Simulator instruction rate (inst/s) 8host_op_rate 8913 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 21323596 # Simulator tick rate (ticks/s) 10host_mem_usage 284080 # Number of bytes of host memory used 11host_seconds 0.64 # Real time elapsed on the host | 7host_inst_rate 36614 # Simulator instruction rate (inst/s) 8host_op_rate 45680 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 130634561 # Simulator tick rate (ticks/s) 10host_mem_usage 244344 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory | 14system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory |
| 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory | 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory |
| 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory | 16system.physmem.bytes_read::total 25152 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory |
| 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory | 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory |
| 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1270100686 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 569677513 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1839778199 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1270100686 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1270100686 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1270100686 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 569677513 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1839778199 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 394 # Total number of read requests seen | 21system.physmem.num_reads::total 393 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1058399951 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 476475255 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1534875206 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1058399951 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1058399951 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1058399951 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 476475255 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1534875206 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.readReqs 393 # Total number of read requests seen |
| 31system.physmem.writeReqs 0 # Total number of write requests seen | 31system.physmem.writeReqs 0 # Total number of write requests seen |
| 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory | 32system.physmem.cpureqs 393 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25152 # Total number of bytes read from memory |
| 34system.physmem.bytesWritten 0 # Total number of bytes written to memory | 34system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() | 35system.physmem.bytesConsumedRd 25152 # bytesRead derated as per pkt->getSize() |
| 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 26 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 32 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 29 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 29 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 40 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 12 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 12 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 36 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 22 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 18 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 7 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 43 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 33 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 9 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 15 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 86 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 46 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 20 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 42 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 17 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 34 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 35 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 10 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 4 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 8 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 28 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 42 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 9 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 6 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 6 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 13648500 # Total gap between requests | 73system.physmem.totGap 16329500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| 80system.physmem.readPktSize::6 394 # Categorize read packet sizes | 80system.physmem.readPktSize::6 393 # Categorize read packet sizes |
| 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 194 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 213 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 42 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see |
| 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 93system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 2507750 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 11751500 # Sum of mem lat for all requests 154system.physmem.totBusLat 1970000 # Total cycles spent in databus access 155system.physmem.totBankLat 7273750 # Total cycles spent in bank access 156system.physmem.avgQLat 6364.85 # Average queueing delay per request 157system.physmem.avgBankLat 18461.29 # Average bank access latency per request | 152system.physmem.bytesPerActivate::samples 45 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 335.644444 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 165.301810 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 465.758285 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 21 46.67% 46.67% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 5 11.11% 57.78% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 4 8.89% 66.67% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 3 6.67% 73.33% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 2 4.44% 77.78% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::448 1 2.22% 80.00% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::512 1 2.22% 82.22% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::704 1 2.22% 84.44% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::960 1 2.22% 86.67% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::1024 1 2.22% 88.89% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::1152 1 2.22% 91.11% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::1216 1 2.22% 93.33% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1536 2 4.44% 97.78% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::1856 1 2.22% 100.00% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::total 45 # Bytes accessed per row activation 171system.physmem.totQLat 2029000 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 9466500 # Sum of mem lat for all requests 173system.physmem.totBusLat 1965000 # Total cycles spent in databus access 174system.physmem.totBankLat 5472500 # Total cycles spent in bank access 175system.physmem.avgQLat 5162.85 # Average queueing delay per request 176system.physmem.avgBankLat 13924.94 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 29826.14 # Average memory access latency 160system.physmem.avgRdBW 1839.78 # Average achieved read bandwidth in MB/s | 178system.physmem.avgMemAccLat 24087.79 # Average memory access latency 179system.physmem.avgRdBW 1534.88 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1839.78 # Average consumed read bandwidth in MB/s | 181system.physmem.avgConsumedRdBW 1534.88 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 14.37 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.86 # Average read queue length over time | 184system.physmem.busUtil 11.99 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.58 # Average read queue length over time |
| 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 186system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 294 # Number of row buffer hits during reads | 187system.physmem.readRowHits 348 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 74.62 # Row buffer hit rate for reads | 189system.physmem.readRowHitRate 88.55 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 34640.86 # Average gap between requests 173system.cpu.branchPred.lookups 2491 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1787 # Number of conditional branches predicted | 191system.physmem.avgGap 41550.89 # Average gap between requests 192system.membus.throughput 1534875206 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 352 # Transaction distribution 194system.membus.trans_dist::ReadResp 352 # Transaction distribution 195system.membus.trans_dist::ReadExReq 41 # Transaction distribution 196system.membus.trans_dist::ReadExResp 41 # Transaction distribution 197system.membus.pkt_count_system.cpu.l2cache.mem_side 786 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 786 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 25152 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 25152 # Cumulative packet size per connected master and slave (bytes) 201system.membus.data_through_bus 25152 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 480500 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 205system.membus.respLayer1.occupancy 3664000 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 22.4 # Layer utilization (%) 207system.cpu.branchPred.lookups 2471 # Number of BP lookups 208system.cpu.branchPred.condPredicted 1774 # Number of conditional branches predicted |
| 175system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect | 209system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect |
| 176system.cpu.branchPred.BTBLookups 1976 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 700 # Number of BTB hits | 210system.cpu.branchPred.BTBLookups 1960 # Number of BTB lookups 211system.cpu.branchPred.BTBHits 695 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 212system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 35.425101 # BTB Hit Percentage | 213system.cpu.branchPred.BTBHitPct 35.459184 # BTB Hit Percentage |
| 180system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 182system.cpu.dtb.inst_hits 0 # ITB inst hits 183system.cpu.dtb.inst_misses 0 # ITB inst misses 184system.cpu.dtb.read_hits 0 # DTB read hits 185system.cpu.dtb.read_misses 0 # DTB read misses 186system.cpu.dtb.write_hits 0 # DTB write hits 187system.cpu.dtb.write_misses 0 # DTB write misses --- 29 unchanged lines hidden (view full) --- 217system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 218system.cpu.itb.read_accesses 0 # DTB read accesses 219system.cpu.itb.write_accesses 0 # DTB write accesses 220system.cpu.itb.inst_accesses 0 # ITB inst accesses 221system.cpu.itb.hits 0 # DTB hits 222system.cpu.itb.misses 0 # DTB misses 223system.cpu.itb.accesses 0 # DTB accesses 224system.cpu.workload.num_syscalls 13 # Number of system calls | 214system.cpu.branchPred.usedRAS 292 # Number of times the RAS was used to get a target. 215system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. 216system.cpu.dtb.inst_hits 0 # ITB inst hits 217system.cpu.dtb.inst_misses 0 # ITB inst misses 218system.cpu.dtb.read_hits 0 # DTB read hits 219system.cpu.dtb.read_misses 0 # DTB read misses 220system.cpu.dtb.write_hits 0 # DTB write hits 221system.cpu.dtb.write_misses 0 # DTB write misses --- 29 unchanged lines hidden (view full) --- 251system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 252system.cpu.itb.read_accesses 0 # DTB read accesses 253system.cpu.itb.write_accesses 0 # DTB write accesses 254system.cpu.itb.inst_accesses 0 # ITB inst accesses 255system.cpu.itb.hits 0 # DTB hits 256system.cpu.itb.misses 0 # DTB misses 257system.cpu.itb.accesses 0 # DTB accesses 258system.cpu.workload.num_syscalls 13 # Number of system calls |
| 225system.cpu.numCycles 27413 # number of cpu cycles simulated | 259system.cpu.numCycles 32775 # number of cpu cycles simulated |
| 226system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 227system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 260system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 261system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 228system.cpu.fetch.icacheStallCycles 6976 # Number of cycles fetch is stalled on an Icache miss 229system.cpu.fetch.Insts 11965 # Number of instructions fetch has processed 230system.cpu.fetch.Branches 2491 # Number of branches that fetch encountered 231system.cpu.fetch.predictedBranches 992 # Number of branches that fetch has predicted taken 232system.cpu.fetch.Cycles 2644 # Number of cycles fetch has run and was not squashing or blocked 233system.cpu.fetch.SquashCycles 1618 # Number of cycles fetch has spent squashing 234system.cpu.fetch.BlockedCycles 2255 # Number of cycles fetch has spent blocked 235system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched 236system.cpu.fetch.IcacheSquashes 282 # Number of outstanding Icache misses that were squashed 237system.cpu.fetch.rateDist::samples 12987 # Number of instructions fetched each cycle (Total) 238system.cpu.fetch.rateDist::mean 1.170247 # Number of instructions fetched each cycle (Total) 239system.cpu.fetch.rateDist::stdev 2.582932 # Number of instructions fetched each cycle (Total) | 262system.cpu.fetch.icacheStallCycles 6975 # Number of cycles fetch is stalled on an Icache miss 263system.cpu.fetch.Insts 11884 # Number of instructions fetch has processed 264system.cpu.fetch.Branches 2471 # Number of branches that fetch encountered 265system.cpu.fetch.predictedBranches 987 # Number of branches that fetch has predicted taken 266system.cpu.fetch.Cycles 2620 # Number of cycles fetch has run and was not squashing or blocked 267system.cpu.fetch.SquashCycles 1611 # Number of cycles fetch has spent squashing 268system.cpu.fetch.BlockedCycles 2625 # Number of cycles fetch has spent blocked 269system.cpu.fetch.CacheLines 1942 # Number of cache lines fetched 270system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed 271system.cpu.fetch.rateDist::samples 13325 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::mean 1.128105 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.rateDist::stdev 2.544240 # Number of instructions fetched each cycle (Total) |
| 240system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 274system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 241system.cpu.fetch.rateDist::0 10343 79.64% 79.64% # Number of instructions fetched each cycle (Total) 242system.cpu.fetch.rateDist::1 225 1.73% 81.37% # Number of instructions fetched each cycle (Total) 243system.cpu.fetch.rateDist::2 203 1.56% 82.94% # Number of instructions fetched each cycle (Total) 244system.cpu.fetch.rateDist::3 225 1.73% 84.67% # Number of instructions fetched each cycle (Total) 245system.cpu.fetch.rateDist::4 221 1.70% 86.37% # Number of instructions fetched each cycle (Total) 246system.cpu.fetch.rateDist::5 273 2.10% 88.47% # Number of instructions fetched each cycle (Total) 247system.cpu.fetch.rateDist::6 93 0.72% 89.19% # Number of instructions fetched each cycle (Total) 248system.cpu.fetch.rateDist::7 147 1.13% 90.32% # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::8 1257 9.68% 100.00% # Number of instructions fetched each cycle (Total) | 275system.cpu.fetch.rateDist::0 10705 80.34% 80.34% # Number of instructions fetched each cycle (Total) 276system.cpu.fetch.rateDist::1 226 1.70% 82.03% # Number of instructions fetched each cycle (Total) 277system.cpu.fetch.rateDist::2 201 1.51% 83.54% # Number of instructions fetched each cycle (Total) 278system.cpu.fetch.rateDist::3 224 1.68% 85.22% # Number of instructions fetched each cycle (Total) 279system.cpu.fetch.rateDist::4 220 1.65% 86.87% # Number of instructions fetched each cycle (Total) 280system.cpu.fetch.rateDist::5 270 2.03% 88.90% # Number of instructions fetched each cycle (Total) 281system.cpu.fetch.rateDist::6 92 0.69% 89.59% # Number of instructions fetched each cycle (Total) 282system.cpu.fetch.rateDist::7 146 1.10% 90.69% # Number of instructions fetched each cycle (Total) 283system.cpu.fetch.rateDist::8 1241 9.31% 100.00% # Number of instructions fetched each cycle (Total) |
| 250system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 251system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 284system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 253system.cpu.fetch.rateDist::total 12987 # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.branchRate 0.090869 # Number of branch fetches per cycle 255system.cpu.fetch.rate 0.436472 # Number of inst fetches per cycle 256system.cpu.decode.IdleCycles 6960 # Number of cycles decode is idle 257system.cpu.decode.BlockedCycles 2563 # Number of cycles decode is blocked 258system.cpu.decode.RunCycles 2438 # Number of cycles decode is running 259system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 260system.cpu.decode.SquashCycles 957 # Number of cycles decode is squashing 261system.cpu.decode.BranchResolved 388 # Number of times decode resolved a branch 262system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 263system.cpu.decode.DecodedInsts 13303 # Number of instructions handled by decode | 287system.cpu.fetch.rateDist::total 13325 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.branchRate 0.075393 # Number of branch fetches per cycle 289system.cpu.fetch.rate 0.362593 # Number of inst fetches per cycle 290system.cpu.decode.IdleCycles 6989 # Number of cycles decode is idle 291system.cpu.decode.BlockedCycles 2898 # Number of cycles decode is blocked 292system.cpu.decode.RunCycles 2415 # Number of cycles decode is running 293system.cpu.decode.UnblockCycles 73 # Number of cycles decode is unblocking 294system.cpu.decode.SquashCycles 950 # Number of cycles decode is squashing 295system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch 296system.cpu.decode.BranchMispred 159 # Number of times decode detected a branch misprediction 297system.cpu.decode.DecodedInsts 13178 # Number of instructions handled by decode |
| 264system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode | 298system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode |
| 265system.cpu.rename.SquashCycles 957 # Number of cycles rename is squashing 266system.cpu.rename.IdleCycles 7226 # Number of cycles rename is idle 267system.cpu.rename.BlockCycles 330 # Number of cycles rename is blocking 268system.cpu.rename.serializeStallCycles 2025 # count of cycles rename stalled for serializing inst 269system.cpu.rename.RunCycles 2238 # Number of cycles rename is running 270system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 271system.cpu.rename.RenamedInsts 12535 # Number of instructions processed by rename 272system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 273system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 274system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full 275system.cpu.rename.RenamedOperands 12533 # Number of destination operands rename has renamed 276system.cpu.rename.RenameLookups 56960 # Number of register rename lookups that rename has made 277system.cpu.rename.int_rename_lookups 56600 # Number of integer rename lookups 278system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups | 299system.cpu.rename.SquashCycles 950 # Number of cycles rename is squashing 300system.cpu.rename.IdleCycles 7255 # Number of cycles rename is idle 301system.cpu.rename.BlockCycles 368 # Number of cycles rename is blocking 302system.cpu.rename.serializeStallCycles 2315 # count of cycles rename stalled for serializing inst 303system.cpu.rename.RunCycles 2217 # Number of cycles rename is running 304system.cpu.rename.UnblockCycles 220 # Number of cycles rename is unblocking 305system.cpu.rename.RenamedInsts 12419 # Number of instructions processed by rename 306system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 307system.cpu.rename.IQFullEvents 9 # Number of times rename has blocked due to IQ full 308system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full 309system.cpu.rename.RenamedOperands 12443 # Number of destination operands rename has renamed 310system.cpu.rename.RenameLookups 56366 # Number of register rename lookups that rename has made 311system.cpu.rename.int_rename_lookups 56110 # Number of integer rename lookups 312system.cpu.rename.fp_rename_lookups 256 # Number of floating rename lookups |
| 279system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed | 313system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed |
| 280system.cpu.rename.UndoneMaps 6860 # Number of HB maps that are undone due to squashing | 314system.cpu.rename.UndoneMaps 6770 # Number of HB maps that are undone due to squashing |
| 281system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 282system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed | 315system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 316system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed |
| 283system.cpu.rename.skidInsts 677 # count of insts added to the skid buffer 284system.cpu.memDep0.insertedLoads 2799 # Number of loads inserted to the mem dependence unit. 285system.cpu.memDep0.insertedStores 1592 # Number of stores inserted to the mem dependence unit. | 317system.cpu.rename.skidInsts 688 # count of insts added to the skid buffer 318system.cpu.memDep0.insertedLoads 2784 # Number of loads inserted to the mem dependence unit. 319system.cpu.memDep0.insertedStores 1569 # Number of stores inserted to the mem dependence unit. |
| 286system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. | 320system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. |
| 287system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 288system.cpu.iq.iqInstsAdded 11241 # Number of instructions added to the IQ (excludes non-spec) | 321system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 322system.cpu.iq.iqInstsAdded 11162 # Number of instructions added to the IQ (excludes non-spec) |
| 289system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ | 323system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ |
| 290system.cpu.iq.iqInstsIssued 8967 # Number of instructions issued 291system.cpu.iq.iqSquashedInstsIssued 119 # Number of squashed instructions issued 292system.cpu.iq.iqSquashedInstsExamined 5221 # Number of squashed instructions iterated over during squash; mainly for profiling 293system.cpu.iq.iqSquashedOperandsExamined 14417 # Number of squashed operands that are examined and possibly removed from graph | 324system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 325system.cpu.iq.iqSquashedInstsIssued 111 # Number of squashed instructions issued 326system.cpu.iq.iqSquashedInstsExamined 5126 # Number of squashed instructions iterated over during squash; mainly for profiling 327system.cpu.iq.iqSquashedOperandsExamined 14148 # Number of squashed operands that are examined and possibly removed from graph |
| 294system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed | 328system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed |
| 295system.cpu.iq.issued_per_cycle::samples 12987 # Number of insts issued each cycle 296system.cpu.iq.issued_per_cycle::mean 0.690460 # Number of insts issued each cycle 297system.cpu.iq.issued_per_cycle::stdev 1.397167 # Number of insts issued each cycle | 329system.cpu.iq.issued_per_cycle::samples 13325 # Number of insts issued each cycle 330system.cpu.iq.issued_per_cycle::mean 0.669493 # Number of insts issued each cycle 331system.cpu.iq.issued_per_cycle::stdev 1.373683 # Number of insts issued each cycle |
| 298system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 332system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 299system.cpu.iq.issued_per_cycle::0 9407 72.43% 72.43% # Number of insts issued each cycle 300system.cpu.iq.issued_per_cycle::1 1316 10.13% 82.57% # Number of insts issued each cycle 301system.cpu.iq.issued_per_cycle::2 806 6.21% 88.77% # Number of insts issued each cycle 302system.cpu.iq.issued_per_cycle::3 531 4.09% 92.86% # Number of insts issued each cycle 303system.cpu.iq.issued_per_cycle::4 466 3.59% 96.45% # Number of insts issued each cycle 304system.cpu.iq.issued_per_cycle::5 267 2.06% 98.51% # Number of insts issued each cycle 305system.cpu.iq.issued_per_cycle::6 125 0.96% 99.47% # Number of insts issued each cycle 306system.cpu.iq.issued_per_cycle::7 55 0.42% 99.89% # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::8 14 0.11% 100.00% # Number of insts issued each cycle | 333system.cpu.iq.issued_per_cycle::0 9737 73.07% 73.07% # Number of insts issued each cycle 334system.cpu.iq.issued_per_cycle::1 1330 9.98% 83.05% # Number of insts issued each cycle 335system.cpu.iq.issued_per_cycle::2 808 6.06% 89.12% # Number of insts issued each cycle 336system.cpu.iq.issued_per_cycle::3 537 4.03% 93.15% # Number of insts issued each cycle 337system.cpu.iq.issued_per_cycle::4 465 3.49% 96.64% # Number of insts issued each cycle 338system.cpu.iq.issued_per_cycle::5 260 1.95% 98.59% # Number of insts issued each cycle 339system.cpu.iq.issued_per_cycle::6 124 0.93% 99.52% # Number of insts issued each cycle 340system.cpu.iq.issued_per_cycle::7 52 0.39% 99.91% # Number of insts issued each cycle 341system.cpu.iq.issued_per_cycle::8 12 0.09% 100.00% # Number of insts issued each cycle |
| 308system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 309system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 342system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 311system.cpu.iq.issued_per_cycle::total 12987 # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::total 13325 # Number of insts issued each cycle |
| 312system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 346system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 313system.cpu.iq.fu_full::IntAlu 8 3.48% 3.48% # attempts to use FU when none available 314system.cpu.iq.fu_full::IntMult 0 0.00% 3.48% # attempts to use FU when none available 315system.cpu.iq.fu_full::IntDiv 0 0.00% 3.48% # attempts to use FU when none available 316system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.48% # attempts to use FU when none available 317system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.48% # attempts to use FU when none available 318system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.48% # attempts to use FU when none available 319system.cpu.iq.fu_full::FloatMult 0 0.00% 3.48% # attempts to use FU when none available 320system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.48% # attempts to use FU when none available 321system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.48% # attempts to use FU when none available 322system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.48% # attempts to use FU when none available 323system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.48% # attempts to use FU when none available 324system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.48% # attempts to use FU when none available 325system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.48% # attempts to use FU when none available 326system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.48% # attempts to use FU when none available 327system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.48% # attempts to use FU when none available 328system.cpu.iq.fu_full::SimdMult 0 0.00% 3.48% # attempts to use FU when none available 329system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.48% # attempts to use FU when none available 330system.cpu.iq.fu_full::SimdShift 0 0.00% 3.48% # attempts to use FU when none available 331system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.48% # attempts to use FU when none available 332system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.48% # attempts to use FU when none available 333system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.48% # attempts to use FU when none available 334system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.48% # attempts to use FU when none available 335system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.48% # attempts to use FU when none available 336system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.48% # attempts to use FU when none available 337system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.48% # attempts to use FU when none available 338system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.48% # attempts to use FU when none available 339system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.48% # attempts to use FU when none available 340system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.48% # attempts to use FU when none available 341system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.48% # attempts to use FU when none available 342system.cpu.iq.fu_full::MemRead 144 62.61% 66.09% # attempts to use FU when none available 343system.cpu.iq.fu_full::MemWrite 78 33.91% 100.00% # attempts to use FU when none available | 347system.cpu.iq.fu_full::IntAlu 6 2.69% 2.69% # attempts to use FU when none available 348system.cpu.iq.fu_full::IntMult 0 0.00% 2.69% # attempts to use FU when none available 349system.cpu.iq.fu_full::IntDiv 0 0.00% 2.69% # attempts to use FU when none available 350system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.69% # attempts to use FU when none available 351system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.69% # attempts to use FU when none available 352system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.69% # attempts to use FU when none available 353system.cpu.iq.fu_full::FloatMult 0 0.00% 2.69% # attempts to use FU when none available 354system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.69% # attempts to use FU when none available 355system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.69% # attempts to use FU when none available 356system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.69% # attempts to use FU when none available 357system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.69% # attempts to use FU when none available 358system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.69% # attempts to use FU when none available 359system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.69% # attempts to use FU when none available 360system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.69% # attempts to use FU when none available 361system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.69% # attempts to use FU when none available 362system.cpu.iq.fu_full::SimdMult 0 0.00% 2.69% # attempts to use FU when none available 363system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.69% # attempts to use FU when none available 364system.cpu.iq.fu_full::SimdShift 0 0.00% 2.69% # attempts to use FU when none available 365system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.69% # attempts to use FU when none available 366system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.69% # attempts to use FU when none available 367system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.69% # attempts to use FU when none available 368system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.69% # attempts to use FU when none available 369system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.69% # attempts to use FU when none available 370system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.69% # attempts to use FU when none available 371system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.69% # attempts to use FU when none available 372system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.69% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.69% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.69% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.69% # attempts to use FU when none available 376system.cpu.iq.fu_full::MemRead 139 62.33% 65.02% # attempts to use FU when none available 377system.cpu.iq.fu_full::MemWrite 78 34.98% 100.00% # attempts to use FU when none available |
| 344system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 345system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 346system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 378system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 379system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 380system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 347system.cpu.iq.FU_type_0::IntAlu 5390 60.11% 60.11% # Type of FU issued 348system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.19% # Type of FU issued 349system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.19% # Type of FU issued 350system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.19% # Type of FU issued 351system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.19% # Type of FU issued 352system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.19% # Type of FU issued 353system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.19% # Type of FU issued 354system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.19% # Type of FU issued 355system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.19% # Type of FU issued 356system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.19% # Type of FU issued 357system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.19% # Type of FU issued 358system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.19% # Type of FU issued 359system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.19% # Type of FU issued 360system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.19% # Type of FU issued 361system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.19% # Type of FU issued 362system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.19% # Type of FU issued 363system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.19% # Type of FU issued 364system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.19% # Type of FU issued 365system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.19% # Type of FU issued 366system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.19% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.19% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.19% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.19% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.19% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.19% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.22% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.22% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.22% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.22% # Type of FU issued 376system.cpu.iq.FU_type_0::MemRead 2344 26.14% 86.36% # Type of FU issued 377system.cpu.iq.FU_type_0::MemWrite 1223 13.64% 100.00% # Type of FU issued | 381system.cpu.iq.FU_type_0::IntAlu 5362 60.11% 60.11% # Type of FU issued 382system.cpu.iq.FU_type_0::IntMult 9 0.10% 60.21% # Type of FU issued 383system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.21% # Type of FU issued 384system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.21% # Type of FU issued 385system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.21% # Type of FU issued 386system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.21% # Type of FU issued 387system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.21% # Type of FU issued 388system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.21% # Type of FU issued 389system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.21% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.21% # Type of FU issued 391system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.21% # Type of FU issued 392system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.21% # Type of FU issued 393system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.21% # Type of FU issued 394system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.21% # Type of FU issued 395system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.21% # Type of FU issued 396system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.21% # Type of FU issued 397system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.21% # Type of FU issued 398system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.21% # Type of FU issued 399system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.21% # Type of FU issued 400system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.21% # Type of FU issued 401system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.21% # Type of FU issued 402system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.21% # Type of FU issued 403system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.21% # Type of FU issued 404system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.21% # Type of FU issued 405system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.21% # Type of FU issued 406system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.24% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.24% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued 410system.cpu.iq.FU_type_0::MemRead 2334 26.16% 86.40% # Type of FU issued 411system.cpu.iq.FU_type_0::MemWrite 1213 13.60% 100.00% # Type of FU issued |
| 378system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 379system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 412system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 413system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 380system.cpu.iq.FU_type_0::total 8967 # Type of FU issued 381system.cpu.iq.rate 0.327108 # Inst issue rate 382system.cpu.iq.fu_busy_cnt 230 # FU busy when requested 383system.cpu.iq.fu_busy_rate 0.025650 # FU busy rate (busy events/executed inst) 384system.cpu.iq.int_inst_queue_reads 31234 # Number of integer instruction queue reads 385system.cpu.iq.int_inst_queue_writes 16481 # Number of integer instruction queue writes 386system.cpu.iq.int_inst_queue_wakeup_accesses 8073 # Number of integer instruction queue wakeup accesses | 414system.cpu.iq.FU_type_0::total 8921 # Type of FU issued 415system.cpu.iq.rate 0.272189 # Inst issue rate 416system.cpu.iq.fu_busy_cnt 223 # FU busy when requested 417system.cpu.iq.fu_busy_rate 0.024997 # FU busy rate (busy events/executed inst) 418system.cpu.iq.int_inst_queue_reads 31465 # Number of integer instruction queue reads 419system.cpu.iq.int_inst_queue_writes 16306 # Number of integer instruction queue writes 420system.cpu.iq.int_inst_queue_wakeup_accesses 8052 # Number of integer instruction queue wakeup accesses |
| 387system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 388system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 389system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 421system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 422system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 423system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 390system.cpu.iq.int_alu_accesses 9177 # Number of integer alu accesses | 424system.cpu.iq.int_alu_accesses 9124 # Number of integer alu accesses |
| 391system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses | 425system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses |
| 392system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores | 426system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores |
| 393system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 427system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 394system.cpu.iew.lsq.thread0.squashedLoads 1599 # Number of loads squashed | 428system.cpu.iew.lsq.thread0.squashedLoads 1584 # Number of loads squashed |
| 395system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed | 429system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| 396system.cpu.iew.lsq.thread0.memOrderViolation 22 # Number of memory ordering violations 397system.cpu.iew.lsq.thread0.squashedStores 654 # Number of stores squashed | 430system.cpu.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations 431system.cpu.iew.lsq.thread0.squashedStores 631 # Number of stores squashed |
| 398system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 399system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 400system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 401system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 402system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 432system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 433system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 434system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 435system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 436system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 403system.cpu.iew.iewSquashCycles 957 # Number of cycles IEW is squashing 404system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 405system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 406system.cpu.iew.iewDispatchedInsts 11290 # Number of instructions dispatched to IQ 407system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch 408system.cpu.iew.iewDispLoadInsts 2799 # Number of dispatched load instructions 409system.cpu.iew.iewDispStoreInsts 1592 # Number of dispatched store instructions | 437system.cpu.iew.iewSquashCycles 950 # Number of cycles IEW is squashing 438system.cpu.iew.iewBlockCycles 232 # Number of cycles IEW is blocking 439system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking 440system.cpu.iew.iewDispatchedInsts 11211 # Number of instructions dispatched to IQ 441system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch 442system.cpu.iew.iewDispLoadInsts 2784 # Number of dispatched load instructions 443system.cpu.iew.iewDispStoreInsts 1569 # Number of dispatched store instructions |
| 410system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions | 444system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions |
| 411system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall | 445system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall |
| 412system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 446system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 413system.cpu.iew.memOrderViolationEvents 22 # Number of memory order violations | 447system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations |
| 414system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly | 448system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly |
| 415system.cpu.iew.predictedNotTakenIncorrect 271 # Number of branches that were predicted not taken incorrectly 416system.cpu.iew.branchMispredicts 379 # Number of branch mispredicts detected at execute 417system.cpu.iew.iewExecutedInsts 8545 # Number of executed instructions | 449system.cpu.iew.predictedNotTakenIncorrect 269 # Number of branches that were predicted not taken incorrectly 450system.cpu.iew.branchMispredicts 377 # Number of branch mispredicts detected at execute 451system.cpu.iew.iewExecutedInsts 8517 # Number of executed instructions |
| 418system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed | 452system.cpu.iew.iewExecLoadInsts 2134 # Number of load instructions executed |
| 419system.cpu.iew.iewExecSquashedInsts 422 # Number of squashed instructions skipped in execute | 453system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute |
| 420system.cpu.iew.exec_swp 0 # number of swp insts executed 421system.cpu.iew.exec_nop 0 # number of nop insts executed | 454system.cpu.iew.exec_swp 0 # number of swp insts executed 455system.cpu.iew.exec_nop 0 # number of nop insts executed |
| 422system.cpu.iew.exec_refs 3301 # number of memory reference insts executed 423system.cpu.iew.exec_branches 1438 # Number of branches executed 424system.cpu.iew.exec_stores 1167 # Number of stores executed 425system.cpu.iew.exec_rate 0.311713 # Inst execution rate 426system.cpu.iew.wb_sent 8247 # cumulative count of insts sent to commit 427system.cpu.iew.wb_count 8089 # cumulative count of insts written-back 428system.cpu.iew.wb_producers 3894 # num instructions producing a value 429system.cpu.iew.wb_consumers 7825 # num instructions consuming a value | 456system.cpu.iew.exec_refs 3294 # number of memory reference insts executed 457system.cpu.iew.exec_branches 1436 # Number of branches executed 458system.cpu.iew.exec_stores 1160 # Number of stores executed 459system.cpu.iew.exec_rate 0.259863 # Inst execution rate 460system.cpu.iew.wb_sent 8224 # cumulative count of insts sent to commit 461system.cpu.iew.wb_count 8068 # cumulative count of insts written-back 462system.cpu.iew.wb_producers 3885 # num instructions producing a value 463system.cpu.iew.wb_consumers 7780 # num instructions consuming a value |
| 430system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 464system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 431system.cpu.iew.wb_rate 0.295079 # insts written-back per cycle 432system.cpu.iew.wb_fanout 0.497636 # average fanout of values written-back | 465system.cpu.iew.wb_rate 0.246163 # insts written-back per cycle 466system.cpu.iew.wb_fanout 0.499357 # average fanout of values written-back |
| 433system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 467system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 434system.cpu.commit.commitSquashedInsts 5566 # The number of squashed insts skipped by commit | 468system.cpu.commit.commitSquashedInsts 5487 # The number of squashed insts skipped by commit |
| 435system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 436system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted | 469system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 470system.cpu.commit.branchMispredicts 327 # The number of times a branch was mispredicted |
| 437system.cpu.commit.committed_per_cycle::samples 12030 # Number of insts commited each cycle 438system.cpu.commit.committed_per_cycle::mean 0.476226 # Number of insts commited each cycle 439system.cpu.commit.committed_per_cycle::stdev 1.310563 # Number of insts commited each cycle | 471system.cpu.commit.committed_per_cycle::samples 12375 # Number of insts commited each cycle 472system.cpu.commit.committed_per_cycle::mean 0.462949 # Number of insts commited each cycle 473system.cpu.commit.committed_per_cycle::stdev 1.295788 # Number of insts commited each cycle |
| 440system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 474system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 441system.cpu.commit.committed_per_cycle::0 9744 81.00% 81.00% # Number of insts commited each cycle 442system.cpu.commit.committed_per_cycle::1 1074 8.93% 89.93% # Number of insts commited each cycle 443system.cpu.commit.committed_per_cycle::2 398 3.31% 93.23% # Number of insts commited each cycle 444system.cpu.commit.committed_per_cycle::3 256 2.13% 95.36% # Number of insts commited each cycle 445system.cpu.commit.committed_per_cycle::4 181 1.50% 96.87% # Number of insts commited each cycle 446system.cpu.commit.committed_per_cycle::5 172 1.43% 98.30% # Number of insts commited each cycle 447system.cpu.commit.committed_per_cycle::6 49 0.41% 98.70% # Number of insts commited each cycle 448system.cpu.commit.committed_per_cycle::7 35 0.29% 98.99% # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::8 121 1.01% 100.00% # Number of insts commited each cycle | 475system.cpu.commit.committed_per_cycle::0 10091 81.54% 81.54% # Number of insts commited each cycle 476system.cpu.commit.committed_per_cycle::1 1074 8.68% 90.22% # Number of insts commited each cycle 477system.cpu.commit.committed_per_cycle::2 396 3.20% 93.42% # Number of insts commited each cycle 478system.cpu.commit.committed_per_cycle::3 256 2.07% 95.49% # Number of insts commited each cycle 479system.cpu.commit.committed_per_cycle::4 180 1.45% 96.95% # Number of insts commited each cycle 480system.cpu.commit.committed_per_cycle::5 172 1.39% 98.34% # Number of insts commited each cycle 481system.cpu.commit.committed_per_cycle::6 49 0.40% 98.73% # Number of insts commited each cycle 482system.cpu.commit.committed_per_cycle::7 35 0.28% 99.01% # Number of insts commited each cycle 483system.cpu.commit.committed_per_cycle::8 122 0.99% 100.00% # Number of insts commited each cycle |
| 450system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 451system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 484system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 453system.cpu.commit.committed_per_cycle::total 12030 # Number of insts commited each cycle | 487system.cpu.commit.committed_per_cycle::total 12375 # Number of insts commited each cycle |
| 454system.cpu.commit.committedInsts 4591 # Number of instructions committed 455system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 456system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 457system.cpu.commit.refs 2138 # Number of memory references committed 458system.cpu.commit.loads 1200 # Number of loads committed 459system.cpu.commit.membars 12 # Number of memory barriers committed 460system.cpu.commit.branches 1007 # Number of branches committed 461system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 462system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 463system.cpu.commit.function_calls 82 # Number of function calls committed. | 488system.cpu.commit.committedInsts 4591 # Number of instructions committed 489system.cpu.commit.committedOps 5729 # Number of ops (including micro ops) committed 490system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 491system.cpu.commit.refs 2138 # Number of memory references committed 492system.cpu.commit.loads 1200 # Number of loads committed 493system.cpu.commit.membars 12 # Number of memory barriers committed 494system.cpu.commit.branches 1007 # Number of branches committed 495system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 496system.cpu.commit.int_insts 4976 # Number of committed integer instructions. 497system.cpu.commit.function_calls 82 # Number of function calls committed. |
| 464system.cpu.commit.bw_lim_events 121 # number cycles where commit BW limit reached | 498system.cpu.commit.bw_lim_events 122 # number cycles where commit BW limit reached |
| 465system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 499system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 466system.cpu.rob.rob_reads 23047 # The number of ROB reads 467system.cpu.rob.rob_writes 23560 # The number of ROB writes | 500system.cpu.rob.rob_reads 23312 # The number of ROB reads 501system.cpu.rob.rob_writes 23396 # The number of ROB writes |
| 468system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself | 502system.cpu.timesIdled 224 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 469system.cpu.idleCycles 14426 # Total number of cycles that the CPU has spent unscheduled due to idling | 503system.cpu.idleCycles 19450 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 470system.cpu.committedInsts 4591 # Number of Instructions Simulated 471system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 472system.cpu.committedInsts_total 4591 # Number of Instructions Simulated | 504system.cpu.committedInsts 4591 # Number of Instructions Simulated 505system.cpu.committedOps 5729 # Number of Ops (including micro ops) Simulated 506system.cpu.committedInsts_total 4591 # Number of Instructions Simulated |
| 473system.cpu.cpi 5.971030 # CPI: Cycles Per Instruction 474system.cpu.cpi_total 5.971030 # CPI: Total CPI of All Threads 475system.cpu.ipc 0.167475 # IPC: Instructions Per Cycle 476system.cpu.ipc_total 0.167475 # IPC: Total IPC of All Threads 477system.cpu.int_regfile_reads 39296 # number of integer regfile reads 478system.cpu.int_regfile_writes 8001 # number of integer regfile writes | 507system.cpu.cpi 7.138968 # CPI: Cycles Per Instruction 508system.cpu.cpi_total 7.138968 # CPI: Total CPI of All Threads 509system.cpu.ipc 0.140076 # IPC: Instructions Per Cycle 510system.cpu.ipc_total 0.140076 # IPC: Total IPC of All Threads 511system.cpu.int_regfile_reads 39187 # number of integer regfile reads 512system.cpu.int_regfile_writes 7985 # number of integer regfile writes |
| 479system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 513system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 480system.cpu.misc_regfile_reads 2981 # number of misc regfile reads | 514system.cpu.misc_regfile_reads 2976 # number of misc regfile reads |
| 481system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 515system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 482system.cpu.icache.replacements 3 # number of replacements 483system.cpu.icache.tagsinuse 146.948464 # Cycle average of tags in use 484system.cpu.icache.total_refs 1590 # Total number of references to valid blocks. | 516system.cpu.toL2Bus.throughput 1706718740 # Throughput (bytes/s) 517system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution 518system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 519system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 520system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 521system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 582 # Packet count per connected master and slave (bytes) 522system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 293 # Packet count per connected master and slave (bytes) 523system.cpu.toL2Bus.pkt_count 875 # Packet count per connected master and slave (bytes) 524system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 18624 # Cumulative packet size per connected master and slave (bytes) 525system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9344 # Cumulative packet size per connected master and slave (bytes) 526system.cpu.toL2Bus.tot_pkt_size 27968 # Cumulative packet size per connected master and slave (bytes) 527system.cpu.toL2Bus.data_through_bus 27968 # Total data (bytes) 528system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 529system.cpu.toL2Bus.reqLayer0.occupancy 219000 # Layer occupancy (ticks) 530system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 531system.cpu.toL2Bus.respLayer0.occupancy 436500 # Layer occupancy (ticks) 532system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 533system.cpu.toL2Bus.respLayer1.occupancy 221495 # Layer occupancy (ticks) 534system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 535system.cpu.icache.replacements 4 # number of replacements 536system.cpu.icache.tagsinuse 145.578272 # Cycle average of tags in use 537system.cpu.icache.total_refs 1578 # Total number of references to valid blocks. |
| 485system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. | 538system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. |
| 486system.cpu.icache.avg_refs 5.463918 # Average number of references to valid blocks. | 539system.cpu.icache.avg_refs 5.422680 # Average number of references to valid blocks. |
| 487system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 540system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 488system.cpu.icache.occ_blocks::cpu.inst 146.948464 # Average occupied blocks per requestor 489system.cpu.icache.occ_percent::cpu.inst 0.071752 # Average percentage of cache occupancy 490system.cpu.icache.occ_percent::total 0.071752 # Average percentage of cache occupancy 491system.cpu.icache.ReadReq_hits::cpu.inst 1590 # number of ReadReq hits 492system.cpu.icache.ReadReq_hits::total 1590 # number of ReadReq hits 493system.cpu.icache.demand_hits::cpu.inst 1590 # number of demand (read+write) hits 494system.cpu.icache.demand_hits::total 1590 # number of demand (read+write) hits 495system.cpu.icache.overall_hits::cpu.inst 1590 # number of overall hits 496system.cpu.icache.overall_hits::total 1590 # number of overall hits 497system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 498system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 499system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 500system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 501system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 502system.cpu.icache.overall_misses::total 360 # number of overall misses 503system.cpu.icache.ReadReq_miss_latency::cpu.inst 17732500 # number of ReadReq miss cycles 504system.cpu.icache.ReadReq_miss_latency::total 17732500 # number of ReadReq miss cycles 505system.cpu.icache.demand_miss_latency::cpu.inst 17732500 # number of demand (read+write) miss cycles 506system.cpu.icache.demand_miss_latency::total 17732500 # number of demand (read+write) miss cycles 507system.cpu.icache.overall_miss_latency::cpu.inst 17732500 # number of overall miss cycles 508system.cpu.icache.overall_miss_latency::total 17732500 # number of overall miss cycles 509system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) 510system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) 511system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses 512system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses 513system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses 514system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses 515system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.184615 # miss rate for ReadReq accesses 516system.cpu.icache.ReadReq_miss_rate::total 0.184615 # miss rate for ReadReq accesses 517system.cpu.icache.demand_miss_rate::cpu.inst 0.184615 # miss rate for demand accesses 518system.cpu.icache.demand_miss_rate::total 0.184615 # miss rate for demand accesses 519system.cpu.icache.overall_miss_rate::cpu.inst 0.184615 # miss rate for overall accesses 520system.cpu.icache.overall_miss_rate::total 0.184615 # miss rate for overall accesses 521system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49256.944444 # average ReadReq miss latency 522system.cpu.icache.ReadReq_avg_miss_latency::total 49256.944444 # average ReadReq miss latency 523system.cpu.icache.demand_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency 524system.cpu.icache.demand_avg_miss_latency::total 49256.944444 # average overall miss latency 525system.cpu.icache.overall_avg_miss_latency::cpu.inst 49256.944444 # average overall miss latency 526system.cpu.icache.overall_avg_miss_latency::total 49256.944444 # average overall miss latency 527system.cpu.icache.blocked_cycles::no_mshrs 126 # number of cycles access was blocked | 541system.cpu.icache.occ_blocks::cpu.inst 145.578272 # Average occupied blocks per requestor 542system.cpu.icache.occ_percent::cpu.inst 0.071083 # Average percentage of cache occupancy 543system.cpu.icache.occ_percent::total 0.071083 # Average percentage of cache occupancy 544system.cpu.icache.ReadReq_hits::cpu.inst 1578 # number of ReadReq hits 545system.cpu.icache.ReadReq_hits::total 1578 # number of ReadReq hits 546system.cpu.icache.demand_hits::cpu.inst 1578 # number of demand (read+write) hits 547system.cpu.icache.demand_hits::total 1578 # number of demand (read+write) hits 548system.cpu.icache.overall_hits::cpu.inst 1578 # number of overall hits 549system.cpu.icache.overall_hits::total 1578 # number of overall hits 550system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 551system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 552system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 553system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 554system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 555system.cpu.icache.overall_misses::total 364 # number of overall misses 556system.cpu.icache.ReadReq_miss_latency::cpu.inst 22955000 # number of ReadReq miss cycles 557system.cpu.icache.ReadReq_miss_latency::total 22955000 # number of ReadReq miss cycles 558system.cpu.icache.demand_miss_latency::cpu.inst 22955000 # number of demand (read+write) miss cycles 559system.cpu.icache.demand_miss_latency::total 22955000 # number of demand (read+write) miss cycles 560system.cpu.icache.overall_miss_latency::cpu.inst 22955000 # number of overall miss cycles 561system.cpu.icache.overall_miss_latency::total 22955000 # number of overall miss cycles 562system.cpu.icache.ReadReq_accesses::cpu.inst 1942 # number of ReadReq accesses(hits+misses) 563system.cpu.icache.ReadReq_accesses::total 1942 # number of ReadReq accesses(hits+misses) 564system.cpu.icache.demand_accesses::cpu.inst 1942 # number of demand (read+write) accesses 565system.cpu.icache.demand_accesses::total 1942 # number of demand (read+write) accesses 566system.cpu.icache.overall_accesses::cpu.inst 1942 # number of overall (read+write) accesses 567system.cpu.icache.overall_accesses::total 1942 # number of overall (read+write) accesses 568system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187436 # miss rate for ReadReq accesses 569system.cpu.icache.ReadReq_miss_rate::total 0.187436 # miss rate for ReadReq accesses 570system.cpu.icache.demand_miss_rate::cpu.inst 0.187436 # miss rate for demand accesses 571system.cpu.icache.demand_miss_rate::total 0.187436 # miss rate for demand accesses 572system.cpu.icache.overall_miss_rate::cpu.inst 0.187436 # miss rate for overall accesses 573system.cpu.icache.overall_miss_rate::total 0.187436 # miss rate for overall accesses 574system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63063.186813 # average ReadReq miss latency 575system.cpu.icache.ReadReq_avg_miss_latency::total 63063.186813 # average ReadReq miss latency 576system.cpu.icache.demand_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency 577system.cpu.icache.demand_avg_miss_latency::total 63063.186813 # average overall miss latency 578system.cpu.icache.overall_avg_miss_latency::cpu.inst 63063.186813 # average overall miss latency 579system.cpu.icache.overall_avg_miss_latency::total 63063.186813 # average overall miss latency 580system.cpu.icache.blocked_cycles::no_mshrs 121 # number of cycles access was blocked |
| 528system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 581system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 529system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked | 582system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked |
| 530system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 583system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 531system.cpu.icache.avg_blocked_cycles::no_mshrs 63 # average number of cycles each access was blocked | 584system.cpu.icache.avg_blocked_cycles::no_mshrs 40.333333 # average number of cycles each access was blocked |
| 532system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 533system.cpu.icache.fast_writes 0 # number of fast writes performed 534system.cpu.icache.cache_copies 0 # number of cache copies performed | 585system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 586system.cpu.icache.fast_writes 0 # number of fast writes performed 587system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 535system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 536system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 537system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 538system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 539system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 540system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits | 588system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits 589system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits 590system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits 591system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits 592system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits 593system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits |
| 541system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 542system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 543system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 544system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 545system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 546system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses | 594system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses 595system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses 596system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses 597system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses 598system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses 599system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses |
| 547system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14598500 # number of ReadReq MSHR miss cycles 548system.cpu.icache.ReadReq_mshr_miss_latency::total 14598500 # number of ReadReq MSHR miss cycles 549system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14598500 # number of demand (read+write) MSHR miss cycles 550system.cpu.icache.demand_mshr_miss_latency::total 14598500 # number of demand (read+write) MSHR miss cycles 551system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14598500 # number of overall MSHR miss cycles 552system.cpu.icache.overall_mshr_miss_latency::total 14598500 # number of overall MSHR miss cycles 553system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for ReadReq accesses 554system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149231 # mshr miss rate for ReadReq accesses 555system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for demand accesses 556system.cpu.icache.demand_mshr_miss_rate::total 0.149231 # mshr miss rate for demand accesses 557system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149231 # mshr miss rate for overall accesses 558system.cpu.icache.overall_mshr_miss_rate::total 0.149231 # mshr miss rate for overall accesses 559system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50166.666667 # average ReadReq mshr miss latency 560system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50166.666667 # average ReadReq mshr miss latency 561system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency 562system.cpu.icache.demand_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency 563system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50166.666667 # average overall mshr miss latency 564system.cpu.icache.overall_avg_mshr_miss_latency::total 50166.666667 # average overall mshr miss latency | 600system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18642000 # number of ReadReq MSHR miss cycles 601system.cpu.icache.ReadReq_mshr_miss_latency::total 18642000 # number of ReadReq MSHR miss cycles 602system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18642000 # number of demand (read+write) MSHR miss cycles 603system.cpu.icache.demand_mshr_miss_latency::total 18642000 # number of demand (read+write) MSHR miss cycles 604system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18642000 # number of overall MSHR miss cycles 605system.cpu.icache.overall_mshr_miss_latency::total 18642000 # number of overall MSHR miss cycles 606system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for ReadReq accesses 607system.cpu.icache.ReadReq_mshr_miss_rate::total 0.149846 # mshr miss rate for ReadReq accesses 608system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for demand accesses 609system.cpu.icache.demand_mshr_miss_rate::total 0.149846 # mshr miss rate for demand accesses 610system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.149846 # mshr miss rate for overall accesses 611system.cpu.icache.overall_mshr_miss_rate::total 0.149846 # mshr miss rate for overall accesses 612system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 64061.855670 # average ReadReq mshr miss latency 613system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 64061.855670 # average ReadReq mshr miss latency 614system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency 615system.cpu.icache.demand_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency 616system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 64061.855670 # average overall mshr miss latency 617system.cpu.icache.overall_avg_mshr_miss_latency::total 64061.855670 # average overall mshr miss latency |
| 565system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 566system.cpu.l2cache.replacements 0 # number of replacements | 618system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 619system.cpu.l2cache.replacements 0 # number of replacements |
| 567system.cpu.l2cache.tagsinuse 185.107247 # Cycle average of tags in use 568system.cpu.l2cache.total_refs 39 # Total number of references to valid blocks. 569system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 570system.cpu.l2cache.avg_refs 0.110482 # Average number of references to valid blocks. | 620system.cpu.l2cache.tagsinuse 183.439490 # Cycle average of tags in use 621system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 622system.cpu.l2cache.sampled_refs 352 # Sample count of references to valid blocks. 623system.cpu.l2cache.avg_refs 0.113636 # Average number of references to valid blocks. |
| 571system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 624system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 572system.cpu.l2cache.occ_blocks::cpu.inst 138.394475 # Average occupied blocks per requestor 573system.cpu.l2cache.occ_blocks::cpu.data 46.712772 # Average occupied blocks per requestor 574system.cpu.l2cache.occ_percent::cpu.inst 0.004223 # Average percentage of cache occupancy 575system.cpu.l2cache.occ_percent::cpu.data 0.001426 # Average percentage of cache occupancy 576system.cpu.l2cache.occ_percent::total 0.005649 # Average percentage of cache occupancy 577system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits | 625system.cpu.l2cache.occ_blocks::cpu.inst 137.046036 # Average occupied blocks per requestor 626system.cpu.l2cache.occ_blocks::cpu.data 46.393454 # Average occupied blocks per requestor 627system.cpu.l2cache.occ_percent::cpu.inst 0.004182 # Average percentage of cache occupancy 628system.cpu.l2cache.occ_percent::cpu.data 0.001416 # Average percentage of cache occupancy 629system.cpu.l2cache.occ_percent::total 0.005598 # Average percentage of cache occupancy 630system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits |
| 578system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits | 631system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits |
| 579system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 580system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits | 632system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 633system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits |
| 581system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits | 634system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits |
| 582system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 583system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits | 635system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 636system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits |
| 584system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits | 637system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits |
| 585system.cpu.l2cache.overall_hits::total 39 # number of overall hits 586system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses | 638system.cpu.l2cache.overall_hits::total 40 # number of overall hits 639system.cpu.l2cache.ReadReq_misses::cpu.inst 271 # number of ReadReq misses |
| 587system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses | 640system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses |
| 588system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses | 641system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses |
| 589system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 590system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses | 642system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 643system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses |
| 591system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses | 644system.cpu.l2cache.demand_misses::cpu.inst 271 # number of demand (read+write) misses |
| 592system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses | 645system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses |
| 593system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 594system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses | 646system.cpu.l2cache.demand_misses::total 398 # number of demand (read+write) misses 647system.cpu.l2cache.overall_misses::cpu.inst 271 # number of overall misses |
| 595system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses | 648system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses |
| 596system.cpu.l2cache.overall_misses::total 399 # number of overall misses 597system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14110000 # number of ReadReq miss cycles 598system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4968000 # number of ReadReq miss cycles 599system.cpu.l2cache.ReadReq_miss_latency::total 19078000 # number of ReadReq miss cycles 600system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2402500 # number of ReadExReq miss cycles 601system.cpu.l2cache.ReadExReq_miss_latency::total 2402500 # number of ReadExReq miss cycles 602system.cpu.l2cache.demand_miss_latency::cpu.inst 14110000 # number of demand (read+write) miss cycles 603system.cpu.l2cache.demand_miss_latency::cpu.data 7370500 # number of demand (read+write) miss cycles 604system.cpu.l2cache.demand_miss_latency::total 21480500 # number of demand (read+write) miss cycles 605system.cpu.l2cache.overall_miss_latency::cpu.inst 14110000 # number of overall miss cycles 606system.cpu.l2cache.overall_miss_latency::cpu.data 7370500 # number of overall miss cycles 607system.cpu.l2cache.overall_miss_latency::total 21480500 # number of overall miss cycles | 649system.cpu.l2cache.overall_misses::total 398 # number of overall misses 650system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18145000 # number of ReadReq miss cycles 651system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6188500 # number of ReadReq miss cycles 652system.cpu.l2cache.ReadReq_miss_latency::total 24333500 # number of ReadReq miss cycles 653system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2992500 # number of ReadExReq miss cycles 654system.cpu.l2cache.ReadExReq_miss_latency::total 2992500 # number of ReadExReq miss cycles 655system.cpu.l2cache.demand_miss_latency::cpu.inst 18145000 # number of demand (read+write) miss cycles 656system.cpu.l2cache.demand_miss_latency::cpu.data 9181000 # number of demand (read+write) miss cycles 657system.cpu.l2cache.demand_miss_latency::total 27326000 # number of demand (read+write) miss cycles 658system.cpu.l2cache.overall_miss_latency::cpu.inst 18145000 # number of overall miss cycles 659system.cpu.l2cache.overall_miss_latency::cpu.data 9181000 # number of overall miss cycles 660system.cpu.l2cache.overall_miss_latency::total 27326000 # number of overall miss cycles |
| 608system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 609system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 610system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 611system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 612system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 613system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 614system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 615system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 616system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 617system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 618system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses | 661system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) 662system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 663system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) 664system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 665system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 666system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses 667system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 668system.cpu.l2cache.demand_accesses::total 438 # number of demand (read+write) accesses 669system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses 670system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 671system.cpu.l2cache.overall_accesses::total 438 # number of overall (read+write) accesses |
| 619system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.934708 # miss rate for ReadReq accesses | 672system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931271 # miss rate for ReadReq accesses |
| 620system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses | 673system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses |
| 621system.cpu.l2cache.ReadReq_miss_rate::total 0.901763 # miss rate for ReadReq accesses | 674system.cpu.l2cache.ReadReq_miss_rate::total 0.899244 # miss rate for ReadReq accesses |
| 622system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 623system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses | 675system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 676system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| 624system.cpu.l2cache.demand_miss_rate::cpu.inst 0.934708 # miss rate for demand accesses | 677system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931271 # miss rate for demand accesses |
| 625system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses | 678system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses |
| 626system.cpu.l2cache.demand_miss_rate::total 0.910959 # miss rate for demand accesses 627system.cpu.l2cache.overall_miss_rate::cpu.inst 0.934708 # miss rate for overall accesses | 679system.cpu.l2cache.demand_miss_rate::total 0.908676 # miss rate for demand accesses 680system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931271 # miss rate for overall accesses |
| 628system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses | 681system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses |
| 629system.cpu.l2cache.overall_miss_rate::total 0.910959 # miss rate for overall accesses 630system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51875 # average ReadReq miss latency 631system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 57767.441860 # average ReadReq miss latency 632system.cpu.l2cache.ReadReq_avg_miss_latency::total 53290.502793 # average ReadReq miss latency 633system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58597.560976 # average ReadExReq miss latency 634system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58597.560976 # average ReadExReq miss latency 635system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51875 # average overall miss latency 636system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency 637system.cpu.l2cache.demand_avg_miss_latency::total 53835.839599 # average overall miss latency 638system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51875 # average overall miss latency 639system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58035.433071 # average overall miss latency 640system.cpu.l2cache.overall_avg_miss_latency::total 53835.839599 # average overall miss latency | 682system.cpu.l2cache.overall_miss_rate::total 0.908676 # miss rate for overall accesses 683system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66955.719557 # average ReadReq miss latency 684system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71959.302326 # average ReadReq miss latency 685system.cpu.l2cache.ReadReq_avg_miss_latency::total 68161.064426 # average ReadReq miss latency 686system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72987.804878 # average ReadExReq miss latency 687system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72987.804878 # average ReadExReq miss latency 688system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency 689system.cpu.l2cache.demand_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency 690system.cpu.l2cache.demand_avg_miss_latency::total 68658.291457 # average overall miss latency 691system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66955.719557 # average overall miss latency 692system.cpu.l2cache.overall_avg_miss_latency::cpu.data 72291.338583 # average overall miss latency 693system.cpu.l2cache.overall_avg_miss_latency::total 68658.291457 # average overall miss latency |
| 641system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 642system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 643system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 644system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 645system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 646system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 647system.cpu.l2cache.fast_writes 0 # number of fast writes performed 648system.cpu.l2cache.cache_copies 0 # number of cache copies performed 649system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 650system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 651system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 652system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 653system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 654system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits | 694system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 695system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 696system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 697system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 698system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 699system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 700system.cpu.l2cache.fast_writes 0 # number of fast writes performed 701system.cpu.l2cache.cache_copies 0 # number of cache copies performed 702system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 703system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 704system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 705system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 706system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 707system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits |
| 655system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses | 708system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 271 # number of ReadReq MSHR misses |
| 656system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses | 709system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses |
| 657system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses | 710system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses |
| 658system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 659system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses | 711system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 712system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses |
| 660system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses | 713system.cpu.l2cache.demand_mshr_misses::cpu.inst 271 # number of demand (read+write) MSHR misses |
| 661system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses | 714system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses |
| 662system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 663system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses | 715system.cpu.l2cache.demand_mshr_misses::total 393 # number of demand (read+write) MSHR misses 716system.cpu.l2cache.overall_mshr_misses::cpu.inst 271 # number of overall MSHR misses |
| 664system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses | 717system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses |
| 665system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 666system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10735459 # number of ReadReq MSHR miss cycles 667system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3756284 # number of ReadReq MSHR miss cycles 668system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14491743 # number of ReadReq MSHR miss cycles 669system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1896771 # number of ReadExReq MSHR miss cycles 670system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1896771 # number of ReadExReq MSHR miss cycles 671system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10735459 # number of demand (read+write) MSHR miss cycles 672system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5653055 # number of demand (read+write) MSHR miss cycles 673system.cpu.l2cache.demand_mshr_miss_latency::total 16388514 # number of demand (read+write) MSHR miss cycles 674system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10735459 # number of overall MSHR miss cycles 675system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5653055 # number of overall MSHR miss cycles 676system.cpu.l2cache.overall_mshr_miss_latency::total 16388514 # number of overall MSHR miss cycles 677system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for ReadReq accesses | 718system.cpu.l2cache.overall_mshr_misses::total 393 # number of overall MSHR misses 719system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14791750 # number of ReadReq MSHR miss cycles 720system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4905500 # number of ReadReq MSHR miss cycles 721system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19697250 # number of ReadReq MSHR miss cycles 722system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2490250 # number of ReadExReq MSHR miss cycles 723system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2490250 # number of ReadExReq MSHR miss cycles 724system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14791750 # number of demand (read+write) MSHR miss cycles 725system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7395750 # number of demand (read+write) MSHR miss cycles 726system.cpu.l2cache.demand_mshr_miss_latency::total 22187500 # number of demand (read+write) MSHR miss cycles 727system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14791750 # number of overall MSHR miss cycles 728system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7395750 # number of overall MSHR miss cycles 729system.cpu.l2cache.overall_mshr_miss_latency::total 22187500 # number of overall MSHR miss cycles 730system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for ReadReq accesses |
| 678system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses | 731system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses |
| 679system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889169 # mshr miss rate for ReadReq accesses | 732system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886650 # mshr miss rate for ReadReq accesses |
| 680system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 681system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses | 733system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 734system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| 682system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for demand accesses | 735system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for demand accesses |
| 683system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses | 736system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses |
| 684system.cpu.l2cache.demand_mshr_miss_rate::total 0.899543 # mshr miss rate for demand accesses 685system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.934708 # mshr miss rate for overall accesses | 737system.cpu.l2cache.demand_mshr_miss_rate::total 0.897260 # mshr miss rate for demand accesses 738system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931271 # mshr miss rate for overall accesses |
| 686system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses | 739system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses |
| 687system.cpu.l2cache.overall_mshr_miss_rate::total 0.899543 # mshr miss rate for overall accesses 688system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39468.599265 # average ReadReq mshr miss latency 689system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46373.876543 # average ReadReq mshr miss latency 690system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41053.096317 # average ReadReq mshr miss latency 691system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46262.707317 # average ReadExReq mshr miss latency 692system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46262.707317 # average ReadExReq mshr miss latency 693system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency 694system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency 695system.cpu.l2cache.demand_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency 696system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39468.599265 # average overall mshr miss latency 697system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 46336.516393 # average overall mshr miss latency 698system.cpu.l2cache.overall_avg_mshr_miss_latency::total 41595.213198 # average overall mshr miss latency | 740system.cpu.l2cache.overall_mshr_miss_rate::total 0.897260 # mshr miss rate for overall accesses 741system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54582.103321 # average ReadReq mshr miss latency 742system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60561.728395 # average ReadReq mshr miss latency 743system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55958.096591 # average ReadReq mshr miss latency 744system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60737.804878 # average ReadExReq mshr miss latency 745system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60737.804878 # average ReadExReq mshr miss latency 746system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency 747system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency 748system.cpu.l2cache.demand_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency 749system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54582.103321 # average overall mshr miss latency 750system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60620.901639 # average overall mshr miss latency 751system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56456.743003 # average overall mshr miss latency |
| 699system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 700system.cpu.dcache.replacements 0 # number of replacements | 752system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 753system.cpu.dcache.replacements 0 # number of replacements |
| 701system.cpu.dcache.tagsinuse 86.521929 # Cycle average of tags in use 702system.cpu.dcache.total_refs 2391 # Total number of references to valid blocks. | 754system.cpu.dcache.tagsinuse 85.937637 # Cycle average of tags in use 755system.cpu.dcache.total_refs 2388 # Total number of references to valid blocks. |
| 703system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. | 756system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. |
| 704system.cpu.dcache.avg_refs 16.376712 # Average number of references to valid blocks. | 757system.cpu.dcache.avg_refs 16.356164 # Average number of references to valid blocks. |
| 705system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 758system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 706system.cpu.dcache.occ_blocks::cpu.data 86.521929 # Average occupied blocks per requestor 707system.cpu.dcache.occ_percent::cpu.data 0.021124 # Average percentage of cache occupancy 708system.cpu.dcache.occ_percent::total 0.021124 # Average percentage of cache occupancy 709system.cpu.dcache.ReadReq_hits::cpu.data 1763 # number of ReadReq hits 710system.cpu.dcache.ReadReq_hits::total 1763 # number of ReadReq hits | 759system.cpu.dcache.occ_blocks::cpu.data 85.937637 # Average occupied blocks per requestor 760system.cpu.dcache.occ_percent::cpu.data 0.020981 # Average percentage of cache occupancy 761system.cpu.dcache.occ_percent::total 0.020981 # Average percentage of cache occupancy 762system.cpu.dcache.ReadReq_hits::cpu.data 1760 # number of ReadReq hits 763system.cpu.dcache.ReadReq_hits::total 1760 # number of ReadReq hits |
| 711system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 712system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 713system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 714system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 715system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 716system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 764system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 765system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 766system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 767system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits 768system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 769system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 717system.cpu.dcache.demand_hits::cpu.data 2369 # number of demand (read+write) hits 718system.cpu.dcache.demand_hits::total 2369 # number of demand (read+write) hits 719system.cpu.dcache.overall_hits::cpu.data 2369 # number of overall hits 720system.cpu.dcache.overall_hits::total 2369 # number of overall hits 721system.cpu.dcache.ReadReq_misses::cpu.data 193 # number of ReadReq misses 722system.cpu.dcache.ReadReq_misses::total 193 # number of ReadReq misses | 770system.cpu.dcache.demand_hits::cpu.data 2366 # number of demand (read+write) hits 771system.cpu.dcache.demand_hits::total 2366 # number of demand (read+write) hits 772system.cpu.dcache.overall_hits::cpu.data 2366 # number of overall hits 773system.cpu.dcache.overall_hits::total 2366 # number of overall hits 774system.cpu.dcache.ReadReq_misses::cpu.data 190 # number of ReadReq misses 775system.cpu.dcache.ReadReq_misses::total 190 # number of ReadReq misses |
| 723system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 724system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 725system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 726system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 776system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 777system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 778system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 779system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 727system.cpu.dcache.demand_misses::cpu.data 500 # number of demand (read+write) misses 728system.cpu.dcache.demand_misses::total 500 # number of demand (read+write) misses 729system.cpu.dcache.overall_misses::cpu.data 500 # number of overall misses 730system.cpu.dcache.overall_misses::total 500 # number of overall misses 731system.cpu.dcache.ReadReq_miss_latency::cpu.data 8675500 # number of ReadReq miss cycles 732system.cpu.dcache.ReadReq_miss_latency::total 8675500 # number of ReadReq miss cycles 733system.cpu.dcache.WriteReq_miss_latency::cpu.data 14874500 # number of WriteReq miss cycles 734system.cpu.dcache.WriteReq_miss_latency::total 14874500 # number of WriteReq miss cycles 735system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 736system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles 737system.cpu.dcache.demand_miss_latency::cpu.data 23550000 # number of demand (read+write) miss cycles 738system.cpu.dcache.demand_miss_latency::total 23550000 # number of demand (read+write) miss cycles 739system.cpu.dcache.overall_miss_latency::cpu.data 23550000 # number of overall miss cycles 740system.cpu.dcache.overall_miss_latency::total 23550000 # number of overall miss cycles 741system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 742system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) | 780system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses 781system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses 782system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses 783system.cpu.dcache.overall_misses::total 497 # number of overall misses 784system.cpu.dcache.ReadReq_miss_latency::cpu.data 10638500 # number of ReadReq miss cycles 785system.cpu.dcache.ReadReq_miss_latency::total 10638500 # number of ReadReq miss cycles 786system.cpu.dcache.WriteReq_miss_latency::cpu.data 19663000 # number of WriteReq miss cycles 787system.cpu.dcache.WriteReq_miss_latency::total 19663000 # number of WriteReq miss cycles 788system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127500 # number of LoadLockedReq miss cycles 789system.cpu.dcache.LoadLockedReq_miss_latency::total 127500 # number of LoadLockedReq miss cycles 790system.cpu.dcache.demand_miss_latency::cpu.data 30301500 # number of demand (read+write) miss cycles 791system.cpu.dcache.demand_miss_latency::total 30301500 # number of demand (read+write) miss cycles 792system.cpu.dcache.overall_miss_latency::cpu.data 30301500 # number of overall miss cycles 793system.cpu.dcache.overall_miss_latency::total 30301500 # number of overall miss cycles 794system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) 795system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) |
| 743system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 744system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 745system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 746system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 747system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 748system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 796system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 797system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 798system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 799system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) 800system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 801system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 749system.cpu.dcache.demand_accesses::cpu.data 2869 # number of demand (read+write) accesses 750system.cpu.dcache.demand_accesses::total 2869 # number of demand (read+write) accesses 751system.cpu.dcache.overall_accesses::cpu.data 2869 # number of overall (read+write) accesses 752system.cpu.dcache.overall_accesses::total 2869 # number of overall (read+write) accesses 753system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098671 # miss rate for ReadReq accesses 754system.cpu.dcache.ReadReq_miss_rate::total 0.098671 # miss rate for ReadReq accesses | 802system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses 803system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses 804system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses 805system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses 806system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097436 # miss rate for ReadReq accesses 807system.cpu.dcache.ReadReq_miss_rate::total 0.097436 # miss rate for ReadReq accesses |
| 755system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 756system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 757system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 758system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses | 808system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 809system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 810system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 811system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses |
| 759system.cpu.dcache.demand_miss_rate::cpu.data 0.174277 # miss rate for demand accesses 760system.cpu.dcache.demand_miss_rate::total 0.174277 # miss rate for demand accesses 761system.cpu.dcache.overall_miss_rate::cpu.data 0.174277 # miss rate for overall accesses 762system.cpu.dcache.overall_miss_rate::total 0.174277 # miss rate for overall accesses 763system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44950.777202 # average ReadReq miss latency 764system.cpu.dcache.ReadReq_avg_miss_latency::total 44950.777202 # average ReadReq miss latency 765system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48451.140065 # average WriteReq miss latency 766system.cpu.dcache.WriteReq_avg_miss_latency::total 48451.140065 # average WriteReq miss latency 767system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 768system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency 769system.cpu.dcache.demand_avg_miss_latency::cpu.data 47100 # average overall miss latency 770system.cpu.dcache.demand_avg_miss_latency::total 47100 # average overall miss latency 771system.cpu.dcache.overall_avg_miss_latency::cpu.data 47100 # average overall miss latency 772system.cpu.dcache.overall_avg_miss_latency::total 47100 # average overall miss latency 773system.cpu.dcache.blocked_cycles::no_mshrs 107 # number of cycles access was blocked | 812system.cpu.dcache.demand_miss_rate::cpu.data 0.173594 # miss rate for demand accesses 813system.cpu.dcache.demand_miss_rate::total 0.173594 # miss rate for demand accesses 814system.cpu.dcache.overall_miss_rate::cpu.data 0.173594 # miss rate for overall accesses 815system.cpu.dcache.overall_miss_rate::total 0.173594 # miss rate for overall accesses 816system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55992.105263 # average ReadReq miss latency 817system.cpu.dcache.ReadReq_avg_miss_latency::total 55992.105263 # average ReadReq miss latency 818system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64048.859935 # average WriteReq miss latency 819system.cpu.dcache.WriteReq_avg_miss_latency::total 64048.859935 # average WriteReq miss latency 820system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63750 # average LoadLockedReq miss latency 821system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63750 # average LoadLockedReq miss latency 822system.cpu.dcache.demand_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency 823system.cpu.dcache.demand_avg_miss_latency::total 60968.812877 # average overall miss latency 824system.cpu.dcache.overall_avg_miss_latency::cpu.data 60968.812877 # average overall miss latency 825system.cpu.dcache.overall_avg_miss_latency::total 60968.812877 # average overall miss latency 826system.cpu.dcache.blocked_cycles::no_mshrs 103 # number of cycles access was blocked |
| 774system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 775system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 776system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 827system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 828system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 829system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 777system.cpu.dcache.avg_blocked_cycles::no_mshrs 35.666667 # average number of cycles each access was blocked | 830system.cpu.dcache.avg_blocked_cycles::no_mshrs 34.333333 # average number of cycles each access was blocked |
| 778system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 779system.cpu.dcache.fast_writes 0 # number of fast writes performed 780system.cpu.dcache.cache_copies 0 # number of cache copies performed | 831system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 832system.cpu.dcache.fast_writes 0 # number of fast writes performed 833system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 781system.cpu.dcache.ReadReq_mshr_hits::cpu.data 87 # number of ReadReq MSHR hits 782system.cpu.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits | 834system.cpu.dcache.ReadReq_mshr_hits::cpu.data 84 # number of ReadReq MSHR hits 835system.cpu.dcache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits |
| 783system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 784system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 785system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 786system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 836system.cpu.dcache.WriteReq_mshr_hits::cpu.data 266 # number of WriteReq MSHR hits 837system.cpu.dcache.WriteReq_mshr_hits::total 266 # number of WriteReq MSHR hits 838system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 839system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 787system.cpu.dcache.demand_mshr_hits::cpu.data 353 # number of demand (read+write) MSHR hits 788system.cpu.dcache.demand_mshr_hits::total 353 # number of demand (read+write) MSHR hits 789system.cpu.dcache.overall_mshr_hits::cpu.data 353 # number of overall MSHR hits 790system.cpu.dcache.overall_mshr_hits::total 353 # number of overall MSHR hits | 840system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 841system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 842system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 843system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits |
| 791system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 792system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 793system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 794system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 795system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 796system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 797system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 798system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 844system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 845system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 846system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 847system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 848system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 849system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 850system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 851system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 799system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5218000 # number of ReadReq MSHR miss cycles 800system.cpu.dcache.ReadReq_mshr_miss_latency::total 5218000 # number of ReadReq MSHR miss cycles 801system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2444500 # number of WriteReq MSHR miss cycles 802system.cpu.dcache.WriteReq_mshr_miss_latency::total 2444500 # number of WriteReq MSHR miss cycles 803system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7662500 # number of demand (read+write) MSHR miss cycles 804system.cpu.dcache.demand_mshr_miss_latency::total 7662500 # number of demand (read+write) MSHR miss cycles 805system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7662500 # number of overall MSHR miss cycles 806system.cpu.dcache.overall_mshr_miss_latency::total 7662500 # number of overall MSHR miss cycles 807system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 808system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses | 852system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6438005 # number of ReadReq MSHR miss cycles 853system.cpu.dcache.ReadReq_mshr_miss_latency::total 6438005 # number of ReadReq MSHR miss cycles 854system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3034500 # number of WriteReq MSHR miss cycles 855system.cpu.dcache.WriteReq_mshr_miss_latency::total 3034500 # number of WriteReq MSHR miss cycles 856system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9472505 # number of demand (read+write) MSHR miss cycles 857system.cpu.dcache.demand_mshr_miss_latency::total 9472505 # number of demand (read+write) MSHR miss cycles 858system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9472505 # number of overall MSHR miss cycles 859system.cpu.dcache.overall_mshr_miss_latency::total 9472505 # number of overall MSHR miss cycles 860system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054359 # mshr miss rate for ReadReq accesses 861system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054359 # mshr miss rate for ReadReq accesses |
| 809system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 810system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses | 862system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 863system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses |
| 811system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 812system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 813system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 814system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses 815system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49226.415094 # average ReadReq mshr miss latency 816system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49226.415094 # average ReadReq mshr miss latency 817system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59621.951220 # average WriteReq mshr miss latency 818system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59621.951220 # average WriteReq mshr miss latency 819system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency 820system.cpu.dcache.demand_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency 821system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52125.850340 # average overall mshr miss latency 822system.cpu.dcache.overall_avg_mshr_miss_latency::total 52125.850340 # average overall mshr miss latency | 864system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for demand accesses 865system.cpu.dcache.demand_mshr_miss_rate::total 0.051345 # mshr miss rate for demand accesses 866system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051345 # mshr miss rate for overall accesses 867system.cpu.dcache.overall_mshr_miss_rate::total 0.051345 # mshr miss rate for overall accesses 868system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60735.896226 # average ReadReq mshr miss latency 869system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60735.896226 # average ReadReq mshr miss latency 870system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74012.195122 # average WriteReq mshr miss latency 871system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74012.195122 # average WriteReq mshr miss latency 872system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency 873system.cpu.dcache.demand_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency 874system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 64438.809524 # average overall mshr miss latency 875system.cpu.dcache.overall_avg_mshr_miss_latency::total 64438.809524 # average overall mshr miss latency |
| 823system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 824 825---------- End Simulation Statistics ---------- | 876system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 877 878---------- End Simulation Statistics ---------- |