| stats.txt (9378:36ed6d4654bb) | stats.txt (9449:56610ab73040) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated |
| 4sim_ticks 13371000 # Number of ticks simulated 5final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 13372000 # Number of ticks simulated 5final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 36978 # Simulator instruction rate (inst/s) 8host_op_rate 46127 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 107546339 # Simulator tick rate (ticks/s) 10host_mem_usage 272728 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host | 7host_inst_rate 20879 # Simulator instruction rate (inst/s) 8host_op_rate 26045 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 60729168 # Simulator tick rate (ticks/s) 10host_mem_usage 230484 # Number of bytes of host memory used 11host_seconds 0.22 # Real time elapsed on the host |
| 12sim_insts 4596 # Number of instructions simulated 13sim_ops 5734 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory | 12sim_insts 4596 # Number of instructions simulated 13sim_ops 5734 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 16system.physmem.bytes_read::total 25216 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 394 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 27 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 30system.physmem.readReqs 394 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 25216 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 25216 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q --- 27 unchanged lines hidden (view full) --- 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 13312500 # Total gap between requests | 73system.physmem.totGap 13314500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 85 unchanged lines hidden (view full) --- 167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 169system.physmem.totBusLat 1576000 # Total cycles spent in databus access 170system.physmem.totBankLat 6524000 # Total cycles spent in bank access 171system.physmem.avgQLat 6245.92 # Average queueing delay per request 172system.physmem.avgBankLat 16558.38 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26804.30 # Average memory access latency | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 394 # Categorize read packet sizes 81system.physmem.readPktSize::7 0 # Categorize read packet sizes --- 85 unchanged lines hidden (view full) --- 167system.physmem.totQLat 2460894 # Total cycles spent in queuing delays 168system.physmem.totMemAccLat 10560894 # Sum of mem lat for all requests 169system.physmem.totBusLat 1576000 # Total cycles spent in databus access 170system.physmem.totBankLat 6524000 # Total cycles spent in bank access 171system.physmem.avgQLat 6245.92 # Average queueing delay per request 172system.physmem.avgBankLat 16558.38 # Average bank access latency per request 173system.physmem.avgBusLat 4000.00 # Average bus latency per request 174system.physmem.avgMemAccLat 26804.30 # Average memory access latency |
| 175system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s | 175system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s |
| 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 177system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s | 177system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s |
| 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 11.79 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.79 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 319 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s 180system.physmem.busUtil 11.79 # Data bus utilization in percentage 181system.physmem.avgRdQLen 0.79 # Average read queue length over time 182system.physmem.avgWrQLen 0.00 # Average write queue length over time 183system.physmem.readRowHits 319 # Number of row buffer hits during reads 184system.physmem.writeRowHits 0 # Number of row buffer hits during writes 185system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads 186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 187system.physmem.avgGap 33788.07 # Average gap between requests | 187system.physmem.avgGap 33793.15 # Average gap between requests |
| 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 13 # Number of system calls | 188system.cpu.dtb.inst_hits 0 # ITB inst hits 189system.cpu.dtb.inst_misses 0 # ITB inst misses 190system.cpu.dtb.read_hits 0 # DTB read hits 191system.cpu.dtb.read_misses 0 # DTB read misses 192system.cpu.dtb.write_hits 0 # DTB write hits 193system.cpu.dtb.write_misses 0 # DTB write misses 194system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 195system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 223system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 224system.cpu.itb.read_accesses 0 # DTB read accesses 225system.cpu.itb.write_accesses 0 # DTB write accesses 226system.cpu.itb.inst_accesses 0 # ITB inst accesses 227system.cpu.itb.hits 0 # DTB hits 228system.cpu.itb.misses 0 # DTB misses 229system.cpu.itb.accesses 0 # DTB accesses 230system.cpu.workload.num_syscalls 13 # Number of system calls |
| 231system.cpu.numCycles 26743 # number of cpu cycles simulated | 231system.cpu.numCycles 26745 # number of cpu cycles simulated |
| 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.BPredUnit.lookups 2505 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. | 232system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 233system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 234system.cpu.BPredUnit.lookups 2505 # Number of BP lookups 235system.cpu.BPredUnit.condPredicted 1796 # Number of conditional branches predicted 236system.cpu.BPredUnit.condIncorrect 487 # Number of conditional branches incorrect 237system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups 238system.cpu.BPredUnit.BTBHits 707 # Number of BTB hits 239system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 240system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. 241system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. |
| 242system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss | 242system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss |
| 243system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing | 243system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed 244system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered 245system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken 246system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked 247system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing |
| 248system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked 249system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 250system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched 251system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed 252system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) | 248system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked 249system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched 250system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 251system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) 252system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) |
| 255system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 254system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 256system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) | 255system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) |
| 258system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 267system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 257system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::5 276 2.14% 88.39% # Number of instructions fetched each cycle (Total) 261system.cpu.fetch.rateDist::6 95 0.74% 89.12% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::7 148 1.15% 90.27% # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Number of instructions fetched each cycle (Total) 264system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 266system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 268system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle 270system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle | 267system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle 269system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle |
| 271system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle | 270system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle |
| 272system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked | 271system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked |
| 273system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 274system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 275system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 276system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch 277system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 278system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode 279system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 280system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 281system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle 282system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 283system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst 284system.cpu.rename.RunCycles 2247 # Number of cycles rename is running | 272system.cpu.decode.RunCycles 2446 # Number of cycles decode is running 273system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking 274system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing 275system.cpu.decode.BranchResolved 391 # Number of times decode resolved a branch 276system.cpu.decode.BranchMispred 160 # Number of times decode detected a branch misprediction 277system.cpu.decode.DecodedInsts 13341 # Number of instructions handled by decode 278system.cpu.decode.SquashedInsts 538 # Number of squashed instructions handled by decode 279system.cpu.rename.SquashCycles 963 # Number of cycles rename is squashing 280system.cpu.rename.IdleCycles 7146 # Number of cycles rename is idle 281system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking 282system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst 283system.cpu.rename.RunCycles 2247 # Number of cycles rename is running |
| 285system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking 286system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename | 284system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 285system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename |
| 287system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 288system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 289system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full | 286system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full 287system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 288system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full |
| 290system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed 291system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made 292system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups | 289system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed 290system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made 291system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups |
| 293system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 294system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed | 292system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups 293system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed |
| 295system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing | 294system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing |
| 296system.cpu.rename.serializingInsts 44 # count of serializing insts renamed 297system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 298system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer 299system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. 300system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. 301system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. 302system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 303system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) 304system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 305system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 306system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 307system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling 308system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph 309system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed | 295system.cpu.rename.serializingInsts 44 # count of serializing insts renamed 296system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed 297system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer 298system.cpu.memDep0.insertedLoads 2803 # Number of loads inserted to the mem dependence unit. 299system.cpu.memDep0.insertedStores 1586 # Number of stores inserted to the mem dependence unit. 300system.cpu.memDep0.conflictingLoads 36 # Number of conflicting loads. 301system.cpu.memDep0.conflictingStores 13 # Number of conflicting stores. 302system.cpu.iq.iqInstsAdded 11253 # Number of instructions added to the IQ (excludes non-spec) 303system.cpu.iq.iqNonSpecInstsAdded 53 # Number of non-speculative instructions added to the IQ 304system.cpu.iq.iqInstsIssued 8988 # Number of instructions issued 305system.cpu.iq.iqSquashedInstsIssued 116 # Number of squashed instructions issued 306system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling 307system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph 308system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed |
| 310system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle | 309system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle 310system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle |
| 313system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 312system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 314system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle | 313system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle |
| 315system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle | 314system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle |
| 316system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle | 315system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle |
| 317system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 325system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 316system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle 319system.cpu.iq.issued_per_cycle::6 121 0.94% 99.46% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::7 55 0.43% 99.88% # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Number of insts issued each cycle 322system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 323system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 324system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 326system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle | 325system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle |
| 327system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 328system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 329system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 330system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 334system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 388system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued 390system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued 391system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued 392system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued 393system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 394system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 395system.cpu.iq.FU_type_0::total 8988 # Type of FU issued | 326system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 327system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available 328system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available 329system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available 331system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available 332system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available 333system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 387system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.29% # Type of FU issued 388system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.29% # Type of FU issued 389system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.29% # Type of FU issued 390system.cpu.iq.FU_type_0::MemRead 2349 26.13% 86.43% # Type of FU issued 391system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Type of FU issued 392system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 393system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 394system.cpu.iq.FU_type_0::total 8988 # Type of FU issued |
| 396system.cpu.iq.rate 0.336088 # Inst issue rate | 395system.cpu.iq.rate 0.336063 # Inst issue rate |
| 397system.cpu.iq.fu_busy_cnt 228 # FU busy when requested 398system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) | 396system.cpu.iq.fu_busy_cnt 228 # FU busy when requested 397system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) |
| 399system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads | 398system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads |
| 400system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes 401system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses 402system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 403system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 404system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 405system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 406system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 407system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 414system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 415system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 416system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 417system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 418system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 419system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 420system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 421system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ | 399system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes 400system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses 401system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 402system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes 403system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 404system.cpu.iq.int_alu_accesses 9196 # Number of integer alu accesses 405system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses 406system.cpu.iew.lsq.thread0.forwLoads 57 # Number of loads that had data forwarded from stores --- 6 unchanged lines hidden (view full) --- 413system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 414system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 415system.cpu.iew.lsq.thread0.cacheBlocked 3 # Number of times an access to memory failed due to the cache being blocked 416system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 417system.cpu.iew.iewSquashCycles 963 # Number of cycles IEW is squashing 418system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking 419system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 420system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ |
| 422system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch | 421system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch |
| 423system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions 424system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions 425system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 426system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 427system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 428system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 429system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 430system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 431system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute 432system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions 433system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 434system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute 435system.cpu.iew.exec_swp 0 # number of swp insts executed 436system.cpu.iew.exec_nop 0 # number of nop insts executed 437system.cpu.iew.exec_refs 3300 # number of memory reference insts executed 438system.cpu.iew.exec_branches 1446 # Number of branches executed 439system.cpu.iew.exec_stores 1164 # Number of stores executed | 422system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions 423system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions 424system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions 425system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall 426system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 427system.cpu.iew.memOrderViolationEvents 21 # Number of memory order violations 428system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 429system.cpu.iew.predictedNotTakenIncorrect 276 # Number of branches that were predicted not taken incorrectly 430system.cpu.iew.branchMispredicts 386 # Number of branch mispredicts detected at execute 431system.cpu.iew.iewExecutedInsts 8564 # Number of executed instructions 432system.cpu.iew.iewExecLoadInsts 2136 # Number of load instructions executed 433system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute 434system.cpu.iew.exec_swp 0 # number of swp insts executed 435system.cpu.iew.exec_nop 0 # number of nop insts executed 436system.cpu.iew.exec_refs 3300 # number of memory reference insts executed 437system.cpu.iew.exec_branches 1446 # Number of branches executed 438system.cpu.iew.exec_stores 1164 # Number of stores executed |
| 440system.cpu.iew.exec_rate 0.320233 # Inst execution rate | 439system.cpu.iew.exec_rate 0.320209 # Inst execution rate |
| 441system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit 442system.cpu.iew.wb_count 8109 # cumulative count of insts written-back 443system.cpu.iew.wb_producers 3899 # num instructions producing a value 444system.cpu.iew.wb_consumers 7837 # num instructions consuming a value 445system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 440system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit 441system.cpu.iew.wb_count 8109 # cumulative count of insts written-back 442system.cpu.iew.wb_producers 3899 # num instructions producing a value 443system.cpu.iew.wb_consumers 7837 # num instructions consuming a value 444system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 446system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle | 445system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle |
| 447system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back 448system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 449system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit 450system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 451system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 452system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle --- 21 unchanged lines hidden (view full) --- 476system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 477system.cpu.commit.int_insts 4980 # Number of committed integer instructions. 478system.cpu.commit.function_calls 82 # Number of function calls committed. 479system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 480system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 481system.cpu.rob.rob_reads 22988 # The number of ROB reads 482system.cpu.rob.rob_writes 23599 # The number of ROB writes 483system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself | 446system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back 447system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 448system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit 449system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards 450system.cpu.commit.branchMispredicts 332 # The number of times a branch was mispredicted 451system.cpu.commit.committed_per_cycle::samples 11953 # Number of insts commited each cycle 452system.cpu.commit.committed_per_cycle::mean 0.479712 # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::stdev 1.312760 # Number of insts commited each cycle --- 21 unchanged lines hidden (view full) --- 475system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 476system.cpu.commit.int_insts 4980 # Number of committed integer instructions. 477system.cpu.commit.function_calls 82 # Number of function calls committed. 478system.cpu.commit.bw_lim_events 119 # number cycles where commit BW limit reached 479system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 480system.cpu.rob.rob_reads 22988 # The number of ROB reads 481system.cpu.rob.rob_writes 23599 # The number of ROB writes 482system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 484system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling | 483system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 485system.cpu.committedInsts 4596 # Number of Instructions Simulated 486system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 487system.cpu.committedInsts_total 4596 # Number of Instructions Simulated | 484system.cpu.committedInsts 4596 # Number of Instructions Simulated 485system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated 486system.cpu.committedInsts_total 4596 # Number of Instructions Simulated |
| 488system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction 489system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads 490system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle 491system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads | 487system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction 488system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads 489system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle 490system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads |
| 492system.cpu.int_regfile_reads 39369 # number of integer regfile reads 493system.cpu.int_regfile_writes 8027 # number of integer regfile writes 494system.cpu.fp_regfile_reads 16 # number of floating regfile reads 495system.cpu.misc_regfile_reads 2981 # number of misc regfile reads 496system.cpu.misc_regfile_writes 26 # number of misc regfile writes 497system.cpu.icache.replacements 4 # number of replacements | 491system.cpu.int_regfile_reads 39369 # number of integer regfile reads 492system.cpu.int_regfile_writes 8027 # number of integer regfile writes 493system.cpu.fp_regfile_reads 16 # number of floating regfile reads 494system.cpu.misc_regfile_reads 2981 # number of misc regfile reads 495system.cpu.misc_regfile_writes 26 # number of misc regfile writes 496system.cpu.icache.replacements 4 # number of replacements |
| 498system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use | 497system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use |
| 499system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. 500system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. 501system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. 502system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 498system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. 499system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. 500system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. 501system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 503system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor 504system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy 505system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy | 502system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor 503system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy 504system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy |
| 506system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 507system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 508system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 509system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 510system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 511system.cpu.icache.overall_hits::total 1601 # number of overall hits | 505system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits 506system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits 507system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits 508system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits 509system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits 510system.cpu.icache.overall_hits::total 1601 # number of overall hits |
| 512system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses 513system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses 514system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses 515system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses 516system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses 517system.cpu.icache.overall_misses::total 359 # number of overall misses 518system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles 519system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles 520system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles 521system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles 522system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles 523system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles 524system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) 525system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) 526system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses 527system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses 528system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses 529system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses 530system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses 531system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses 532system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses 533system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses 534system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses 535system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses 536system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency 537system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency 538system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency 539system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency 540system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency 541system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency | 511system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 512system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 513system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 514system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 515system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 516system.cpu.icache.overall_misses::total 360 # number of overall misses 517system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles 518system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles 519system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles 520system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles 521system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles 522system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles 523system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) 524system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) 525system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses 526system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses 527system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses 528system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses 529system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses 530system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses 531system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses 532system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses 533system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses 534system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses 535system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency 536system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency 537system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 538system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency 539system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency 540system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency |
| 542system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 543system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 544system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 545system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 546system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 547system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 548system.cpu.icache.fast_writes 0 # number of fast writes performed 549system.cpu.icache.cache_copies 0 # number of cache copies performed | 541system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked 542system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 543system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked 544system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 545system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked 546system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 547system.cpu.icache.fast_writes 0 # number of fast writes performed 548system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 550system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits 551system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits 552system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits 553system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits 554system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits 555system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits | 549system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 550system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 551system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 552system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 553system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 554system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits |
| 556system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses 557system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses 558system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses 559system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses 560system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses 561system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses | 555system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses 556system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses 557system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses 558system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses 559system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses 560system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses |
| 562system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles 563system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles 564system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles 565system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles 566system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles 567system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles 568system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses 569system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses 570system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses 571system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses 572system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses 573system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses 574system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency 575system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency 576system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency 577system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency 578system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency 579system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency | 561system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles 562system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles 563system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles 564system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles 565system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles 566system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles 567system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses 568system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses 569system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses 570system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses 571system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses 572system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses 573system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency 574system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency 575system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 576system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency 577system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency 578system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency |
| 580system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 579system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 580system.cpu.l2cache.replacements 0 # number of replacements 581system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use 582system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 583system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 584system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. 585system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 586system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor 587system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor 588system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy 589system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy 590system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy 591system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 592system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 593system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 594system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 595system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 596system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 597system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 598system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 599system.cpu.l2cache.overall_hits::total 40 # number of overall hits 600system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 601system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 602system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 603system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 604system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 605system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 606system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 607system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 608system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 609system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 610system.cpu.l2cache.overall_misses::total 399 # number of overall misses 611system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13736500 # number of ReadReq miss cycles 612system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4676000 # number of ReadReq miss cycles 613system.cpu.l2cache.ReadReq_miss_latency::total 18412500 # number of ReadReq miss cycles 614system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 615system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 616system.cpu.l2cache.demand_miss_latency::cpu.inst 13736500 # number of demand (read+write) miss cycles 617system.cpu.l2cache.demand_miss_latency::cpu.data 6947500 # number of demand (read+write) miss cycles 618system.cpu.l2cache.demand_miss_latency::total 20684000 # number of demand (read+write) miss cycles 619system.cpu.l2cache.overall_miss_latency::cpu.inst 13736500 # number of overall miss cycles 620system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles 621system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles 622system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) 623system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 624system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 625system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 626system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 627system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses 628system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 629system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 630system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses 631system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 632system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 633system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses 634system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 635system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses 636system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 637system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 638system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses 639system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 640system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses 641system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses 642system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 643system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses 644system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency 645system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency 646system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency 647system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 648system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 649system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 650system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 651system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency 652system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency 653system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency 654system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # average overall miss latency 655system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 656system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 657system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 658system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 659system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 660system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 661system.cpu.l2cache.fast_writes 0 # number of fast writes performed 662system.cpu.l2cache.cache_copies 0 # number of cache copies performed 663system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 664system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 665system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 666system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 667system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 668system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 669system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 670system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 671system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 672system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 673system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 674system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 675system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 676system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 677system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 678system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 679system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 680system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319902 # number of ReadReq MSHR miss cycles 681system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455564 # number of ReadReq MSHR miss cycles 682system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13775466 # number of ReadReq MSHR miss cycles 683system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 684system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 685system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319902 # number of demand (read+write) MSHR miss cycles 686system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5220104 # number of demand (read+write) MSHR miss cycles 687system.cpu.l2cache.demand_mshr_miss_latency::total 15540006 # number of demand (read+write) MSHR miss cycles 688system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319902 # number of overall MSHR miss cycles 689system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5220104 # number of overall MSHR miss cycles 690system.cpu.l2cache.overall_mshr_miss_latency::total 15540006 # number of overall MSHR miss cycles 691system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses 692system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 693system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses 694system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 695system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 696system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses 697system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 698system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses 699system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses 700system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 701system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses 702system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37940.816176 # average ReadReq mshr miss latency 703system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42661.283951 # average ReadReq mshr miss latency 704system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39023.983003 # average ReadReq mshr miss latency 705system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 706system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 707system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 708system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 709system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 710system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency 711system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency 712system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency 713system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 581system.cpu.dcache.replacements 0 # number of replacements | 714system.cpu.dcache.replacements 0 # number of replacements |
| 582system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use | 715system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use |
| 583system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. 584system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 585system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. 586system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 716system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. 717system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. 718system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. 719system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 587system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor 588system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy 589system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy | 720system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor 721system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy 722system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy |
| 590system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits 591system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits 592system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 593system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 594system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 595system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 596system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 597system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits --- 6 unchanged lines hidden (view full) --- 604system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 605system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 606system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 607system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 608system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 609system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 610system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 611system.cpu.dcache.overall_misses::total 498 # number of overall misses | 723system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits 724system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits 725system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits 726system.cpu.dcache.WriteReq_hits::total 606 # number of WriteReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits --- 6 unchanged lines hidden (view full) --- 737system.cpu.dcache.WriteReq_misses::cpu.data 307 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 307 # number of WriteReq misses 739system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 740system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 741system.cpu.dcache.demand_misses::cpu.data 498 # number of demand (read+write) misses 742system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses 743system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses 744system.cpu.dcache.overall_misses::total 498 # number of overall misses |
| 612system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # number of ReadReq miss cycles 613system.cpu.dcache.ReadReq_miss_latency::total 8138000 # number of ReadReq miss cycles | 745system.cpu.dcache.ReadReq_miss_latency::cpu.data 8139500 # number of ReadReq miss cycles 746system.cpu.dcache.ReadReq_miss_latency::total 8139500 # number of ReadReq miss cycles |
| 614system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 615system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 616system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 617system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles | 747system.cpu.dcache.WriteReq_miss_latency::cpu.data 14907500 # number of WriteReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::total 14907500 # number of WriteReq miss cycles 749system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles |
| 618system.cpu.dcache.demand_miss_latency::cpu.data 23045500 # number of demand (read+write) miss cycles 619system.cpu.dcache.demand_miss_latency::total 23045500 # number of demand (read+write) miss cycles 620system.cpu.dcache.overall_miss_latency::cpu.data 23045500 # number of overall miss cycles 621system.cpu.dcache.overall_miss_latency::total 23045500 # number of overall miss cycles | 751system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles |
| 622system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 623system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 624system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 625system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 626system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 627system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 628system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 629system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 636system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 637system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 638system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 639system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 640system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses 641system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses 642system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses 643system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses | 755system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) 757system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) 760system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) 762system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) --- 6 unchanged lines hidden (view full) --- 769system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.336254 # miss rate for WriteReq accesses 770system.cpu.dcache.WriteReq_miss_rate::total 0.336254 # miss rate for WriteReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses 773system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 # miss rate for demand accesses 774system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses 775system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses 776system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses |
| 644system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency 645system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency | 777system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency 778system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency |
| 646system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 647system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 648system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 649system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency | 779system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency |
| 650system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency 651system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency 653system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency | 783system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 784system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency |
| 654system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 655system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 657system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 658system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 659system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 660system.cpu.dcache.fast_writes 0 # number of fast writes performed 661system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 672system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 673system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 674system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 675system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 676system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 677system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 678system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 679system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses | 787system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked 788system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_mshrs 21 # average number of cycles each access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 793system.cpu.dcache.fast_writes 0 # number of fast writes performed 794system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 10 unchanged lines hidden (view full) --- 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 809system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 810system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 811system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 812system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses |
| 680system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # number of ReadReq MSHR miss cycles 681system.cpu.dcache.ReadReq_mshr_miss_latency::total 4925000 # number of ReadReq MSHR miss cycles | 813system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4926000 # number of ReadReq MSHR miss cycles 814system.cpu.dcache.ReadReq_mshr_miss_latency::total 4926000 # number of ReadReq MSHR miss cycles |
| 682system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 683system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles | 815system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2313500 # number of WriteReq MSHR miss cycles 816system.cpu.dcache.WriteReq_mshr_miss_latency::total 2313500 # number of WriteReq MSHR miss cycles |
| 684system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7238500 # number of demand (read+write) MSHR miss cycles 685system.cpu.dcache.demand_mshr_miss_latency::total 7238500 # number of demand (read+write) MSHR miss cycles 686system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7238500 # number of overall MSHR miss cycles 687system.cpu.dcache.overall_mshr_miss_latency::total 7238500 # number of overall MSHR miss cycles | 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7239500 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 7239500 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7239500 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 7239500 # number of overall MSHR miss cycles |
| 688system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 689system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 690system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 691system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 692system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 693system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 694system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 695system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses | 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054192 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054192 # mshr miss rate for ReadReq accesses 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 825system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for demand accesses 826system.cpu.dcache.demand_mshr_miss_rate::total 0.051237 # mshr miss rate for demand accesses 827system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051237 # mshr miss rate for overall accesses 828system.cpu.dcache.overall_mshr_miss_rate::total 0.051237 # mshr miss rate for overall accesses |
| 696system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46462.264151 # average ReadReq mshr miss latency 697system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46462.264151 # average ReadReq mshr miss latency | 829system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46471.698113 # average ReadReq mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46471.698113 # average ReadReq mshr miss latency |
| 698system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 699system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency | 831system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56426.829268 # average WriteReq mshr miss latency 832system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56426.829268 # average WriteReq mshr miss latency |
| 700system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency 701system.cpu.dcache.demand_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency 702system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49241.496599 # average overall mshr miss latency 703system.cpu.dcache.overall_avg_mshr_miss_latency::total 49241.496599 # average overall mshr miss latency | 833system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 834system.cpu.dcache.demand_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49248.299320 # average overall mshr miss latency 836system.cpu.dcache.overall_avg_mshr_miss_latency::total 49248.299320 # average overall mshr miss latency |
| 704system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 837system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 705system.cpu.l2cache.replacements 0 # number of replacements 706system.cpu.l2cache.tagsinuse 186.102289 # Cycle average of tags in use 707system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. 708system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. 709system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. 710system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 711system.cpu.l2cache.occ_blocks::cpu.inst 139.205724 # Average occupied blocks per requestor 712system.cpu.l2cache.occ_blocks::cpu.data 46.896565 # Average occupied blocks per requestor 713system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy 714system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy 715system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy 716system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 717system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 718system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits 719system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 720system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 721system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits 722system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 723system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 724system.cpu.l2cache.overall_hits::total 40 # number of overall hits 725system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses 726system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 727system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses 728system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses 729system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses 730system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses 731system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 732system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses 733system.cpu.l2cache.overall_misses::cpu.inst 272 # number of overall misses 734system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 735system.cpu.l2cache.overall_misses::total 399 # number of overall misses 736system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13735000 # number of ReadReq miss cycles 737system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4675000 # number of ReadReq miss cycles 738system.cpu.l2cache.ReadReq_miss_latency::total 18410000 # number of ReadReq miss cycles 739system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles 740system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles 741system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles 742system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles 743system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles 744system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles 745system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles 746system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles 747system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) 748system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) 749system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) 750system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 751system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 752system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses 753system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 754system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 755system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses 756system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 757system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 758system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses 759system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses 760system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses 761system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 762system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 763system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses 764system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 765system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses 766system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses 767system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 768system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses 769system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency 770system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency 771system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency 772system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency 773system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency 774system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency 775system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency 776system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency 777system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency 778system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency 779system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency 780system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 781system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 782system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 783system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 784system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 785system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 786system.cpu.l2cache.fast_writes 0 # number of fast writes performed 787system.cpu.l2cache.cache_copies 0 # number of cache copies performed 788system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 789system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 790system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 791system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 792system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 793system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 794system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses 795system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses 796system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses 797system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses 798system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses 799system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 800system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 801system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses 802system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 803system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 804system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses 805system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles 806system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles 807system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles 808system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles 809system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles 810system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles 811system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles 812system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles 813system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles 814system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles 815system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles 816system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses 817system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses 818system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses 819system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 820system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 821system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses 822system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 823system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses 824system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses 825system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 826system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses 827system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency 828system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency 829system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency 830system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency 831system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency 832system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency 833system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency 834system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency 835system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency 836system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency 837system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency 838system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 839 840---------- End Simulation Statistics ---------- | 838 839---------- End Simulation Statistics ---------- |