| stats.txt (8911:4da2ea94319f) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated 4sim_ticks 10303500 # Number of ticks simulated 5final_tick 10303500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 48410 # Simulator instruction rate (inst/s) 8host_op_rate 60388 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 108401694 # Simulator tick rate (ticks/s) 10host_mem_usage 222284 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host | 7host_inst_rate 29431 # Simulator instruction rate (inst/s) 8host_op_rate 36712 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 65901409 # Simulator tick rate (ticks/s) 10host_mem_usage 229344 # Number of bytes of host memory used 11host_seconds 0.16 # Real time elapsed on the host |
| 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 25664 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 401 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 349 unchanged lines hidden (view full) --- 369system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency 371system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 25664 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 401 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 349 unchanged lines hidden (view full) --- 369system.cpu.icache.overall_miss_rate::cpu.inst 0.180207 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34474.043716 # average ReadReq miss latency 371system.cpu.icache.demand_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::cpu.inst 34474.043716 # average overall miss latency 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 377system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 377system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 382system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 383system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 384system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 385system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 386system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 466system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 468system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 469system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 470system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed 381system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits 382system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits 383system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits 384system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits 385system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits 386system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits --- 78 unchanged lines hidden (view full) --- 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency 466system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 468system.cpu.dcache.overall_avg_miss_latency::cpu.data 34568.565401 # average overall miss latency 469system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 470system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 473system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 474system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 473system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 474system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 475system.cpu.dcache.fast_writes 0 # number of fast writes performed 476system.cpu.dcache.cache_copies 0 # number of cache copies performed 477system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 478system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 479system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 480system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 481system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 482system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 92 unchanged lines hidden (view full) --- 575system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 475system.cpu.dcache.fast_writes 0 # number of fast writes performed 476system.cpu.dcache.cache_copies 0 # number of cache copies performed 477system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 478system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 479system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 480system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 481system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 482system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 92 unchanged lines hidden (view full) --- 575system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34331.521739 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34461.240310 # average overall miss latency 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed 587system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 588system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 589system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 590system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 591system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 592system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits --- 39 unchanged lines hidden --- | 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed 587system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 588system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 589system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 590system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 591system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 592system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits --- 39 unchanged lines hidden --- |