| stats.txt (8835:7c68f84d7c4e) | stats.txt (8844:a451e4eda591) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000010 # Number of seconds simulated |
| 4sim_ticks 10000500 # Number of ticks simulated 5final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 10389500 # Number of ticks simulated 5final_tick 10389500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 72927 # Simulator instruction rate (inst/s) 8host_op_rate 90959 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 158457261 # Simulator tick rate (ticks/s) 10host_mem_usage 221260 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 66059 # Simulator instruction rate (inst/s) 8host_op_rate 82394 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 149123755 # Simulator tick rate (ticks/s) 10host_mem_usage 221320 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated | 12sim_insts 4600 # Number of instructions simulated 13sim_ops 5739 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 25856 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory | 14system.physmem.bytes_read 25600 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory |
| 16system.physmem.bytes_written 0 # Number of bytes written to this memory | 16system.physmem.bytes_written 0 # Number of bytes written to this memory |
| 17system.physmem.num_reads 404 # Number of read requests responded to by this memory | 17system.physmem.num_reads 400 # Number of read requests responded to by this memory |
| 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory | 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory |
| 20system.physmem.bw_read 2585470726 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1785510724 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2585470726 # Total bandwidth to/from this memory (bytes/s) | 20system.physmem.bw_read 2464026180 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1700178064 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2464026180 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu.dtb.inst_hits 0 # ITB inst hits 24system.cpu.dtb.inst_misses 0 # ITB inst misses 25system.cpu.dtb.read_hits 0 # DTB read hits 26system.cpu.dtb.read_misses 0 # DTB read misses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.itb.read_accesses 0 # DTB read accesses 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.itb.hits 0 # DTB hits 63system.cpu.itb.misses 0 # DTB misses 64system.cpu.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 13 # Number of system calls | 23system.cpu.dtb.inst_hits 0 # ITB inst hits 24system.cpu.dtb.inst_misses 0 # ITB inst misses 25system.cpu.dtb.read_hits 0 # DTB read hits 26system.cpu.dtb.read_misses 0 # DTB read misses 27system.cpu.dtb.write_hits 0 # DTB write hits 28system.cpu.dtb.write_misses 0 # DTB write misses 29system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 30system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 27 unchanged lines hidden (view full) --- 58system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 59system.cpu.itb.read_accesses 0 # DTB read accesses 60system.cpu.itb.write_accesses 0 # DTB write accesses 61system.cpu.itb.inst_accesses 0 # ITB inst accesses 62system.cpu.itb.hits 0 # DTB hits 63system.cpu.itb.misses 0 # DTB misses 64system.cpu.itb.accesses 0 # DTB accesses 65system.cpu.workload.num_syscalls 13 # Number of system calls |
| 66system.cpu.numCycles 20002 # number of cpu cycles simulated | 66system.cpu.numCycles 20780 # number of cpu cycles simulated |
| 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 67system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 68system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 69system.cpu.BPredUnit.lookups 2398 # Number of BP lookups 70system.cpu.BPredUnit.condPredicted 1771 # Number of conditional branches predicted 71system.cpu.BPredUnit.condIncorrect 436 # Number of conditional branches incorrect 72system.cpu.BPredUnit.BTBLookups 1789 # Number of BTB lookups 73system.cpu.BPredUnit.BTBHits 703 # Number of BTB hits | 69system.cpu.BPredUnit.lookups 2550 # Number of BP lookups 70system.cpu.BPredUnit.condPredicted 1890 # Number of conditional branches predicted 71system.cpu.BPredUnit.condIncorrect 477 # Number of conditional branches incorrect 72system.cpu.BPredUnit.BTBLookups 1987 # Number of BTB lookups 73system.cpu.BPredUnit.BTBHits 688 # Number of BTB hits |
| 74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 74system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 75system.cpu.BPredUnit.usedRAS 246 # Number of times the RAS was used to get a target. 76system.cpu.BPredUnit.RASInCorrect 51 # Number of incorrect RAS predictions. 77system.cpu.fetch.icacheStallCycles 6118 # Number of cycles fetch is stalled on an Icache miss 78system.cpu.fetch.Insts 12133 # Number of instructions fetch has processed 79system.cpu.fetch.Branches 2398 # Number of branches that fetch encountered 80system.cpu.fetch.predictedBranches 949 # Number of branches that fetch has predicted taken 81system.cpu.fetch.Cycles 2694 # Number of cycles fetch has run and was not squashing or blocked 82system.cpu.fetch.SquashCycles 1578 # Number of cycles fetch has spent squashing 83system.cpu.fetch.BlockedCycles 1626 # Number of cycles fetch has spent blocked | 75system.cpu.BPredUnit.usedRAS 244 # Number of times the RAS was used to get a target. 76system.cpu.BPredUnit.RASInCorrect 55 # Number of incorrect RAS predictions. 77system.cpu.fetch.icacheStallCycles 6285 # Number of cycles fetch is stalled on an Icache miss 78system.cpu.fetch.Insts 13028 # Number of instructions fetch has processed 79system.cpu.fetch.Branches 2550 # Number of branches that fetch encountered 80system.cpu.fetch.predictedBranches 932 # Number of branches that fetch has predicted taken 81system.cpu.fetch.Cycles 2849 # Number of cycles fetch has run and was not squashing or blocked 82system.cpu.fetch.SquashCycles 1782 # Number of cycles fetch has spent squashing 83system.cpu.fetch.BlockedCycles 1735 # Number of cycles fetch has spent blocked |
| 84system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 84system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 85system.cpu.fetch.PendingTrapStallCycles 19 # Number of stall cycles due to pending traps 86system.cpu.fetch.CacheLines 1919 # Number of cache lines fetched 87system.cpu.fetch.IcacheSquashes 303 # Number of outstanding Icache misses that were squashed 88system.cpu.fetch.rateDist::samples 11508 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::mean 1.338286 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::stdev 2.716814 # Number of instructions fetched each cycle (Total) | 85system.cpu.fetch.PendingTrapStallCycles 42 # Number of stall cycles due to pending traps 86system.cpu.fetch.CacheLines 2028 # Number of cache lines fetched 87system.cpu.fetch.IcacheSquashes 296 # Number of outstanding Icache misses that were squashed 88system.cpu.fetch.rateDist::samples 12124 # Number of instructions fetched each cycle (Total) 89system.cpu.fetch.rateDist::mean 1.372402 # Number of instructions fetched each cycle (Total) 90system.cpu.fetch.rateDist::stdev 2.762919 # Number of instructions fetched each cycle (Total) |
| 91system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 91system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 92system.cpu.fetch.rateDist::0 8814 76.59% 76.59% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::1 262 2.28% 78.87% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::2 169 1.47% 80.34% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::3 225 1.96% 82.29% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::4 227 1.97% 84.26% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::5 313 2.72% 86.98% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::6 109 0.95% 87.93% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::7 113 0.98% 88.91% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::8 1276 11.09% 100.00% # Number of instructions fetched each cycle (Total) | 92system.cpu.fetch.rateDist::0 9275 76.50% 76.50% # Number of instructions fetched each cycle (Total) 93system.cpu.fetch.rateDist::1 244 2.01% 78.51% # Number of instructions fetched each cycle (Total) 94system.cpu.fetch.rateDist::2 198 1.63% 80.15% # Number of instructions fetched each cycle (Total) 95system.cpu.fetch.rateDist::3 226 1.86% 82.01% # Number of instructions fetched each cycle (Total) 96system.cpu.fetch.rateDist::4 226 1.86% 83.87% # Number of instructions fetched each cycle (Total) 97system.cpu.fetch.rateDist::5 278 2.29% 86.17% # Number of instructions fetched each cycle (Total) 98system.cpu.fetch.rateDist::6 125 1.03% 87.20% # Number of instructions fetched each cycle (Total) 99system.cpu.fetch.rateDist::7 139 1.15% 88.35% # Number of instructions fetched each cycle (Total) 100system.cpu.fetch.rateDist::8 1413 11.65% 100.00% # Number of instructions fetched each cycle (Total) |
| 101system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 101system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 102system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 103system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 104system.cpu.fetch.rateDist::total 11508 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.branchRate 0.119888 # Number of branch fetches per cycle 106system.cpu.fetch.rate 0.606589 # Number of inst fetches per cycle 107system.cpu.decode.IdleCycles 6263 # Number of cycles decode is idle 108system.cpu.decode.BlockedCycles 1809 # Number of cycles decode is blocked 109system.cpu.decode.RunCycles 2491 # Number of cycles decode is running 110system.cpu.decode.UnblockCycles 58 # Number of cycles decode is unblocking 111system.cpu.decode.SquashCycles 887 # Number of cycles decode is squashing 112system.cpu.decode.BranchResolved 401 # Number of times decode resolved a branch 113system.cpu.decode.BranchMispred 168 # Number of times decode detected a branch misprediction 114system.cpu.decode.DecodedInsts 13387 # Number of instructions handled by decode 115system.cpu.decode.SquashedInsts 587 # Number of squashed instructions handled by decode 116system.cpu.rename.SquashCycles 887 # Number of cycles rename is squashing 117system.cpu.rename.IdleCycles 6539 # Number of cycles rename is idle 118system.cpu.rename.BlockCycles 230 # Number of cycles rename is blocking 119system.cpu.rename.serializeStallCycles 1411 # count of cycles rename stalled for serializing inst 120system.cpu.rename.RunCycles 2270 # Number of cycles rename is running 121system.cpu.rename.UnblockCycles 171 # Number of cycles rename is unblocking 122system.cpu.rename.RenamedInsts 12504 # Number of instructions processed by rename 123system.cpu.rename.LSQFullEvents 153 # Number of times rename has blocked due to LSQ full 124system.cpu.rename.RenamedOperands 12063 # Number of destination operands rename has renamed 125system.cpu.rename.RenameLookups 57218 # Number of register rename lookups that rename has made 126system.cpu.rename.int_rename_lookups 56026 # Number of integer rename lookups 127system.cpu.rename.fp_rename_lookups 1192 # Number of floating rename lookups | 104system.cpu.fetch.rateDist::total 12124 # Number of instructions fetched each cycle (Total) 105system.cpu.fetch.branchRate 0.122714 # Number of branch fetches per cycle 106system.cpu.fetch.rate 0.626949 # Number of inst fetches per cycle 107system.cpu.decode.IdleCycles 6488 # Number of cycles decode is idle 108system.cpu.decode.BlockedCycles 1902 # Number of cycles decode is blocked 109system.cpu.decode.RunCycles 2634 # Number of cycles decode is running 110system.cpu.decode.UnblockCycles 56 # Number of cycles decode is unblocking 111system.cpu.decode.SquashCycles 1044 # Number of cycles decode is squashing 112system.cpu.decode.BranchResolved 445 # Number of times decode resolved a branch 113system.cpu.decode.BranchMispred 175 # Number of times decode detected a branch misprediction 114system.cpu.decode.DecodedInsts 14514 # Number of instructions handled by decode 115system.cpu.decode.SquashedInsts 580 # Number of squashed instructions handled by decode 116system.cpu.rename.SquashCycles 1044 # Number of cycles rename is squashing 117system.cpu.rename.IdleCycles 6777 # Number of cycles rename is idle 118system.cpu.rename.BlockCycles 274 # Number of cycles rename is blocking 119system.cpu.rename.serializeStallCycles 1438 # count of cycles rename stalled for serializing inst 120system.cpu.rename.RunCycles 2397 # Number of cycles rename is running 121system.cpu.rename.UnblockCycles 194 # Number of cycles rename is unblocking 122system.cpu.rename.RenamedInsts 13625 # Number of instructions processed by rename 123system.cpu.rename.IQFullEvents 14 # Number of times rename has blocked due to IQ full 124system.cpu.rename.LSQFullEvents 154 # Number of times rename has blocked due to LSQ full 125system.cpu.rename.RenamedOperands 13271 # Number of destination operands rename has renamed 126system.cpu.rename.RenameLookups 62674 # Number of register rename lookups that rename has made 127system.cpu.rename.int_rename_lookups 61282 # Number of integer rename lookups 128system.cpu.rename.fp_rename_lookups 1392 # Number of floating rename lookups |
| 128system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed | 129system.cpu.rename.CommittedMaps 5684 # Number of HB maps that are committed |
| 129system.cpu.rename.UndoneMaps 6379 # Number of HB maps that are undone due to squashing 130system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 131system.cpu.rename.tempSerializingInsts 39 # count of temporary serializing insts renamed 132system.cpu.rename.skidInsts 478 # count of insts added to the skid buffer 133system.cpu.memDep0.insertedLoads 2574 # Number of loads inserted to the mem dependence unit. 134system.cpu.memDep0.insertedStores 1703 # Number of stores inserted to the mem dependence unit. 135system.cpu.memDep0.conflictingLoads 9 # Number of conflicting loads. 136system.cpu.memDep0.conflictingStores 8 # Number of conflicting stores. 137system.cpu.iq.iqInstsAdded 10784 # Number of instructions added to the IQ (excludes non-spec) 138system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 139system.cpu.iq.iqInstsIssued 8706 # Number of instructions issued 140system.cpu.iq.iqSquashedInstsIssued 95 # Number of squashed instructions issued 141system.cpu.iq.iqSquashedInstsExamined 4802 # Number of squashed instructions iterated over during squash; mainly for profiling 142system.cpu.iq.iqSquashedOperandsExamined 13397 # Number of squashed operands that are examined and possibly removed from graph 143system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 144system.cpu.iq.issued_per_cycle::samples 11508 # Number of insts issued each cycle 145system.cpu.iq.issued_per_cycle::mean 0.756517 # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::stdev 1.438154 # Number of insts issued each cycle | 130system.cpu.rename.UndoneMaps 7587 # Number of HB maps that are undone due to squashing 131system.cpu.rename.serializingInsts 48 # count of serializing insts renamed 132system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed 133system.cpu.rename.skidInsts 646 # count of insts added to the skid buffer 134system.cpu.memDep0.insertedLoads 2866 # Number of loads inserted to the mem dependence unit. 135system.cpu.memDep0.insertedStores 1785 # Number of stores inserted to the mem dependence unit. 136system.cpu.memDep0.conflictingLoads 16 # Number of conflicting loads. 137system.cpu.memDep0.conflictingStores 12 # Number of conflicting stores. 138system.cpu.iq.iqInstsAdded 11782 # Number of instructions added to the IQ (excludes non-spec) 139system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ 140system.cpu.iq.iqInstsIssued 9138 # Number of instructions issued 141system.cpu.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued 142system.cpu.iq.iqSquashedInstsExamined 5710 # Number of squashed instructions iterated over during squash; mainly for profiling 143system.cpu.iq.iqSquashedOperandsExamined 16685 # Number of squashed operands that are examined and possibly removed from graph 144system.cpu.iq.iqSquashedNonSpecRemoved 19 # Number of squashed non-spec instructions that were removed 145system.cpu.iq.issued_per_cycle::samples 12124 # Number of insts issued each cycle 146system.cpu.iq.issued_per_cycle::mean 0.753712 # Number of insts issued each cycle 147system.cpu.iq.issued_per_cycle::stdev 1.440468 # Number of insts issued each cycle |
| 147system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 148system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 148system.cpu.iq.issued_per_cycle::0 8023 69.72% 69.72% # Number of insts issued each cycle 149system.cpu.iq.issued_per_cycle::1 1281 11.13% 80.85% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::2 772 6.71% 87.56% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::3 541 4.70% 92.26% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::4 447 3.88% 96.14% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::5 256 2.22% 98.37% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::6 137 1.19% 99.56% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::7 40 0.35% 99.90% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::8 11 0.10% 100.00% # Number of insts issued each cycle | 149system.cpu.iq.issued_per_cycle::0 8489 70.02% 70.02% # Number of insts issued each cycle 150system.cpu.iq.issued_per_cycle::1 1331 10.98% 81.00% # Number of insts issued each cycle 151system.cpu.iq.issued_per_cycle::2 789 6.51% 87.50% # Number of insts issued each cycle 152system.cpu.iq.issued_per_cycle::3 561 4.63% 92.13% # Number of insts issued each cycle 153system.cpu.iq.issued_per_cycle::4 477 3.93% 96.07% # Number of insts issued each cycle 154system.cpu.iq.issued_per_cycle::5 294 2.42% 98.49% # Number of insts issued each cycle 155system.cpu.iq.issued_per_cycle::6 126 1.04% 99.53% # Number of insts issued each cycle 156system.cpu.iq.issued_per_cycle::7 44 0.36% 99.89% # Number of insts issued each cycle 157system.cpu.iq.issued_per_cycle::8 13 0.11% 100.00% # Number of insts issued each cycle |
| 157system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 158system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 158system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 159system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 160system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 160system.cpu.iq.issued_per_cycle::total 11508 # Number of insts issued each cycle | 161system.cpu.iq.issued_per_cycle::total 12124 # Number of insts issued each cycle |
| 161system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 162system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 162system.cpu.iq.fu_full::IntAlu 2 0.99% 0.99% # attempts to use FU when none available 163system.cpu.iq.fu_full::IntMult 0 0.00% 0.99% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntDiv 0 0.00% 0.99% # attempts to use FU when none available 165system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.99% # attempts to use FU when none available 166system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.99% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.99% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatMult 0 0.00% 0.99% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.99% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.99% # attempts to use FU when none available 171system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.99% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.99% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.99% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.99% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.99% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.99% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdMult 0 0.00% 0.99% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.99% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdShift 0 0.00% 0.99% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.99% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.99% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.99% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.99% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.99% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.99% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.99% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.99% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.99% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.99% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.99% # attempts to use FU when none available 191system.cpu.iq.fu_full::MemRead 137 67.49% 68.47% # attempts to use FU when none available 192system.cpu.iq.fu_full::MemWrite 64 31.53% 100.00% # attempts to use FU when none available | 163system.cpu.iq.fu_full::IntAlu 2 0.93% 0.93% # attempts to use FU when none available 164system.cpu.iq.fu_full::IntMult 0 0.00% 0.93% # attempts to use FU when none available 165system.cpu.iq.fu_full::IntDiv 0 0.00% 0.93% # attempts to use FU when none available 166system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.93% # attempts to use FU when none available 167system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.93% # attempts to use FU when none available 168system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.93% # attempts to use FU when none available 169system.cpu.iq.fu_full::FloatMult 0 0.00% 0.93% # attempts to use FU when none available 170system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.93% # attempts to use FU when none available 171system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 172system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.93% # attempts to use FU when none available 173system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.93% # attempts to use FU when none available 174system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.93% # attempts to use FU when none available 175system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.93% # attempts to use FU when none available 176system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.93% # attempts to use FU when none available 177system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.93% # attempts to use FU when none available 178system.cpu.iq.fu_full::SimdMult 0 0.00% 0.93% # attempts to use FU when none available 179system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.93% # attempts to use FU when none available 180system.cpu.iq.fu_full::SimdShift 0 0.00% 0.93% # attempts to use FU when none available 181system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.93% # attempts to use FU when none available 182system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.93% # attempts to use FU when none available 183system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.93% # attempts to use FU when none available 184system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.93% # attempts to use FU when none available 185system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.93% # attempts to use FU when none available 186system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.93% # attempts to use FU when none available 187system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.93% # attempts to use FU when none available 188system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.93% # attempts to use FU when none available 189system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.93% # attempts to use FU when none available 190system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.93% # attempts to use FU when none available 191system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.93% # attempts to use FU when none available 192system.cpu.iq.fu_full::MemRead 150 69.77% 70.70% # attempts to use FU when none available 193system.cpu.iq.fu_full::MemWrite 63 29.30% 100.00% # attempts to use FU when none available |
| 193system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 194system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 195system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 194system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 195system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 196system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 196system.cpu.iq.FU_type_0::IntAlu 5272 60.56% 60.56% # Type of FU issued 197system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.62% # Type of FU issued 198system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.62% # Type of FU issued 199system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.62% # Type of FU issued 200system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.62% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.62% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.62% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.62% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.62% # Type of FU issued 205system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.62% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.62% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.62% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.62% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.62% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.62% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.62% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.62% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.62% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.62% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.62% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.62% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.62% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.62% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.62% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.62% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.66% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.66% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.66% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.66% # Type of FU issued 225system.cpu.iq.FU_type_0::MemRead 2203 25.30% 85.96% # Type of FU issued 226system.cpu.iq.FU_type_0::MemWrite 1222 14.04% 100.00% # Type of FU issued | 197system.cpu.iq.FU_type_0::IntAlu 5491 60.09% 60.09% # Type of FU issued 198system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.17% # Type of FU issued 199system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.17% # Type of FU issued 200system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.17% # Type of FU issued 201system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.17% # Type of FU issued 202system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.17% # Type of FU issued 203system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.17% # Type of FU issued 204system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.17% # Type of FU issued 205system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.17% # Type of FU issued 206system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.17% # Type of FU issued 207system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.17% # Type of FU issued 208system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.17% # Type of FU issued 209system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.17% # Type of FU issued 210system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.17% # Type of FU issued 211system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.17% # Type of FU issued 212system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.17% # Type of FU issued 213system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.17% # Type of FU issued 214system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.17% # Type of FU issued 215system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.17% # Type of FU issued 216system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.17% # Type of FU issued 217system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.17% # Type of FU issued 218system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.17% # Type of FU issued 219system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.17% # Type of FU issued 220system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.17% # Type of FU issued 221system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.17% # Type of FU issued 222system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.20% # Type of FU issued 223system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.20% # Type of FU issued 224system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.20% # Type of FU issued 225system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.20% # Type of FU issued 226system.cpu.iq.FU_type_0::MemRead 2383 26.08% 86.28% # Type of FU issued 227system.cpu.iq.FU_type_0::MemWrite 1254 13.72% 100.00% # Type of FU issued |
| 227system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 228system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 228system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 229system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 229system.cpu.iq.FU_type_0::total 8706 # Type of FU issued 230system.cpu.iq.rate 0.435256 # Inst issue rate 231system.cpu.iq.fu_busy_cnt 203 # FU busy when requested 232system.cpu.iq.fu_busy_rate 0.023317 # FU busy rate (busy events/executed inst) 233system.cpu.iq.int_inst_queue_reads 29182 # Number of integer instruction queue reads 234system.cpu.iq.int_inst_queue_writes 15632 # Number of integer instruction queue writes 235system.cpu.iq.int_inst_queue_wakeup_accesses 7824 # Number of integer instruction queue wakeup accesses | 230system.cpu.iq.FU_type_0::total 9138 # Type of FU issued 231system.cpu.iq.rate 0.439750 # Inst issue rate 232system.cpu.iq.fu_busy_cnt 215 # FU busy when requested 233system.cpu.iq.fu_busy_rate 0.023528 # FU busy rate (busy events/executed inst) 234system.cpu.iq.int_inst_queue_reads 30688 # Number of integer instruction queue reads 235system.cpu.iq.int_inst_queue_writes 17549 # Number of integer instruction queue writes 236system.cpu.iq.int_inst_queue_wakeup_accesses 8140 # Number of integer instruction queue wakeup accesses |
| 236system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 237system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 238system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 237system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads 238system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 239system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 239system.cpu.iq.int_alu_accesses 8889 # Number of integer alu accesses | 240system.cpu.iq.int_alu_accesses 9333 # Number of integer alu accesses |
| 240system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses | 241system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses |
| 241system.cpu.iew.lsq.thread0.forwLoads 51 # Number of loads that had data forwarded from stores | 242system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores |
| 242system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 243system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 243system.cpu.iew.lsq.thread0.squashedLoads 1373 # Number of loads squashed | 244system.cpu.iew.lsq.thread0.squashedLoads 1665 # Number of loads squashed |
| 244system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed | 245system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| 245system.cpu.iew.lsq.thread0.memOrderViolation 14 # Number of memory ordering violations 246system.cpu.iew.lsq.thread0.squashedStores 765 # Number of stores squashed | 246system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations 247system.cpu.iew.lsq.thread0.squashedStores 847 # Number of stores squashed |
| 247system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 248system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 249system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 250system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 251system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 248system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 249system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 250system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 251system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked 252system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 252system.cpu.iew.iewSquashCycles 887 # Number of cycles IEW is squashing 253system.cpu.iew.iewBlockCycles 121 # Number of cycles IEW is blocking 254system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking 255system.cpu.iew.iewDispatchedInsts 10834 # Number of instructions dispatched to IQ | 253system.cpu.iew.iewSquashCycles 1044 # Number of cycles IEW is squashing 254system.cpu.iew.iewBlockCycles 169 # Number of cycles IEW is blocking 255system.cpu.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking 256system.cpu.iew.iewDispatchedInsts 11839 # Number of instructions dispatched to IQ |
| 256system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch | 257system.cpu.iew.iewDispSquashedInsts 179 # Number of squashed instructions skipped by dispatch |
| 257system.cpu.iew.iewDispLoadInsts 2574 # Number of dispatched load instructions 258system.cpu.iew.iewDispStoreInsts 1703 # Number of dispatched store instructions 259system.cpu.iew.iewDispNonSpecInsts 37 # Number of dispatched non-speculative instructions 260system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall | 258system.cpu.iew.iewDispLoadInsts 2866 # Number of dispatched load instructions 259system.cpu.iew.iewDispStoreInsts 1785 # Number of dispatched store instructions 260system.cpu.iew.iewDispNonSpecInsts 44 # Number of dispatched non-speculative instructions 261system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall |
| 261system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall | 262system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| 262system.cpu.iew.memOrderViolationEvents 14 # Number of memory order violations 263system.cpu.iew.predictedTakenIncorrect 90 # Number of branches that were predicted taken incorrectly 264system.cpu.iew.predictedNotTakenIncorrect 295 # Number of branches that were predicted not taken incorrectly 265system.cpu.iew.branchMispredicts 385 # Number of branch mispredicts detected at execute 266system.cpu.iew.iewExecutedInsts 8282 # Number of executed instructions 267system.cpu.iew.iewExecLoadInsts 2009 # Number of load instructions executed 268system.cpu.iew.iewExecSquashedInsts 424 # Number of squashed instructions skipped in execute | 263system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations 264system.cpu.iew.predictedTakenIncorrect 100 # Number of branches that were predicted taken incorrectly 265system.cpu.iew.predictedNotTakenIncorrect 326 # Number of branches that were predicted not taken incorrectly 266system.cpu.iew.branchMispredicts 426 # Number of branch mispredicts detected at execute 267system.cpu.iew.iewExecutedInsts 8635 # Number of executed instructions 268system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed 269system.cpu.iew.iewExecSquashedInsts 503 # Number of squashed instructions skipped in execute |
| 269system.cpu.iew.exec_swp 0 # number of swp insts executed 270system.cpu.iew.exec_nop 1 # number of nop insts executed | 270system.cpu.iew.exec_swp 0 # number of swp insts executed 271system.cpu.iew.exec_nop 1 # number of nop insts executed |
| 271system.cpu.iew.exec_refs 3178 # number of memory reference insts executed 272system.cpu.iew.exec_branches 1354 # Number of branches executed 273system.cpu.iew.exec_stores 1169 # Number of stores executed 274system.cpu.iew.exec_rate 0.414059 # Inst execution rate 275system.cpu.iew.wb_sent 7957 # cumulative count of insts sent to commit 276system.cpu.iew.wb_count 7840 # cumulative count of insts written-back 277system.cpu.iew.wb_producers 3690 # num instructions producing a value 278system.cpu.iew.wb_consumers 7291 # num instructions consuming a value | 272system.cpu.iew.exec_refs 3325 # number of memory reference insts executed 273system.cpu.iew.exec_branches 1404 # Number of branches executed 274system.cpu.iew.exec_stores 1195 # Number of stores executed 275system.cpu.iew.exec_rate 0.415544 # Inst execution rate 276system.cpu.iew.wb_sent 8328 # cumulative count of insts sent to commit 277system.cpu.iew.wb_count 8156 # cumulative count of insts written-back 278system.cpu.iew.wb_producers 3863 # num instructions producing a value 279system.cpu.iew.wb_consumers 7813 # num instructions consuming a value |
| 279system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 280system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 280system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle 281system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back | 281system.cpu.iew.wb_rate 0.392493 # insts written-back per cycle 282system.cpu.iew.wb_fanout 0.494432 # average fanout of values written-back |
| 282system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 283system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions 284system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions | 283system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 284system.cpu.commit.commitCommittedInsts 4600 # The number of committed instructions 285system.cpu.commit.commitCommittedOps 5739 # The number of committed instructions |
| 285system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit | 286system.cpu.commit.commitSquashedInsts 6099 # The number of squashed insts skipped by commit |
| 286system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards | 287system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards |
| 287system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted 288system.cpu.commit.committed_per_cycle::samples 10622 # Number of insts commited each cycle 289system.cpu.commit.committed_per_cycle::mean 0.540294 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::stdev 1.352838 # Number of insts commited each cycle | 288system.cpu.commit.branchMispredicts 380 # The number of times a branch was mispredicted 289system.cpu.commit.committed_per_cycle::samples 11081 # Number of insts commited each cycle 290system.cpu.commit.committed_per_cycle::mean 0.517914 # Number of insts commited each cycle 291system.cpu.commit.committed_per_cycle::stdev 1.332416 # Number of insts commited each cycle |
| 291system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 292system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 292system.cpu.commit.committed_per_cycle::0 8286 78.01% 78.01% # Number of insts commited each cycle 293system.cpu.commit.committed_per_cycle::1 1088 10.24% 88.25% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::2 420 3.95% 92.20% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::3 282 2.65% 94.86% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::4 183 1.72% 96.58% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::5 168 1.58% 98.16% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::6 65 0.61% 98.78% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::7 37 0.35% 99.12% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::8 93 0.88% 100.00% # Number of insts commited each cycle | 293system.cpu.commit.committed_per_cycle::0 8736 78.84% 78.84% # Number of insts commited each cycle 294system.cpu.commit.committed_per_cycle::1 1106 9.98% 88.82% # Number of insts commited each cycle 295system.cpu.commit.committed_per_cycle::2 431 3.89% 92.71% # Number of insts commited each cycle 296system.cpu.commit.committed_per_cycle::3 257 2.32% 95.03% # Number of insts commited each cycle 297system.cpu.commit.committed_per_cycle::4 182 1.64% 96.67% # Number of insts commited each cycle 298system.cpu.commit.committed_per_cycle::5 177 1.60% 98.27% # Number of insts commited each cycle 299system.cpu.commit.committed_per_cycle::6 55 0.50% 98.76% # Number of insts commited each cycle 300system.cpu.commit.committed_per_cycle::7 39 0.35% 99.12% # Number of insts commited each cycle 301system.cpu.commit.committed_per_cycle::8 98 0.88% 100.00% # Number of insts commited each cycle |
| 301system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 302system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 302system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 303system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 304system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 304system.cpu.commit.committed_per_cycle::total 10622 # Number of insts commited each cycle | 305system.cpu.commit.committed_per_cycle::total 11081 # Number of insts commited each cycle |
| 305system.cpu.commit.committedInsts 4600 # Number of instructions committed 306system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed 307system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 308system.cpu.commit.refs 2139 # Number of memory references committed 309system.cpu.commit.loads 1201 # Number of loads committed 310system.cpu.commit.membars 12 # Number of memory barriers committed 311system.cpu.commit.branches 945 # Number of branches committed 312system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 313system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 314system.cpu.commit.function_calls 82 # Number of function calls committed. | 306system.cpu.commit.committedInsts 4600 # Number of instructions committed 307system.cpu.commit.committedOps 5739 # Number of ops (including micro ops) committed 308system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 309system.cpu.commit.refs 2139 # Number of memory references committed 310system.cpu.commit.loads 1201 # Number of loads committed 311system.cpu.commit.membars 12 # Number of memory barriers committed 312system.cpu.commit.branches 945 # Number of branches committed 313system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. 314system.cpu.commit.int_insts 4985 # Number of committed integer instructions. 315system.cpu.commit.function_calls 82 # Number of function calls committed. |
| 315system.cpu.commit.bw_lim_events 93 # number cycles where commit BW limit reached | 316system.cpu.commit.bw_lim_events 98 # number cycles where commit BW limit reached |
| 316system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 317system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 317system.cpu.rob.rob_reads 21205 # The number of ROB reads 318system.cpu.rob.rob_writes 22566 # The number of ROB writes 319system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself 320system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling | 318system.cpu.rob.rob_reads 22664 # The number of ROB reads 319system.cpu.rob.rob_writes 24737 # The number of ROB writes 320system.cpu.timesIdled 179 # Number of times that the entire CPU went into an idle state and unscheduled itself 321system.cpu.idleCycles 8656 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 321system.cpu.committedInsts 4600 # Number of Instructions Simulated 322system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated 323system.cpu.committedInsts_total 4600 # Number of Instructions Simulated | 322system.cpu.committedInsts 4600 # Number of Instructions Simulated 323system.cpu.committedOps 5739 # Number of Ops (including micro ops) Simulated 324system.cpu.committedInsts_total 4600 # Number of Instructions Simulated |
| 324system.cpu.cpi 4.348261 # CPI: Cycles Per Instruction 325system.cpu.cpi_total 4.348261 # CPI: Total CPI of All Threads 326system.cpu.ipc 0.229977 # IPC: Instructions Per Cycle 327system.cpu.ipc_total 0.229977 # IPC: Total IPC of All Threads 328system.cpu.int_regfile_reads 37816 # number of integer regfile reads 329system.cpu.int_regfile_writes 7658 # number of integer regfile writes | 325system.cpu.cpi 4.517391 # CPI: Cycles Per Instruction 326system.cpu.cpi_total 4.517391 # CPI: Total CPI of All Threads 327system.cpu.ipc 0.221367 # IPC: Instructions Per Cycle 328system.cpu.ipc_total 0.221367 # IPC: Total IPC of All Threads 329system.cpu.int_regfile_reads 39570 # number of integer regfile reads 330system.cpu.int_regfile_writes 8020 # number of integer regfile writes |
| 330system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 331system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 331system.cpu.misc_regfile_reads 14992 # number of misc regfile reads | 332system.cpu.misc_regfile_reads 16023 # number of misc regfile reads |
| 332system.cpu.misc_regfile_writes 24 # number of misc regfile writes 333system.cpu.icache.replacements 2 # number of replacements | 333system.cpu.misc_regfile_writes 24 # number of misc regfile writes 334system.cpu.icache.replacements 2 # number of replacements |
| 334system.cpu.icache.tagsinuse 148.855822 # Cycle average of tags in use 335system.cpu.icache.total_refs 1559 # Total number of references to valid blocks. 336system.cpu.icache.sampled_refs 297 # Sample count of references to valid blocks. 337system.cpu.icache.avg_refs 5.249158 # Average number of references to valid blocks. | 335system.cpu.icache.tagsinuse 152.513802 # Cycle average of tags in use 336system.cpu.icache.total_refs 1663 # Total number of references to valid blocks. 337system.cpu.icache.sampled_refs 296 # Sample count of references to valid blocks. 338system.cpu.icache.avg_refs 5.618243 # Average number of references to valid blocks. |
| 338system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 339system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 339system.cpu.icache.occ_blocks::cpu.inst 148.855822 # Average occupied blocks per requestor 340system.cpu.icache.occ_percent::cpu.inst 0.072684 # Average percentage of cache occupancy 341system.cpu.icache.occ_percent::total 0.072684 # Average percentage of cache occupancy 342system.cpu.icache.ReadReq_hits::cpu.inst 1559 # number of ReadReq hits 343system.cpu.icache.ReadReq_hits::total 1559 # number of ReadReq hits 344system.cpu.icache.demand_hits::cpu.inst 1559 # number of demand (read+write) hits 345system.cpu.icache.demand_hits::total 1559 # number of demand (read+write) hits 346system.cpu.icache.overall_hits::cpu.inst 1559 # number of overall hits 347system.cpu.icache.overall_hits::total 1559 # number of overall hits 348system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses 349system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses 350system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses 351system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses 352system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses 353system.cpu.icache.overall_misses::total 360 # number of overall misses 354system.cpu.icache.ReadReq_miss_latency::cpu.inst 12552000 # number of ReadReq miss cycles 355system.cpu.icache.ReadReq_miss_latency::total 12552000 # number of ReadReq miss cycles 356system.cpu.icache.demand_miss_latency::cpu.inst 12552000 # number of demand (read+write) miss cycles 357system.cpu.icache.demand_miss_latency::total 12552000 # number of demand (read+write) miss cycles 358system.cpu.icache.overall_miss_latency::cpu.inst 12552000 # number of overall miss cycles 359system.cpu.icache.overall_miss_latency::total 12552000 # number of overall miss cycles 360system.cpu.icache.ReadReq_accesses::cpu.inst 1919 # number of ReadReq accesses(hits+misses) 361system.cpu.icache.ReadReq_accesses::total 1919 # number of ReadReq accesses(hits+misses) 362system.cpu.icache.demand_accesses::cpu.inst 1919 # number of demand (read+write) accesses 363system.cpu.icache.demand_accesses::total 1919 # number of demand (read+write) accesses 364system.cpu.icache.overall_accesses::cpu.inst 1919 # number of overall (read+write) accesses 365system.cpu.icache.overall_accesses::total 1919 # number of overall (read+write) accesses 366system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.187598 # miss rate for ReadReq accesses 367system.cpu.icache.demand_miss_rate::cpu.inst 0.187598 # miss rate for demand accesses 368system.cpu.icache.overall_miss_rate::cpu.inst 0.187598 # miss rate for overall accesses 369system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667 # average ReadReq miss latency 370system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency 371system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667 # average overall miss latency | 340system.cpu.icache.occ_blocks::cpu.inst 152.513802 # Average occupied blocks per requestor 341system.cpu.icache.occ_percent::cpu.inst 0.074470 # Average percentage of cache occupancy 342system.cpu.icache.occ_percent::total 0.074470 # Average percentage of cache occupancy 343system.cpu.icache.ReadReq_hits::cpu.inst 1663 # number of ReadReq hits 344system.cpu.icache.ReadReq_hits::total 1663 # number of ReadReq hits 345system.cpu.icache.demand_hits::cpu.inst 1663 # number of demand (read+write) hits 346system.cpu.icache.demand_hits::total 1663 # number of demand (read+write) hits 347system.cpu.icache.overall_hits::cpu.inst 1663 # number of overall hits 348system.cpu.icache.overall_hits::total 1663 # number of overall hits 349system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 350system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 351system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 352system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 353system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 354system.cpu.icache.overall_misses::total 365 # number of overall misses 355system.cpu.icache.ReadReq_miss_latency::cpu.inst 12618000 # number of ReadReq miss cycles 356system.cpu.icache.ReadReq_miss_latency::total 12618000 # number of ReadReq miss cycles 357system.cpu.icache.demand_miss_latency::cpu.inst 12618000 # number of demand (read+write) miss cycles 358system.cpu.icache.demand_miss_latency::total 12618000 # number of demand (read+write) miss cycles 359system.cpu.icache.overall_miss_latency::cpu.inst 12618000 # number of overall miss cycles 360system.cpu.icache.overall_miss_latency::total 12618000 # number of overall miss cycles 361system.cpu.icache.ReadReq_accesses::cpu.inst 2028 # number of ReadReq accesses(hits+misses) 362system.cpu.icache.ReadReq_accesses::total 2028 # number of ReadReq accesses(hits+misses) 363system.cpu.icache.demand_accesses::cpu.inst 2028 # number of demand (read+write) accesses 364system.cpu.icache.demand_accesses::total 2028 # number of demand (read+write) accesses 365system.cpu.icache.overall_accesses::cpu.inst 2028 # number of overall (read+write) accesses 366system.cpu.icache.overall_accesses::total 2028 # number of overall (read+write) accesses 367system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.179980 # miss rate for ReadReq accesses 368system.cpu.icache.demand_miss_rate::cpu.inst 0.179980 # miss rate for demand accesses 369system.cpu.icache.overall_miss_rate::cpu.inst 0.179980 # miss rate for overall accesses 370system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34569.863014 # average ReadReq miss latency 371system.cpu.icache.demand_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency 372system.cpu.icache.overall_avg_miss_latency::cpu.inst 34569.863014 # average overall miss latency |
| 372system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 373system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 374system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 376system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 377system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 378system.cpu.icache.fast_writes 0 # number of fast writes performed 379system.cpu.icache.cache_copies 0 # number of cache copies performed | 373system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 374system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 375system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 376system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 377system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 378system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 379system.cpu.icache.fast_writes 0 # number of fast writes performed 380system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 380system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits 381system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 382system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits 383system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits 384system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits 385system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits 386system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 387system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 388system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 389system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 390system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 391system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 392system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9945000 # number of ReadReq MSHR miss cycles 393system.cpu.icache.ReadReq_mshr_miss_latency::total 9945000 # number of ReadReq MSHR miss cycles 394system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9945000 # number of demand (read+write) MSHR miss cycles 395system.cpu.icache.demand_mshr_miss_latency::total 9945000 # number of demand (read+write) MSHR miss cycles 396system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9945000 # number of overall MSHR miss cycles 397system.cpu.icache.overall_mshr_miss_latency::total 9945000 # number of overall MSHR miss cycles 398system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for ReadReq accesses 399system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for demand accesses 400system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.154768 # mshr miss rate for overall accesses 401system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485 # average ReadReq mshr miss latency 402system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency 403system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485 # average overall mshr miss latency | 381system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits 382system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits 383system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits 384system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits 385system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits 386system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits 387system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 388system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 389system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 390system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 391system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 392system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 393system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9837000 # number of ReadReq MSHR miss cycles 394system.cpu.icache.ReadReq_mshr_miss_latency::total 9837000 # number of ReadReq MSHR miss cycles 395system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9837000 # number of demand (read+write) MSHR miss cycles 396system.cpu.icache.demand_mshr_miss_latency::total 9837000 # number of demand (read+write) MSHR miss cycles 397system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9837000 # number of overall MSHR miss cycles 398system.cpu.icache.overall_mshr_miss_latency::total 9837000 # number of overall MSHR miss cycles 399system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for ReadReq accesses 400system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for demand accesses 401system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145957 # mshr miss rate for overall accesses 402system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33233.108108 # average ReadReq mshr miss latency 403system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency 404system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33233.108108 # average overall mshr miss latency |
| 404system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 405system.cpu.dcache.replacements 0 # number of replacements | 405system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 406system.cpu.dcache.replacements 0 # number of replacements |
| 406system.cpu.dcache.tagsinuse 89.085552 # Cycle average of tags in use 407system.cpu.dcache.total_refs 2331 # Total number of references to valid blocks. 408system.cpu.dcache.sampled_refs 154 # Sample count of references to valid blocks. 409system.cpu.dcache.avg_refs 15.136364 # Average number of references to valid blocks. | 407system.cpu.dcache.tagsinuse 87.512831 # Cycle average of tags in use 408system.cpu.dcache.total_refs 2409 # Total number of references to valid blocks. 409system.cpu.dcache.sampled_refs 149 # Sample count of references to valid blocks. 410system.cpu.dcache.avg_refs 16.167785 # Average number of references to valid blocks. |
| 410system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 411system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 411system.cpu.dcache.occ_blocks::cpu.data 89.085552 # Average occupied blocks per requestor 412system.cpu.dcache.occ_percent::cpu.data 0.021749 # Average percentage of cache occupancy 413system.cpu.dcache.occ_percent::total 0.021749 # Average percentage of cache occupancy 414system.cpu.dcache.ReadReq_hits::cpu.data 1702 # number of ReadReq hits 415system.cpu.dcache.ReadReq_hits::total 1702 # number of ReadReq hits | 412system.cpu.dcache.occ_blocks::cpu.data 87.512831 # Average occupied blocks per requestor 413system.cpu.dcache.occ_percent::cpu.data 0.021365 # Average percentage of cache occupancy 414system.cpu.dcache.occ_percent::total 0.021365 # Average percentage of cache occupancy 415system.cpu.dcache.ReadReq_hits::cpu.data 1780 # number of ReadReq hits 416system.cpu.dcache.ReadReq_hits::total 1780 # number of ReadReq hits |
| 416system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits 417system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits 418system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 419system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 420system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 421system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 417system.cpu.dcache.WriteReq_hits::cpu.data 609 # number of WriteReq hits 418system.cpu.dcache.WriteReq_hits::total 609 # number of WriteReq hits 419system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 420system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 421system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 422system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 422system.cpu.dcache.demand_hits::cpu.data 2311 # number of demand (read+write) hits 423system.cpu.dcache.demand_hits::total 2311 # number of demand (read+write) hits 424system.cpu.dcache.overall_hits::cpu.data 2311 # number of overall hits 425system.cpu.dcache.overall_hits::total 2311 # number of overall hits 426system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 427system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses | 423system.cpu.dcache.demand_hits::cpu.data 2389 # number of demand (read+write) hits 424system.cpu.dcache.demand_hits::total 2389 # number of demand (read+write) hits 425system.cpu.dcache.overall_hits::cpu.data 2389 # number of overall hits 426system.cpu.dcache.overall_hits::total 2389 # number of overall hits 427system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses 428system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses |
| 428system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses 429system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses 430system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 431system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 429system.cpu.dcache.WriteReq_misses::cpu.data 304 # number of WriteReq misses 430system.cpu.dcache.WriteReq_misses::total 304 # number of WriteReq misses 431system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 432system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 432system.cpu.dcache.demand_misses::cpu.data 473 # number of demand (read+write) misses 433system.cpu.dcache.demand_misses::total 473 # number of demand (read+write) misses 434system.cpu.dcache.overall_misses::cpu.data 473 # number of overall misses 435system.cpu.dcache.overall_misses::total 473 # number of overall misses 436system.cpu.dcache.ReadReq_miss_latency::cpu.data 5350500 # number of ReadReq miss cycles 437system.cpu.dcache.ReadReq_miss_latency::total 5350500 # number of ReadReq miss cycles 438system.cpu.dcache.WriteReq_miss_latency::cpu.data 10725000 # number of WriteReq miss cycles 439system.cpu.dcache.WriteReq_miss_latency::total 10725000 # number of WriteReq miss cycles | 433system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses 434system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses 435system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses 436system.cpu.dcache.overall_misses::total 474 # number of overall misses 437system.cpu.dcache.ReadReq_miss_latency::cpu.data 5506000 # number of ReadReq miss cycles 438system.cpu.dcache.ReadReq_miss_latency::total 5506000 # number of ReadReq miss cycles 439system.cpu.dcache.WriteReq_miss_latency::cpu.data 10844000 # number of WriteReq miss cycles 440system.cpu.dcache.WriteReq_miss_latency::total 10844000 # number of WriteReq miss cycles |
| 440system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 441system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles | 441system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 76500 # number of LoadLockedReq miss cycles 442system.cpu.dcache.LoadLockedReq_miss_latency::total 76500 # number of LoadLockedReq miss cycles |
| 442system.cpu.dcache.demand_miss_latency::cpu.data 16075500 # number of demand (read+write) miss cycles 443system.cpu.dcache.demand_miss_latency::total 16075500 # number of demand (read+write) miss cycles 444system.cpu.dcache.overall_miss_latency::cpu.data 16075500 # number of overall miss cycles 445system.cpu.dcache.overall_miss_latency::total 16075500 # number of overall miss cycles 446system.cpu.dcache.ReadReq_accesses::cpu.data 1871 # number of ReadReq accesses(hits+misses) 447system.cpu.dcache.ReadReq_accesses::total 1871 # number of ReadReq accesses(hits+misses) | 443system.cpu.dcache.demand_miss_latency::cpu.data 16350000 # number of demand (read+write) miss cycles 444system.cpu.dcache.demand_miss_latency::total 16350000 # number of demand (read+write) miss cycles 445system.cpu.dcache.overall_miss_latency::cpu.data 16350000 # number of overall miss cycles 446system.cpu.dcache.overall_miss_latency::total 16350000 # number of overall miss cycles 447system.cpu.dcache.ReadReq_accesses::cpu.data 1950 # number of ReadReq accesses(hits+misses) 448system.cpu.dcache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) |
| 448system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 449system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 450system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 451system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 452system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 453system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 449system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 450system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 451system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 452system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 453system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 454system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 454system.cpu.dcache.demand_accesses::cpu.data 2784 # number of demand (read+write) accesses 455system.cpu.dcache.demand_accesses::total 2784 # number of demand (read+write) accesses 456system.cpu.dcache.overall_accesses::cpu.data 2784 # number of overall (read+write) accesses 457system.cpu.dcache.overall_accesses::total 2784 # number of overall (read+write) accesses 458system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.090326 # miss rate for ReadReq accesses | 455system.cpu.dcache.demand_accesses::cpu.data 2863 # number of demand (read+write) accesses 456system.cpu.dcache.demand_accesses::total 2863 # number of demand (read+write) accesses 457system.cpu.dcache.overall_accesses::cpu.data 2863 # number of overall (read+write) accesses 458system.cpu.dcache.overall_accesses::total 2863 # number of overall (read+write) accesses 459system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087179 # miss rate for ReadReq accesses |
| 459system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses 460system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses | 460system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.332968 # miss rate for WriteReq accesses 461system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses |
| 461system.cpu.dcache.demand_miss_rate::cpu.data 0.169899 # miss rate for demand accesses 462system.cpu.dcache.overall_miss_rate::cpu.data 0.169899 # miss rate for overall accesses 463system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314 # average ReadReq miss latency 464system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263 # average WriteReq miss latency | 462system.cpu.dcache.demand_miss_rate::cpu.data 0.165561 # miss rate for demand accesses 463system.cpu.dcache.overall_miss_rate::cpu.data 0.165561 # miss rate for overall accesses 464system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32388.235294 # average ReadReq miss latency 465system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35671.052632 # average WriteReq miss latency |
| 465system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency | 466system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 38250 # average LoadLockedReq miss latency |
| 466system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency 467system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928 # average overall miss latency | 467system.cpu.dcache.demand_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency 468system.cpu.dcache.overall_avg_miss_latency::cpu.data 34493.670886 # average overall miss latency |
| 468system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 469system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 470system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 471system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 472system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 473system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 474system.cpu.dcache.fast_writes 0 # number of fast writes performed 475system.cpu.dcache.cache_copies 0 # number of cache copies performed | 469system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 470system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 471system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 472system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 473system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 474system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 475system.cpu.dcache.fast_writes 0 # number of fast writes performed 476system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 476system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 477system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits | 477system.cpu.dcache.ReadReq_mshr_hits::cpu.data 63 # number of ReadReq MSHR hits 478system.cpu.dcache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits |
| 478system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 479system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 480system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 481system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 479system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits 480system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits 481system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 482system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 482system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits 483system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits 484system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits 485system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits 486system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses 487system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses | 483system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits 484system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits 485system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits 486system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits 487system.cpu.dcache.ReadReq_mshr_misses::cpu.data 107 # number of ReadReq MSHR misses 488system.cpu.dcache.ReadReq_mshr_misses::total 107 # number of ReadReq MSHR misses |
| 488system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 489system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses | 489system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 490system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses |
| 490system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses 491system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses 492system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses 493system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses 494system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles 495system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles 496system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles 497system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles 498system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles 499system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles 500system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles 501system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles 502system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses | 491system.cpu.dcache.demand_mshr_misses::cpu.data 149 # number of demand (read+write) MSHR misses 492system.cpu.dcache.demand_mshr_misses::total 149 # number of demand (read+write) MSHR misses 493system.cpu.dcache.overall_mshr_misses::cpu.data 149 # number of overall MSHR misses 494system.cpu.dcache.overall_mshr_misses::total 149 # number of overall MSHR misses 495system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3156500 # number of ReadReq MSHR miss cycles 496system.cpu.dcache.ReadReq_mshr_miss_latency::total 3156500 # number of ReadReq MSHR miss cycles 497system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1501500 # number of WriteReq MSHR miss cycles 498system.cpu.dcache.WriteReq_mshr_miss_latency::total 1501500 # number of WriteReq MSHR miss cycles 499system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4658000 # number of demand (read+write) MSHR miss cycles 500system.cpu.dcache.demand_mshr_miss_latency::total 4658000 # number of demand (read+write) MSHR miss cycles 501system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4658000 # number of overall MSHR miss cycles 502system.cpu.dcache.overall_mshr_miss_latency::total 4658000 # number of overall MSHR miss cycles 503system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054872 # mshr miss rate for ReadReq accesses |
| 503system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses | 504system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses |
| 504system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses 505system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses 506system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency 507system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency 508system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency 509system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency | 505system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for demand accesses 506system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052043 # mshr miss rate for overall accesses 507system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 29500 # average ReadReq mshr miss latency 508system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35750 # average WriteReq mshr miss latency 509system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency 510system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 31261.744966 # average overall mshr miss latency |
| 510system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 511system.cpu.l2cache.replacements 0 # number of replacements | 511system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 512system.cpu.l2cache.replacements 0 # number of replacements |
| 512system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use 513system.cpu.l2cache.total_refs 42 # Total number of references to valid blocks. 514system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks. 515system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks. | 513system.cpu.l2cache.tagsinuse 189.446862 # Cycle average of tags in use 514system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. 515system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. 516system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. |
| 516system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 517system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 517system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor 518system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor 519system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy 520system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy 521system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy 522system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits 523system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits 524system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits 525system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits 526system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits 527system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits 528system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits 529system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits 530system.cpu.l2cache.overall_hits::total 42 # number of overall hits 531system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses 532system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses 533system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses | 518system.cpu.l2cache.occ_blocks::cpu.inst 142.892597 # Average occupied blocks per requestor 519system.cpu.l2cache.occ_blocks::cpu.data 46.554265 # Average occupied blocks per requestor 520system.cpu.l2cache.occ_percent::cpu.inst 0.004361 # Average percentage of cache occupancy 521system.cpu.l2cache.occ_percent::cpu.data 0.001421 # Average percentage of cache occupancy 522system.cpu.l2cache.occ_percent::total 0.005781 # Average percentage of cache occupancy 523system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits 524system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits 525system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits 526system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits 527system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits 528system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits 529system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits 530system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits 531system.cpu.l2cache.overall_hits::total 41 # number of overall hits 532system.cpu.l2cache.ReadReq_misses::cpu.inst 276 # number of ReadReq misses 533system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses 534system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses |
| 534system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 535system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses | 535system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 536system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses |
| 536system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses 537system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses 538system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses 539system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses 540system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses 541system.cpu.l2cache.overall_misses::total 409 # number of overall misses 542system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles 543system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles 544system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles 545system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles 546system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles 547system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles 548system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles 549system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles 550system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles 551system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles 552system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles 553system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) 554system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses) 555system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses) | 537system.cpu.l2cache.demand_misses::cpu.inst 276 # number of demand (read+write) misses 538system.cpu.l2cache.demand_misses::cpu.data 128 # number of demand (read+write) misses 539system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses 540system.cpu.l2cache.overall_misses::cpu.inst 276 # number of overall misses 541system.cpu.l2cache.overall_misses::cpu.data 128 # number of overall misses 542system.cpu.l2cache.overall_misses::total 404 # number of overall misses 543system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9478000 # number of ReadReq miss cycles 544system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2963500 # number of ReadReq miss cycles 545system.cpu.l2cache.ReadReq_miss_latency::total 12441500 # number of ReadReq miss cycles 546system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1446500 # number of ReadExReq miss cycles 547system.cpu.l2cache.ReadExReq_miss_latency::total 1446500 # number of ReadExReq miss cycles 548system.cpu.l2cache.demand_miss_latency::cpu.inst 9478000 # number of demand (read+write) miss cycles 549system.cpu.l2cache.demand_miss_latency::cpu.data 4410000 # number of demand (read+write) miss cycles 550system.cpu.l2cache.demand_miss_latency::total 13888000 # number of demand (read+write) miss cycles 551system.cpu.l2cache.overall_miss_latency::cpu.inst 9478000 # number of overall miss cycles 552system.cpu.l2cache.overall_miss_latency::cpu.data 4410000 # number of overall miss cycles 553system.cpu.l2cache.overall_miss_latency::total 13888000 # number of overall miss cycles 554system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) 555system.cpu.l2cache.ReadReq_accesses::cpu.data 107 # number of ReadReq accesses(hits+misses) 556system.cpu.l2cache.ReadReq_accesses::total 403 # number of ReadReq accesses(hits+misses) |
| 556system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 557system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) | 557system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 558system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) |
| 558system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 559system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses 560system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses 561system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 562system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses 563system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses 564system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses 565system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses | 559system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 560system.cpu.l2cache.demand_accesses::cpu.data 149 # number of demand (read+write) accesses 561system.cpu.l2cache.demand_accesses::total 445 # number of demand (read+write) accesses 562system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses 563system.cpu.l2cache.overall_accesses::cpu.data 149 # number of overall (read+write) accesses 564system.cpu.l2cache.overall_accesses::total 445 # number of overall (read+write) accesses 565system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932432 # miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.803738 # miss rate for ReadReq accesses |
| 566system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses | 567system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 567system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses 568system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses 569system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses 570system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses 571system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency 572system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency 573system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency 574system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency 576system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency | 568system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932432 # miss rate for demand accesses 569system.cpu.l2cache.demand_miss_rate::cpu.data 0.859060 # miss rate for demand accesses 570system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932432 # miss rate for overall accesses 571system.cpu.l2cache.overall_miss_rate::cpu.data 0.859060 # miss rate for overall accesses 572system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34340.579710 # average ReadReq miss latency 573system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34459.302326 # average ReadReq miss latency 574system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34440.476190 # average ReadExReq miss latency 575system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency 576system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency 577system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34340.579710 # average overall miss latency 578system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34453.125000 # average overall miss latency |
| 578system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 584system.cpu.l2cache.fast_writes 0 # number of fast writes performed 585system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 579system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 582system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 584system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked 585system.cpu.l2cache.fast_writes 0 # number of fast writes performed 586system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 586system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 587system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 588system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 589system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 590system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 591system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 592system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses 593system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses 594system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses | 587system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits 588system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits 589system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits 590system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits 591system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits 592system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits 593system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses 594system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses 595system.cpu.l2cache.ReadReq_mshr_misses::total 358 # number of ReadReq MSHR misses |
| 595system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 596system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses | 596system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 597system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses |
| 597system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses 598system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses 599system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses 600system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses 601system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses 602system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses 603system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles 604system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles 605system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles 606system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles 607system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles 608system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles 611system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles 613system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles 614system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses 615system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses | 598system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses 599system.cpu.l2cache.demand_mshr_misses::cpu.data 124 # number of demand (read+write) MSHR misses 600system.cpu.l2cache.demand_mshr_misses::total 400 # number of demand (read+write) MSHR misses 601system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses 602system.cpu.l2cache.overall_mshr_misses::cpu.data 124 # number of overall MSHR misses 603system.cpu.l2cache.overall_mshr_misses::total 400 # number of overall MSHR misses 604system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8590500 # number of ReadReq MSHR miss cycles 605system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2580000 # number of ReadReq MSHR miss cycles 606system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11170500 # number of ReadReq MSHR miss cycles 607system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1315000 # number of ReadExReq MSHR miss cycles 608system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1315000 # number of ReadExReq MSHR miss cycles 609system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8590500 # number of demand (read+write) MSHR miss cycles 610system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3895000 # number of demand (read+write) MSHR miss cycles 611system.cpu.l2cache.demand_mshr_miss_latency::total 12485500 # number of demand (read+write) MSHR miss cycles 612system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8590500 # number of overall MSHR miss cycles 613system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3895000 # number of overall MSHR miss cycles 614system.cpu.l2cache.overall_mshr_miss_latency::total 12485500 # number of overall MSHR miss cycles 615system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for ReadReq accesses 616system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.766355 # mshr miss rate for ReadReq accesses |
| 616system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses | 617system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 617system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses 618system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses 619system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses 620system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses 621system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency 622system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency 623system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency 624system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency 626system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency 627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency | 618system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for demand accesses 619system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for demand accesses 620system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932432 # mshr miss rate for overall accesses 621system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.832215 # mshr miss rate for overall accesses 622system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31125 # average ReadReq mshr miss latency 623system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31463.414634 # average ReadReq mshr miss latency 624system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31309.523810 # average ReadExReq mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 626system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency 627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31125 # average overall mshr miss latency 628system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31411.290323 # average overall mshr miss latency |
| 628system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 629 630---------- End Simulation Statistics ---------- | 629system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 630 631---------- End Simulation Statistics ---------- |