| stats.txt (11860:67dee11badea) | stats.txt (11955:1170d039b31e) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 20302000 # Number of ticks simulated 5final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93691 # Simulator instruction rate (inst/s) 8host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) --- 386 unchanged lines hidden (view full) --- 395system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated 4sim_ticks 20302000 # Number of ticks simulated 5final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 93691 # Simulator instruction rate (inst/s) 8host_op_rate 109699 # Simulator op (including micro ops) rate (op/s) --- 386 unchanged lines hidden (view full) --- 395system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses |
| 403system.cpu.workload.num_syscalls 13 # Number of system calls | 403system.cpu.workload.numSyscalls 13 # Number of system calls |
| 404system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 40605 # number of cpu cycles simulated 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 411system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken --- 768 unchanged lines hidden --- | 404system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 40605 # number of cpu cycles simulated 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 408system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 411system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken --- 768 unchanged lines hidden --- |