| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000020 # Number of seconds simulated |
| 4sim_ticks 20299000 # Number of ticks simulated 5final_tick 20299000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 20302000 # Number of ticks simulated 5final_tick 20302000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 98455 # Simulator instruction rate (inst/s) 8host_op_rate 115276 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 434998330 # Simulator tick rate (ticks/s) 10host_mem_usage 266116 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 10367 # Simulator instruction rate (inst/s) 8host_op_rate 12141 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 45828431 # Simulator tick rate (ticks/s) 10host_mem_usage 248616 # Number of bytes of host memory used 11host_seconds 0.44 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 20system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 444 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8128 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 20system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 127 # Number of read requests responded to by this memory 25system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 26system.physmem.num_reads::total 444 # Number of read requests responded to by this memory |
| 27system.physmem.bw_read::cpu.inst 914330755 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 400413813 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 85127346 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 1399871915 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 914330755 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 914330755 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 914330755 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 400413813 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 85127346 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 1399871915 # Total bandwidth to/from this memory (bytes/s) | 27system.physmem.bw_read::cpu.inst 914195646 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 400354645 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 1399665058 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 914195646 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 914195646 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 914195646 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 400354645 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 1399665058 # Total bandwidth to/from this memory (bytes/s) |
| 37system.physmem.readReqs 445 # Number of read requests accepted 38system.physmem.writeReqs 0 # Number of write requests accepted 39system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 37system.physmem.readReqs 445 # Number of read requests accepted 38system.physmem.writeReqs 0 # Number of write requests accepted 39system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 41system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 44system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 83system.physmem.totGap 20257500 # Total gap between requests | 83system.physmem.totGap 20260500 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 445 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) 90system.physmem.readPktSize::6 445 # Read request sizes (log2) 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 241 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::1 136 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see |
| 102system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 194system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation | 102system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see --- 78 unchanged lines hidden (view full) --- 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 194system.physmem.bytesPerActivate::samples 62 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::mean 435.612903 # Bytes accessed per row activation |
| 196system.physmem.bytesPerActivate::gmean 295.342416 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 353.563376 # Bytes accessed per row activation | 196system.physmem.bytesPerActivate::gmean 295.844737 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 352.802892 # Bytes accessed per row activation |
| 198system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation | 198system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 62 # Bytes accessed per row activation |
| 208system.physmem.totQLat 6110750 # Total ticks spent queuing 209system.physmem.totMemAccLat 14454500 # Total ticks spent from burst creation until serviced by the DRAM | 208system.physmem.totQLat 6124000 # Total ticks spent queuing 209system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM |
| 210system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers | 210system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers |
| 211system.physmem.avgQLat 13732.02 # Average queueing delay per DRAM burst | 211system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst |
| 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 213system.physmem.avgMemAccLat 32482.02 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 1403.02 # Average DRAM read bandwidth in MiByte/s | 213system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 1402.82 # Average DRAM read bandwidth in MiByte/s |
| 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 216system.physmem.avgRdBWSys 1403.02 # Average system read bandwidth in MiByte/s | 216system.physmem.avgRdBWSys 1402.82 # Average system read bandwidth in MiByte/s |
| 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 219system.physmem.busUtil 10.96 # Data bus utilization in percentage 220system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 219system.physmem.busUtil 10.96 # Data bus utilization in percentage 220system.physmem.busUtilRead 10.96 # Data bus utilization in percentage for reads 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 222system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing | 222system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing |
| 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 224system.physmem.readRowHits 373 # Number of row buffer hits during reads 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes 226system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 224system.physmem.readRowHits 373 # Number of row buffer hits during reads 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes 226system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 228system.physmem.avgGap 45522.47 # Average gap between requests | 228system.physmem.avgGap 45529.21 # Average gap between requests |
| 229system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 229system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 349860 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 170775 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 2334780 # Energy for read commands per rank (pJ) 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.physmem_0.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 235system.physmem_0.actBackEnergy 3572760 # Energy for active background per rank (pJ) | 235system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ) |
| 236system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) | 236system.physmem_0.preBackEnergy 28800 # Energy for precharge background per rank (pJ) |
| 237system.physmem_0.actPowerDownEnergy 5648700 # Energy for active power-down per rank (pJ) | 237system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ) |
| 238system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) 239system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 238system.physmem_0.prePowerDownEnergy 960 # Energy for precharge power-down per rank (pJ) 239system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 240system.physmem_0.totalEnergy 13335915 # Total energy per rank (pJ) 241system.physmem_0.averagePower 656.941626 # Core power per rank (mW) 242system.physmem_0.totalIdleTime 12232500 # Total Idle time Per DRAM Rank | 240system.physmem_0.totalEnergy 13337055 # Total energy per rank (pJ) 241system.physmem_0.averagePower 656.916882 # Core power per rank (mW) 242system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank |
| 243system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states 244system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 245system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 246system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states | 243system.physmem_0.memoryStateTime::IDLE 19000 # Time in different power states 244system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 245system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 246system.physmem_0.memoryStateTime::PRE_PDN 2500 # Time in different power states |
| 247system.physmem_0.memoryStateTime::ACT 7376750 # Time in different power states 248system.physmem_0.memoryStateTime::ACT_PDN 12380750 # Time in different power states | 247system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states 248system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states |
| 249system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 250system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) 251system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) 252system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 253system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) | 249system.physmem_1.actEnergy 164220 # Energy for activate commands per rank (pJ) 250system.physmem_1.preEnergy 64515 # Energy for precharge commands per rank (pJ) 251system.physmem_1.readEnergy 842520 # Energy for read commands per rank (pJ) 252system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 253system.physmem_1.refreshEnergy 1229280.000000 # Energy for refresh commands per rank (pJ) |
| 254system.physmem_1.actBackEnergy 1468320 # Energy for active background per rank (pJ) 255system.physmem_1.preBackEnergy 69120 # Energy for precharge background per rank (pJ) 256system.physmem_1.actPowerDownEnergy 7424250 # Energy for active power-down per rank (pJ) 257system.physmem_1.prePowerDownEnergy 237600 # Energy for precharge power-down per rank (pJ) | 254system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ) 255system.physmem_1.preBackEnergy 68640 # Energy for precharge background per rank (pJ) 256system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ) 257system.physmem_1.prePowerDownEnergy 238560 # Energy for precharge power-down per rank (pJ) |
| 258system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) | 258system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) |
| 259system.physmem_1.totalEnergy 11499825 # Total energy per rank (pJ) 260system.physmem_1.averagePower 566.493842 # Core power per rank (mW) 261system.physmem_1.totalIdleTime 16895250 # Total Idle time Per DRAM Rank | 259system.physmem_1.totalEnergy 11500875 # Total energy per rank (pJ) 260system.physmem_1.averagePower 566.475803 # Core power per rank (mW) 261system.physmem_1.totalIdleTime 16880000 # Total Idle time Per DRAM Rank |
| 262system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states 263system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 264system.physmem_1.memoryStateTime::SREF 0 # Time in different power states | 262system.physmem_1.memoryStateTime::IDLE 110000 # Time in different power states 263system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 264system.physmem_1.memoryStateTime::SREF 0 # Time in different power states |
| 265system.physmem_1.memoryStateTime::PRE_PDN 618500 # Time in different power states 266system.physmem_1.memoryStateTime::ACT 2773750 # Time in different power states 267system.physmem_1.memoryStateTime::ACT_PDN 16276750 # Time in different power states 268system.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states 269system.cpu.branchPred.lookups 2441 # Number of BP lookups 270system.cpu.branchPred.condPredicted 1444 # Number of conditional branches predicted | 265system.physmem_1.memoryStateTime::PRE_PDN 620500 # Time in different power states 266system.physmem_1.memoryStateTime::ACT 2792000 # Time in different power states 267system.physmem_1.memoryStateTime::ACT_PDN 16259500 # Time in different power states 268system.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states 269system.cpu.branchPred.lookups 2438 # Number of BP lookups 270system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted |
| 271system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect | 271system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect |
| 272system.cpu.branchPred.BTBLookups 916 # Number of BTB lookups | 272system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups |
| 273system.cpu.branchPred.BTBHits 449 # Number of BTB hits 274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 273system.cpu.branchPred.BTBHits 449 # Number of BTB hits 274system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 275system.cpu.branchPred.BTBHitPct 49.017467 # BTB Hit Percentage | 275system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage |
| 276system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 277system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 278system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 279system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 280system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 281system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. 282system.cpu_clk_domain.clock 500 # Clock period in ticks | 276system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 277system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 278system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 279system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 280system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 281system.cpu.branchPredindirectMispredicted 59 # Number of mispredicted indirect branches. 282system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 283system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 284system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 285system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 286system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 287system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 288system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 289system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 290system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 291system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 305system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 306system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 307system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 308system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 309system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 310system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 311system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 312system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 313system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 314system.cpu.dtb.walker.walks 0 # Table walker walks requested 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses | 314system.cpu.dtb.walker.walks 0 # Table walker walks requested 315system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 316system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 317system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 318system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 319system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 320system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 321system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 335system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 336system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 337system.cpu.dtb.read_accesses 0 # DTB read accesses 338system.cpu.dtb.write_accesses 0 # DTB write accesses 339system.cpu.dtb.inst_accesses 0 # ITB inst accesses 340system.cpu.dtb.hits 0 # DTB hits 341system.cpu.dtb.misses 0 # DTB misses 342system.cpu.dtb.accesses 0 # DTB accesses |
| 343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 343system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 344system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 365system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 344system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 345system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 346system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 347system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 348system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 349system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 350system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 351system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 365system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 366system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 367system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 368system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 369system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 370system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 371system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 372system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 373system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 374system.cpu.itb.walker.walks 0 # Table walker walks requested 375system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 13 # Number of system calls | 374system.cpu.itb.walker.walks 0 # Table walker walks requested 375system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 376system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 377system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 378system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 379system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 380system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 381system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 396system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 397system.cpu.itb.read_accesses 0 # DTB read accesses 398system.cpu.itb.write_accesses 0 # DTB write accesses 399system.cpu.itb.inst_accesses 0 # ITB inst accesses 400system.cpu.itb.hits 0 # DTB hits 401system.cpu.itb.misses 0 # DTB misses 402system.cpu.itb.accesses 0 # DTB accesses 403system.cpu.workload.num_syscalls 13 # Number of system calls |
| 404system.cpu.pwrStateResidencyTicks::ON 20299000 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 40599 # number of cpu cycles simulated | 404system.cpu.pwrStateResidencyTicks::ON 20302000 # Cumulative time (in ticks) in various power states 405system.cpu.numCycles 40605 # number of cpu cycles simulated |
| 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 406system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 407system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 408system.cpu.fetch.icacheStallCycles 6170 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 2441 # Number of branches that fetch encountered | 408system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss 409system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed 410system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered |
| 411system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken | 411system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken |
| 412system.cpu.fetch.Cycles 8322 # Number of cycles fetch has run and was not squashing or blocked | 412system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked |
| 413system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing | 413system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing |
| 414system.cpu.fetch.MiscStallCycles 161 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs | 414system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| 415system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps | 415system.cpu.fetch.PendingTrapStallCycles 286 # Number of stall cycles due to pending traps |
| 416system.cpu.fetch.IcacheWaitRetryStallCycles 434 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched | 416system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR 417system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched |
| 418system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed | 418system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed |
| 419system.cpu.fetch.rateDist::samples 15916 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 0.856748 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.206522 # Number of instructions fetched each cycle (Total) | 419system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total) 420system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total) |
| 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 422system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 423system.cpu.fetch.rateDist::0 9525 59.85% 59.85% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 2508 15.76% 75.60% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 3362 21.12% 100.00% # Number of instructions fetched each cycle (Total) | 423system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total) 424system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total) 425system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total) 426system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total) |
| 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 427system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 428system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 429system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 430system.cpu.fetch.rateDist::total 15916 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.060125 # Number of branch fetches per cycle 432system.cpu.fetch.rate 0.282470 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 5812 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 4409 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 5179 # Number of cycles decode is running | 430system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total) 431system.cpu.fetch.branchRate 0.060042 # Number of branch fetches per cycle 432system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle 433system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle 434system.cpu.decode.BlockedCycles 4410 # Number of cycles decode is blocked 435system.cpu.decode.RunCycles 5174 # Number of cycles decode is running |
| 436system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction | 436system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 437system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing 438system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch 439system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction |
| 440system.cpu.decode.DecodedInsts 10178 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 1683 # Number of squashed instructions handled by decode | 440system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode 441system.cpu.decode.SquashedInsts 1674 # Number of squashed instructions handled by decode |
| 442system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing | 442system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing |
| 443system.cpu.rename.IdleCycles 6925 # Number of cycles rename is idle | 443system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle |
| 444system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst | 444system.cpu.rename.BlockCycles 1165 # Number of cycles rename is blocking 445system.cpu.rename.serializeStallCycles 2515 # count of cycles rename stalled for serializing inst |
| 446system.cpu.rename.RunCycles 4188 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 9100 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 467 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full | 446system.cpu.rename.RunCycles 4185 # Number of cycles rename is running 447system.cpu.rename.UnblockCycles 740 # Number of cycles rename is unblocking 448system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename 449system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename 450system.cpu.rename.ROBFullEvents 25 # Number of times rename has blocked due to ROB full |
| 451system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full | 451system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 452system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full 453system.cpu.rename.SQFullEvents 631 # Number of times rename has blocked due to SQ full |
| 454system.cpu.rename.RenamedOperands 9458 # Number of destination operands rename has renamed 455system.cpu.rename.RenameLookups 41150 # Number of register rename lookups that rename has made 456system.cpu.rename.int_rename_lookups 10006 # Number of integer rename lookups | 454system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed 455system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made 456system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups |
| 457system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 458system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 457system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 458system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 459system.cpu.rename.UndoneMaps 3964 # Number of HB maps that are undone due to squashing | 459system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing |
| 460system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 461system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 460system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 461system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 462system.cpu.rename.skidInsts 330 # count of insts added to the skid buffer 463system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. 464system.cpu.memDep0.insertedStores 1289 # Number of stores inserted to the mem dependence unit. | 462system.cpu.rename.skidInsts 332 # count of insts added to the skid buffer 463system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit. 464system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit. |
| 465system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 466system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 465system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 466system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 467system.cpu.iq.iqInstsAdded 8513 # Number of instructions added to the IQ (excludes non-spec) | 467system.cpu.iq.iqInstsAdded 8508 # Number of instructions added to the IQ (excludes non-spec) |
| 468system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ | 468system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ |
| 469system.cpu.iq.iqInstsIssued 7228 # Number of instructions issued 470system.cpu.iq.iqSquashedInstsIssued 182 # Number of squashed instructions issued 471system.cpu.iq.iqSquashedInstsExamined 3173 # Number of squashed instructions iterated over during squash; mainly for profiling 472system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph | 469system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued 470system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued 471system.cpu.iq.iqSquashedInstsExamined 3168 # Number of squashed instructions iterated over during squash; mainly for profiling 472system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph |
| 473system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed | 473system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed |
| 474system.cpu.iq.issued_per_cycle::samples 15916 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::mean 0.454134 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::stdev 0.844472 # Number of insts issued each cycle | 474system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle |
| 477system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 477system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 478system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::1 1992 12.52% 85.73% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::2 1620 10.18% 95.91% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::3 608 3.82% 99.73% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle | 478system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle 480system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% # Number of insts issued each cycle 481system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle 482system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% # Number of insts issued each cycle |
| 483system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle | 483system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 484system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 485system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 486system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 487system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 488system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 489system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle |
| 490system.cpu.iq.issued_per_cycle::total 15916 # Number of insts issued each cycle | 490system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle |
| 491system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 491system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 492system.cpu.iq.fu_full::IntAlu 416 28.75% 28.75% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntMult 0 0.00% 28.75% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntDiv 0 0.00% 28.75% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.75% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.75% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.75% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatMult 0 0.00% 28.75% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.75% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.75% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.75% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.75% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.75% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.75% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.75% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.75% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.75% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdMult 0 0.00% 28.75% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.75% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdShift 0 0.00% 28.75% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.75% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.75% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.75% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.75% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.75% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.75% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.75% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.75% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.75% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.75% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.75% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemRead 475 32.83% 61.58% # attempts to use FU when none available 524system.cpu.iq.fu_full::MemWrite 539 37.25% 98.83% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.83% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatMemWrite 17 1.17% 100.00% # attempts to use FU when none available | 492system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available 493system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available 494system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available 495system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available 496system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available 497system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available 498system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available 499system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available 500system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available 501system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available 502system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available 511system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available 512system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available 513system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available 514system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available 515system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available 516system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available 517system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available 518system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available 519system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available 520system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available 521system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available 522system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available 523system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available 524system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% # attempts to use FU when none available 525system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% # attempts to use FU when none available 526system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% # attempts to use FU when none available |
| 527system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 528system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 529system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 527system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 528system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 529system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 530system.cpu.iq.FU_type_0::IntAlu 4533 62.71% 62.71% # Type of FU issued 531system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.78% # Type of FU issued 532system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.78% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.78% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.78% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.78% # Type of FU issued 536system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.78% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.78% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.78% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.78% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.78% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.78% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.78% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.78% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.78% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.78% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.78% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.78% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.78% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.78% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.78% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.78% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.78% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.78% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.78% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.78% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.78% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued 561system.cpu.iq.FU_type_0::MemRead 1605 22.21% 85.03% # Type of FU issued 562system.cpu.iq.FU_type_0::MemWrite 1066 14.75% 99.78% # Type of FU issued | 530system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued 531system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued 532system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued 533system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued 534system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued 535system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued 536system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued 537system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued 538system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued 539system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued 540system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued 545system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued 546system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued 547system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued 548system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued 549system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued 550system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued 551system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued 552system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued 553system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued 554system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued 555system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued 556system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued 557system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued 558system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued 559system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued 560system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued 561system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued 562system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued |
| 563system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued 564system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued 565system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 566system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 563system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% # Type of FU issued 564system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% # Type of FU issued 565system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 566system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 567system.cpu.iq.FU_type_0::total 7228 # Type of FU issued 568system.cpu.iq.rate 0.178034 # Inst issue rate 569system.cpu.iq.fu_busy_cnt 1447 # FU busy when requested 570system.cpu.iq.fu_busy_rate 0.200194 # FU busy rate (busy events/executed inst) 571system.cpu.iq.int_inst_queue_reads 31952 # Number of integer instruction queue reads 572system.cpu.iq.int_inst_queue_writes 11715 # Number of integer instruction queue writes 573system.cpu.iq.int_inst_queue_wakeup_accesses 6617 # Number of integer instruction queue wakeup accesses | 567system.cpu.iq.FU_type_0::total 7222 # Type of FU issued 568system.cpu.iq.rate 0.177860 # Inst issue rate 569system.cpu.iq.fu_busy_cnt 1438 # FU busy when requested 570system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst) 571system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads 572system.cpu.iq.int_inst_queue_writes 11705 # Number of integer instruction queue writes 573system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses |
| 574system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads 575system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 576system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 574system.cpu.iq.fp_inst_queue_reads 49 # Number of floating instruction queue reads 575system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 576system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 577system.cpu.iq.int_alu_accesses 8642 # Number of integer alu accesses | 577system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses |
| 578system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses 579system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores 580system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 578system.cpu.iq.fp_alu_accesses 33 # Number of floating point alu accesses 579system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores 580system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 581system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed | 581system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed |
| 582system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 583system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 582system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 583system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 584system.cpu.iew.lsq.thread0.squashedStores 351 # Number of stores squashed | 584system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed |
| 585system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 586system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 587system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 588system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 589system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 590system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing 591system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking 592system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking | 585system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 586system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 587system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 588system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 589system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 590system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing 591system.cpu.iew.iewBlockCycles 345 # Number of cycles IEW is blocking 592system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking |
| 593system.cpu.iew.iewDispatchedInsts 8564 # Number of instructions dispatched to IQ | 593system.cpu.iew.iewDispatchedInsts 8559 # Number of instructions dispatched to IQ |
| 594system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 594system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 595system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions 596system.cpu.iew.iewDispStoreInsts 1289 # Number of dispatched store instructions | 595system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions 596system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions |
| 597system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 598system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 599system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 600system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 601system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly 602system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly 603system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute | 597system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 598system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 599system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 600system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 601system.cpu.iew.predictedTakenIncorrect 60 # Number of branches that were predicted taken incorrectly 602system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly 603system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute |
| 604system.cpu.iew.iewExecutedInsts 6821 # Number of executed instructions 605system.cpu.iew.iewExecLoadInsts 1422 # Number of load instructions executed | 604system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions 605system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed |
| 606system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute 607system.cpu.iew.exec_swp 0 # number of swp insts executed 608system.cpu.iew.exec_nop 13 # number of nop insts executed | 606system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute 607system.cpu.iew.exec_swp 0 # number of swp insts executed 608system.cpu.iew.exec_nop 13 # number of nop insts executed |
| 609system.cpu.iew.exec_refs 2447 # number of memory reference insts executed 610system.cpu.iew.exec_branches 1298 # Number of branches executed 611system.cpu.iew.exec_stores 1025 # Number of stores executed 612system.cpu.iew.exec_rate 0.168009 # Inst execution rate 613system.cpu.iew.wb_sent 6677 # cumulative count of insts sent to commit 614system.cpu.iew.wb_count 6633 # cumulative count of insts written-back | 609system.cpu.iew.exec_refs 2442 # number of memory reference insts executed 610system.cpu.iew.exec_branches 1297 # Number of branches executed 611system.cpu.iew.exec_stores 1024 # Number of stores executed 612system.cpu.iew.exec_rate 0.167836 # Inst execution rate 613system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit 614system.cpu.iew.wb_count 6631 # cumulative count of insts written-back |
| 615system.cpu.iew.wb_producers 2981 # num instructions producing a value | 615system.cpu.iew.wb_producers 2981 # num instructions producing a value |
| 616system.cpu.iew.wb_consumers 5419 # num instructions consuming a value 617system.cpu.iew.wb_rate 0.163378 # insts written-back per cycle 618system.cpu.iew.wb_fanout 0.550101 # average fanout of values written-back 619system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit | 616system.cpu.iew.wb_consumers 5426 # num instructions consuming a value 617system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle 618system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back 619system.cpu.commit.commitSquashedInsts 2701 # The number of squashed insts skipped by commit |
| 620system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 621system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted | 620system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 621system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted |
| 622system.cpu.commit.committed_per_cycle::samples 15349 # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::mean 0.350381 # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::stdev 0.988718 # Number of insts commited each cycle | 622system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle 623system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle 624system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle |
| 625system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 625system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 626system.cpu.commit.committed_per_cycle::0 12681 82.62% 82.62% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::1 1407 9.17% 91.78% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::2 599 3.90% 95.69% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::3 298 1.94% 97.63% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::4 170 1.11% 98.74% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::5 79 0.51% 99.25% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::6 44 0.29% 99.54% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle | 626system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle 627system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle 628system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% # Number of insts commited each cycle 629system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% # Number of insts commited each cycle 630system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle 631system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% # Number of insts commited each cycle 632system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle 633system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% # Number of insts commited each cycle 634system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle |
| 635system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 635system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 636system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 637system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 638system.cpu.commit.committed_per_cycle::total 15349 # Number of insts commited each cycle | 638system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle |
| 639system.cpu.commit.committedInsts 4592 # Number of instructions committed 640system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 641system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 642system.cpu.commit.refs 1965 # Number of memory references committed 643system.cpu.commit.loads 1027 # Number of loads committed 644system.cpu.commit.membars 12 # Number of memory barriers committed 645system.cpu.commit.branches 1008 # Number of branches committed 646system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 680system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 681system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 682system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction 683system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 684system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 5378 # Class of committed instruction | 639system.cpu.commit.committedInsts 4592 # Number of instructions committed 640system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 641system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 642system.cpu.commit.refs 1965 # Number of memory references committed 643system.cpu.commit.loads 1027 # Number of loads committed 644system.cpu.commit.membars 12 # Number of memory barriers committed 645system.cpu.commit.branches 1008 # Number of branches committed 646system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 33 unchanged lines hidden (view full) --- 680system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 681system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 682system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% # Class of committed instruction 683system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% # Class of committed instruction 684system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% # Class of committed instruction 685system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 686system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 687system.cpu.commit.op_class_0::total 5378 # Class of committed instruction |
| 688system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached 689system.cpu.rob.rob_reads 23233 # The number of ROB reads 690system.cpu.rob.rob_writes 16740 # The number of ROB writes 691system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 24683 # Total number of cycles that the CPU has spent unscheduled due to idling | 688system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached 689system.cpu.rob.rob_reads 23226 # The number of ROB reads 690system.cpu.rob.rob_writes 16730 # The number of ROB writes 691system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 692system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 693system.cpu.committedInsts 4592 # Number of Instructions Simulated 694system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated | 693system.cpu.committedInsts 4592 # Number of Instructions Simulated 694system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated |
| 695system.cpu.cpi 8.841246 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 8.841246 # CPI: Total CPI of All Threads 697system.cpu.ipc 0.113106 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 0.113106 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 6772 # number of integer regfile reads 700system.cpu.int_regfile_writes 3788 # number of integer regfile writes | 695system.cpu.cpi 8.842552 # CPI: Cycles Per Instruction 696system.cpu.cpi_total 8.842552 # CPI: Total CPI of All Threads 697system.cpu.ipc 0.113090 # IPC: Instructions Per Cycle 698system.cpu.ipc_total 0.113090 # IPC: Total IPC of All Threads 699system.cpu.int_regfile_reads 6765 # number of integer regfile reads 700system.cpu.int_regfile_writes 3787 # number of integer regfile writes |
| 701system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 701system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 702system.cpu.cc_regfile_reads 24220 # number of cc regfile reads | 702system.cpu.cc_regfile_reads 24202 # number of cc regfile reads |
| 703system.cpu.cc_regfile_writes 2924 # number of cc regfile writes | 703system.cpu.cc_regfile_writes 2924 # number of cc regfile writes |
| 704system.cpu.misc_regfile_reads 2559 # number of misc regfile reads | 704system.cpu.misc_regfile_reads 2558 # number of misc regfile reads |
| 705system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 705system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 706system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 706system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 707system.cpu.dcache.tags.replacements 1 # number of replacements | 707system.cpu.dcache.tags.replacements 1 # number of replacements |
| 708system.cpu.dcache.tags.tagsinuse 84.063183 # Cycle average of tags in use 709system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. | 708system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use 709system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks. |
| 710system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. | 710system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. |
| 711system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. | 711system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks. |
| 712system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 712system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 713system.cpu.dcache.tags.occ_blocks::cpu.data 84.063183 # Average occupied blocks per requestor 714system.cpu.dcache.tags.occ_percent::cpu.data 0.164186 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_percent::total 0.164186 # Average percentage of cache occupancy | 713system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor 714system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy 715system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy |
| 716system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 719system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id | 716system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 717system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id 718system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id 719system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id |
| 720system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses 721system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses 722system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states 723system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits 724system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits | 720system.cpu.dcache.tags.tag_accesses 4715 # Number of tag accesses 721system.cpu.dcache.tags.data_accesses 4715 # Number of data accesses 722system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states 723system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits 724system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits |
| 725system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 726system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 725system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 726system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 727system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 728system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 729system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 730system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 731system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits 732system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits 733system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits 734system.cpu.dcache.overall_hits::total 1910 # number of overall hits | 731system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits 732system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits 733system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits 734system.cpu.dcache.overall_hits::total 1906 # number of overall hits |
| 735system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 736system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 737system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 739system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 740system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 741system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses 742system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses 743system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses 744system.cpu.dcache.overall_misses::total 358 # number of overall misses | 735system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 736system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 737system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 738system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 739system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 740system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 741system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses 742system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses 743system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses 744system.cpu.dcache.overall_misses::total 358 # number of overall misses |
| 745system.cpu.dcache.ReadReq_miss_latency::cpu.data 12032500 # number of ReadReq miss cycles 746system.cpu.dcache.ReadReq_miss_latency::total 12032500 # number of ReadReq miss cycles 747system.cpu.dcache.WriteReq_miss_latency::cpu.data 8019500 # number of WriteReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::total 8019500 # number of WriteReq miss cycles | 745system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles 746system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles 747system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 # number of WriteReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::total 8016500 # number of WriteReq miss cycles |
| 749system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles | 749system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 # number of LoadLockedReq miss cycles 750system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 # number of LoadLockedReq miss cycles |
| 751system.cpu.dcache.demand_miss_latency::cpu.data 20052000 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 20052000 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 20052000 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 20052000 # number of overall miss cycles 755system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) | 751system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles 752system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles 753system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles 754system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles 755system.cpu.dcache.ReadReq_accesses::cpu.data 1351 # number of ReadReq accesses(hits+misses) 756system.cpu.dcache.ReadReq_accesses::total 1351 # number of ReadReq accesses(hits+misses) |
| 757system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 760system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 762system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 757system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 758system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 759system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 760system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 761system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 762system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 763system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses 764system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses 765system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses 766system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses 767system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses 768system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses | 763system.cpu.dcache.demand_accesses::cpu.data 2264 # number of demand (read+write) accesses 764system.cpu.dcache.demand_accesses::total 2264 # number of demand (read+write) accesses 765system.cpu.dcache.overall_accesses::cpu.data 2264 # number of overall (read+write) accesses 766system.cpu.dcache.overall_accesses::total 2264 # number of overall (read+write) accesses 767system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses 768system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses |
| 769system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 770system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses | 769system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 770system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 771system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 772system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses |
| 773system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses 774system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses 775system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses 776system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72050.898204 # average ReadReq miss latency 778system.cpu.dcache.ReadReq_avg_miss_latency::total 72050.898204 # average ReadReq miss latency 779system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41986.910995 # average WriteReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::total 41986.910995 # average WriteReq miss latency | 773system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses 774system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses 775system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses 776system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses 777system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency 778system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency 779system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 # average WriteReq miss latency 780system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 # average WriteReq miss latency |
| 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency | 781system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 # average LoadLockedReq miss latency 782system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 # average LoadLockedReq miss latency |
| 783system.cpu.dcache.demand_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency 784system.cpu.dcache.demand_avg_miss_latency::total 56011.173184 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::cpu.data 56011.173184 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::total 56011.173184 # average overall miss latency | 783system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency 784system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency 785system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency 786system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency |
| 787system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked 793system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 794system.cpu.dcache.writebacks::total 1 # number of writebacks --- 10 unchanged lines hidden (view full) --- 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 809system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 810system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 811system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 812system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses | 787system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 788system.cpu.dcache.blocked_cycles::no_targets 853 # number of cycles access was blocked 789system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 790system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 791system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 792system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 # average number of cycles each access was blocked 793system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 794system.cpu.dcache.writebacks::total 1 # number of writebacks --- 10 unchanged lines hidden (view full) --- 805system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 806system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 807system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 808system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 809system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 810system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 811system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 812system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses |
| 813system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7984500 # number of ReadReq MSHR miss cycles 814system.cpu.dcache.ReadReq_mshr_miss_latency::total 7984500 # number of ReadReq MSHR miss cycles 815system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2595500 # number of WriteReq MSHR miss cycles 816system.cpu.dcache.WriteReq_mshr_miss_latency::total 2595500 # number of WriteReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10580000 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 10580000 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10580000 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 10580000 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses | 813system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles 814system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles 815system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2594500 # number of WriteReq MSHR miss cycles 816system.cpu.dcache.WriteReq_mshr_miss_latency::total 2594500 # number of WriteReq MSHR miss cycles 817system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles 818system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles 819system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles 820system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles 821system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076240 # mshr miss rate for ReadReq accesses 822system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076240 # mshr miss rate for ReadReq accesses |
| 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses | 823system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 824system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses |
| 825system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses 826system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses 827system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses 828system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses 829system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77519.417476 # average ReadReq mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77519.417476 # average ReadReq mshr miss latency 831system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63304.878049 # average WriteReq mshr miss latency 832system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63304.878049 # average WriteReq mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency 834system.cpu.dcache.demand_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73472.222222 # average overall mshr miss latency 836system.cpu.dcache.overall_avg_mshr_miss_latency::total 73472.222222 # average overall mshr miss latency 837system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 825system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for demand accesses 826system.cpu.dcache.demand_mshr_miss_rate::total 0.063604 # mshr miss rate for demand accesses 827system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063604 # mshr miss rate for overall accesses 828system.cpu.dcache.overall_mshr_miss_rate::total 0.063604 # mshr miss rate for overall accesses 829system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency 830system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency 831system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 63280.487805 # average WriteReq mshr miss latency 832system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 63280.487805 # average WriteReq mshr miss latency 833system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency 834system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency 835system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency 836system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency 837system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 838system.cpu.icache.tags.replacements 44 # number of replacements | 838system.cpu.icache.tags.replacements 44 # number of replacements |
| 839system.cpu.icache.tags.tagsinuse 137.515573 # Cycle average of tags in use 840system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. | 839system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use 840system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks. |
| 841system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. | 841system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. |
| 842system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. | 842system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks. |
| 843system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 843system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 844system.cpu.icache.tags.occ_blocks::cpu.inst 137.515573 # Average occupied blocks per requestor 845system.cpu.icache.tags.occ_percent::cpu.inst 0.268585 # Average percentage of cache occupancy 846system.cpu.icache.tags.occ_percent::total 0.268585 # Average percentage of cache occupancy | 844system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor 845system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy 846system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy |
| 847system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id 848system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id 849system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 850system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id | 847system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id 848system.cpu.icache.tags.age_task_id_blocks_1024::0 145 # Occupied blocks per task id 849system.cpu.icache.tags.age_task_id_blocks_1024::1 110 # Occupied blocks per task id 850system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id |
| 851system.cpu.icache.tags.tag_accesses 8109 # Number of tag accesses 852system.cpu.icache.tags.data_accesses 8109 # Number of data accesses 853system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states 854system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits 855system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits 856system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits 857system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits 858system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits 859system.cpu.icache.overall_hits::total 3540 # number of overall hits | 851system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses 852system.cpu.icache.tags.data_accesses 8101 # Number of data accesses 853system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states 854system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits 855system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits 856system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits 857system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits 858system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits 859system.cpu.icache.overall_hits::total 3536 # number of overall hits |
| 860system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 861system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 862system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 863system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 864system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 865system.cpu.icache.overall_misses::total 365 # number of overall misses | 860system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses 861system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses 862system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses 863system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses 864system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses 865system.cpu.icache.overall_misses::total 365 # number of overall misses |
| 866system.cpu.icache.ReadReq_miss_latency::cpu.inst 25051490 # number of ReadReq miss cycles 867system.cpu.icache.ReadReq_miss_latency::total 25051490 # number of ReadReq miss cycles 868system.cpu.icache.demand_miss_latency::cpu.inst 25051490 # number of demand (read+write) miss cycles 869system.cpu.icache.demand_miss_latency::total 25051490 # number of demand (read+write) miss cycles 870system.cpu.icache.overall_miss_latency::cpu.inst 25051490 # number of overall miss cycles 871system.cpu.icache.overall_miss_latency::total 25051490 # number of overall miss cycles 872system.cpu.icache.ReadReq_accesses::cpu.inst 3905 # number of ReadReq accesses(hits+misses) 873system.cpu.icache.ReadReq_accesses::total 3905 # number of ReadReq accesses(hits+misses) 874system.cpu.icache.demand_accesses::cpu.inst 3905 # number of demand (read+write) accesses 875system.cpu.icache.demand_accesses::total 3905 # number of demand (read+write) accesses 876system.cpu.icache.overall_accesses::cpu.inst 3905 # number of overall (read+write) accesses 877system.cpu.icache.overall_accesses::total 3905 # number of overall (read+write) accesses 878system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093470 # miss rate for ReadReq accesses 879system.cpu.icache.ReadReq_miss_rate::total 0.093470 # miss rate for ReadReq accesses 880system.cpu.icache.demand_miss_rate::cpu.inst 0.093470 # miss rate for demand accesses 881system.cpu.icache.demand_miss_rate::total 0.093470 # miss rate for demand accesses 882system.cpu.icache.overall_miss_rate::cpu.inst 0.093470 # miss rate for overall accesses 883system.cpu.icache.overall_miss_rate::total 0.093470 # miss rate for overall accesses 884system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68634.219178 # average ReadReq miss latency 885system.cpu.icache.ReadReq_avg_miss_latency::total 68634.219178 # average ReadReq miss latency 886system.cpu.icache.demand_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency 887system.cpu.icache.demand_avg_miss_latency::total 68634.219178 # average overall miss latency 888system.cpu.icache.overall_avg_miss_latency::cpu.inst 68634.219178 # average overall miss latency 889system.cpu.icache.overall_avg_miss_latency::total 68634.219178 # average overall miss latency 890system.cpu.icache.blocked_cycles::no_mshrs 9850 # number of cycles access was blocked | 866system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles 867system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles 868system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles 869system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles 870system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles 871system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles 872system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) 873system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) 874system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses 875system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses 876system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses 877system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses 878system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses 879system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses 880system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses 881system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses 882system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses 883system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses 884system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency 885system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency 886system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency 887system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency 888system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency 889system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency 890system.cpu.icache.blocked_cycles::no_mshrs 9833 # number of cycles access was blocked |
| 891system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked | 891system.cpu.icache.blocked_cycles::no_targets 47 # number of cycles access was blocked |
| 892system.cpu.icache.blocked::no_mshrs 96 # number of cycles access was blocked | 892system.cpu.icache.blocked::no_mshrs 97 # number of cycles access was blocked |
| 893system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked | 893system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 894system.cpu.icache.avg_blocked_cycles::no_mshrs 102.604167 # average number of cycles each access was blocked | 894system.cpu.icache.avg_blocked_cycles::no_mshrs 101.371134 # average number of cycles each access was blocked |
| 895system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked 896system.cpu.icache.writebacks::writebacks 44 # number of writebacks 897system.cpu.icache.writebacks::total 44 # number of writebacks 898system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits 899system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 900system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits 901system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits 902system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits 903system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits 904system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses 905system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses 906system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses 907system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses 908system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses 909system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses | 895system.cpu.icache.avg_blocked_cycles::no_targets 47 # average number of cycles each access was blocked 896system.cpu.icache.writebacks::writebacks 44 # number of writebacks 897system.cpu.icache.writebacks::total 44 # number of writebacks 898system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits 899system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits 900system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits 901system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits 902system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits 903system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits 904system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses 905system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses 906system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses 907system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses 908system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses 909system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses |
| 910system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22011990 # number of ReadReq MSHR miss cycles 911system.cpu.icache.ReadReq_mshr_miss_latency::total 22011990 # number of ReadReq MSHR miss cycles 912system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22011990 # number of demand (read+write) MSHR miss cycles 913system.cpu.icache.demand_mshr_miss_latency::total 22011990 # number of demand (read+write) MSHR miss cycles 914system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22011990 # number of overall MSHR miss cycles 915system.cpu.icache.overall_mshr_miss_latency::total 22011990 # number of overall MSHR miss cycles 916system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for ReadReq accesses 917system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076569 # mshr miss rate for ReadReq accesses 918system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for demand accesses 919system.cpu.icache.demand_mshr_miss_rate::total 0.076569 # mshr miss rate for demand accesses 920system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076569 # mshr miss rate for overall accesses 921system.cpu.icache.overall_mshr_miss_rate::total 0.076569 # mshr miss rate for overall accesses 922system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73618.695652 # average ReadReq mshr miss latency 923system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73618.695652 # average ReadReq mshr miss latency 924system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency 925system.cpu.icache.demand_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency 926system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73618.695652 # average overall mshr miss latency 927system.cpu.icache.overall_avg_mshr_miss_latency::total 73618.695652 # average overall mshr miss latency 928system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 910system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles 911system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles 912system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles 913system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles 914system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles 915system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles 916system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses 917system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses 918system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses 919system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses 920system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 921system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 922system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency 923system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency 924system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency 925system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency 926system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency 927system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency 928system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 929system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 930system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 931system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 932system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 933system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 934system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 929system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 930system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 931system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 932system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 933system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 934system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 935system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 935system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 936system.cpu.l2cache.tags.replacements 0 # number of replacements | 936system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 937system.cpu.l2cache.tags.tagsinuse 17.353048 # Cycle average of tags in use | 937system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use |
| 938system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 939system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. 940system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. 941system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 938system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 939system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. 940system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. 941system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 942system.cpu.l2cache.tags.occ_blocks::writebacks 9.225603 # Average occupied blocks per requestor 943system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.127445 # Average occupied blocks per requestor | 942system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor 943system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor |
| 944system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy 945system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id 948system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 953system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 # Percentage of cache occupancy per task id 954system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id 955system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses 956system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses | 944system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy 945system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000496 # Average percentage of cache occupancy 946system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy 947system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id 948system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id 949system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 950system.cpu.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 951system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 952system.cpu.l2cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 953system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 # Percentage of cache occupancy per task id 954system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id 955system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses 956system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses |
| 957system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 957system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 958system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 959system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 960system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 961system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 962system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 963system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits 964system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.data 11 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 974system.cpu.l2cache.ReadSharedReq_misses::cpu.data 103 # number of ReadSharedReq misses 975system.cpu.l2cache.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses 976system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses 977system.cpu.l2cache.demand_misses::cpu.data 133 # number of demand (read+write) misses 978system.cpu.l2cache.demand_misses::total 424 # number of demand (read+write) misses 979system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses 980system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses 981system.cpu.l2cache.overall_misses::total 424 # number of overall misses | 958system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 959system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 960system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 961system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 962system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 963system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits 964system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits 965system.cpu.l2cache.demand_hits::cpu.data 11 # number of demand (read+write) hits --- 8 unchanged lines hidden (view full) --- 974system.cpu.l2cache.ReadSharedReq_misses::cpu.data 103 # number of ReadSharedReq misses 975system.cpu.l2cache.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses 976system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses 977system.cpu.l2cache.demand_misses::cpu.data 133 # number of demand (read+write) misses 978system.cpu.l2cache.demand_misses::total 424 # number of demand (read+write) misses 979system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses 980system.cpu.l2cache.overall_misses::cpu.data 133 # number of overall misses 981system.cpu.l2cache.overall_misses::total 424 # number of overall misses |
| 982system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2461000 # number of ReadExReq miss cycles 983system.cpu.l2cache.ReadExReq_miss_latency::total 2461000 # number of ReadExReq miss cycles 984system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21652500 # number of ReadCleanReq miss cycles 985system.cpu.l2cache.ReadCleanReq_miss_latency::total 21652500 # number of ReadCleanReq miss cycles 986system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7825000 # number of ReadSharedReq miss cycles 987system.cpu.l2cache.ReadSharedReq_miss_latency::total 7825000 # number of ReadSharedReq miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.inst 21652500 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.data 10286000 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::total 31938500 # number of demand (read+write) miss cycles 991system.cpu.l2cache.overall_miss_latency::cpu.inst 21652500 # number of overall miss cycles 992system.cpu.l2cache.overall_miss_latency::cpu.data 10286000 # number of overall miss cycles 993system.cpu.l2cache.overall_miss_latency::total 31938500 # number of overall miss cycles | 982system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2460000 # number of ReadExReq miss cycles 983system.cpu.l2cache.ReadExReq_miss_latency::total 2460000 # number of ReadExReq miss cycles 984system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles 985system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles 986system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles 987system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles 988system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles 989system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles 990system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles 991system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles 992system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles 993system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles |
| 994system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 995system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 996system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 997system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 998system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) 999system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) 1000system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 1001system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1012system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1013system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 1014system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses 1015system.cpu.l2cache.demand_miss_rate::cpu.data 0.923611 # miss rate for demand accesses 1016system.cpu.l2cache.demand_miss_rate::total 0.957111 # miss rate for demand accesses 1017system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses 1018system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses 1019system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses | 994system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 995system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 996system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 997system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 998system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) 999system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) 1000system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 1001system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 1012system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 1013system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 1014system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses 1015system.cpu.l2cache.demand_miss_rate::cpu.data 0.923611 # miss rate for demand accesses 1016system.cpu.l2cache.demand_miss_rate::total 0.957111 # miss rate for demand accesses 1017system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses 1018system.cpu.l2cache.overall_miss_rate::cpu.data 0.923611 # miss rate for overall accesses 1019system.cpu.l2cache.overall_miss_rate::total 0.957111 # miss rate for overall accesses |
| 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82033.333333 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82033.333333 # average ReadExReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74407.216495 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74407.216495 # average ReadCleanReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 75970.873786 # average ReadSharedReq miss latency 1025system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 75970.873786 # average ReadSharedReq miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::total 75326.650943 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74407.216495 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77338.345865 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::total 75326.650943 # average overall miss latency | 1020system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82000 # average ReadExReq miss latency 1021system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82000 # average ReadExReq miss latency 1022system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency 1023system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency 1024system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency 1025system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency 1026system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency 1027system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency 1028system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency 1029system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency 1030system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency 1031system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency |
| 1032system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1034system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1035system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1036system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1037system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1038system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1039system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 17 unchanged lines hidden (view full) --- 1057system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses 1058system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses 1061system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses 1062system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses 1063system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles 1064system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles | 1032system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1033system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1034system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1035system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1036system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1037system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1038system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1039system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits --- 17 unchanged lines hidden (view full) --- 1057system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses 1058system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses 1059system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses 1060system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses 1061system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses 1062system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses 1063system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of HardPFReq MSHR miss cycles 1064system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1766926 # number of HardPFReq MSHR miss cycles |
| 1065system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2281000 # number of ReadExReq MSHR miss cycles 1066system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2281000 # number of ReadExReq MSHR miss cycles 1067system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19850000 # number of ReadCleanReq MSHR miss cycles 1068system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19850000 # number of ReadCleanReq MSHR miss cycles 1069system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6909500 # number of ReadSharedReq MSHR miss cycles 1070system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6909500 # number of ReadSharedReq MSHR miss cycles 1071system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19850000 # number of demand (read+write) MSHR miss cycles 1072system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9190500 # number of demand (read+write) MSHR miss cycles 1073system.cpu.l2cache.demand_mshr_miss_latency::total 29040500 # number of demand (read+write) MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19850000 # number of overall MSHR miss cycles 1075system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9190500 # number of overall MSHR miss cycles | 1065system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2280000 # number of ReadExReq MSHR miss cycles 1066system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2280000 # number of ReadExReq MSHR miss cycles 1067system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles 1068system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles 1069system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles 1070system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles 1071system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles 1072system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles 1073system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles 1074system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles 1075system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles |
| 1076system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles | 1076system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1766926 # number of overall MSHR miss cycles |
| 1077system.cpu.l2cache.overall_mshr_miss_latency::total 30807426 # number of overall MSHR miss cycles | 1077system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles |
| 1078system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1079system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1080system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1081system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses 1085system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses 1086system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses 1087system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses 1088system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses 1089system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses 1090system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses 1091system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1092system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses 1093system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency 1094system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency | 1078system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1079system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1080system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1081system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1082system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses 1083system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses 1084system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses 1085system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses 1086system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses 1087system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses 1088system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses 1089system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses 1090system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses 1091system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1092system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses 1093system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average HardPFReq mshr miss latency 1094system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33338.226415 # average HardPFReq mshr miss latency |
| 1095system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76033.333333 # average ReadExReq mshr miss latency 1096system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76033.333333 # average ReadExReq mshr miss latency 1097system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68448.275862 # average ReadCleanReq mshr miss latency 1098system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68448.275862 # average ReadCleanReq mshr miss latency 1099system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70505.102041 # average ReadSharedReq mshr miss latency 1100system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70505.102041 # average ReadSharedReq mshr miss latency 1101system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency 1102system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69474.880383 # average overall mshr miss latency 1104system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68448.275862 # average overall mshr miss latency 1105system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71800.781250 # average overall mshr miss latency | 1095system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 76000 # average ReadExReq mshr miss latency 1096system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 76000 # average ReadExReq mshr miss latency 1097system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency 1098system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency 1099system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency 1100system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency 1101system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency 1102system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency 1103system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency 1104system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency 1105system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency |
| 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency | 1106system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33338.226415 # average overall mshr miss latency |
| 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65408.547771 # average overall mshr miss latency | 1107system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency |
| 1108system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1109system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1110system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1111system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. 1112system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1113system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1108system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1109system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1110system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1111system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. 1112system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1113system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1114system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 1114system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 1115system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 1122system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) --- 22 unchanged lines hidden (view full) --- 1145system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1146system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 1147system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 1148system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1149system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1150system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1151system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1152system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 1115system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1116system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution 1117system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1118system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1119system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1120system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1121system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 1122system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) --- 22 unchanged lines hidden (view full) --- 1145system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1146system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 1147system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 1148system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1149system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1150system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1151system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1152system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1153system.membus.pwrStateResidencyTicks::UNDEFINED 20299000 # Cumulative time (in ticks) in various power states | 1153system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 # Cumulative time (in ticks) in various power states |
| 1154system.membus.trans_dist::ReadResp 414 # Transaction distribution 1155system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1156system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1157system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution 1158system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) 1159system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) 1160system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 1161system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1166system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram 1169system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1170system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1171system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1172system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1173system.membus.snoop_fanout::total 445 # Request fanout histogram | 1154system.membus.trans_dist::ReadResp 414 # Transaction distribution 1155system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1156system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1157system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution 1158system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) 1159system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) 1160system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 1161system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) --- 4 unchanged lines hidden (view full) --- 1166system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1167system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1168system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram 1169system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1170system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1171system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1172system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1173system.membus.snoop_fanout::total 445 # Request fanout histogram |
| 1174system.membus.reqLayer0.occupancy 564444 # Layer occupancy (ticks) 1175system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 1176system.membus.respLayer1.occupancy 2334750 # Layer occupancy (ticks) | 1174system.membus.reqLayer0.occupancy 554444 # Layer occupancy (ticks) 1175system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 1176system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks) |
| 1177system.membus.respLayer1.utilization 11.5 # Layer utilization (%) 1178 1179---------- End Simulation Statistics ---------- | 1177system.membus.respLayer1.utilization 11.5 # Layer utilization (%) 1178 1179---------- End Simulation Statistics ---------- |