| stats.txt (11589:af2f7fef4875) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated |
| 4sim_ticks 18821000 # Number of ticks simulated 5final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 19046000 # Number of ticks simulated 5final_tick 19046000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 81076 # Simulator instruction rate (inst/s) 8host_op_rate 94934 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 332169191 # Simulator tick rate (ticks/s) 10host_mem_usage 262700 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 51970 # Simulator instruction rate (inst/s) 8host_op_rate 60857 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 215490046 # Simulator tick rate (ticks/s) 10host_mem_usage 266056 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory |
| 18system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory | 18system.physmem.bytes_read::cpu.data 8192 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory | 19system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory |
| 20system.physmem.bytes_read::total 28352 # Number of bytes read from this memory | 20system.physmem.bytes_read::total 28480 # Number of bytes read from this memory |
| 21system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory | 21system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory |
| 24system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory | 24system.physmem.num_reads::cpu.data 128 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory | 25system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory |
| 26system.physmem.num_reads::total 443 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 986132512 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 428457574 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 91812337 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 1506402423 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 986132512 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 986132512 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 986132512 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 428457574 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 91812337 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 1506402423 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 443 # Number of read requests accepted | 26system.physmem.num_reads::total 445 # Number of read requests responded to by this memory 27system.physmem.bw_read::cpu.inst 974482831 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.data 430116560 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::cpu.l2cache.prefetcher 90727712 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_read::total 1495327103 # Total read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::cpu.inst 974482831 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_inst_read::total 974482831 # Instruction read bandwidth from this memory (bytes/s) 33system.physmem.bw_total::cpu.inst 974482831 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.data 430116560 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::cpu.l2cache.prefetcher 90727712 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.bw_total::total 1495327103 # Total bandwidth to/from this memory (bytes/s) 37system.physmem.readReqs 445 # Number of read requests accepted |
| 38system.physmem.writeReqs 0 # Number of write requests accepted | 38system.physmem.writeReqs 0 # Number of write requests accepted |
| 39system.physmem.readBursts 443 # Number of DRAM read bursts, including those serviced by the write queue | 39system.physmem.readBursts 445 # Number of DRAM read bursts, including those serviced by the write queue |
| 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 40system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 41system.physmem.bytesReadDRAM 28352 # Total number of bytes read from DRAM | 41system.physmem.bytesReadDRAM 28480 # Total number of bytes read from DRAM |
| 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 42system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 43system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 44system.physmem.bytesReadSys 28352 # Total read bytes from the system interface side | 44system.physmem.bytesReadSys 28480 # Total read bytes from the system interface side |
| 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 45system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 46system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 47system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 48system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 49system.physmem.perBankRdBursts::0 101 # Per bank write bursts | 49system.physmem.perBankRdBursts::0 103 # Per bank write bursts |
| 50system.physmem.perBankRdBursts::1 48 # Per bank write bursts 51system.physmem.perBankRdBursts::2 19 # Per bank write bursts 52system.physmem.perBankRdBursts::3 45 # Per bank write bursts 53system.physmem.perBankRdBursts::4 19 # Per bank write bursts 54system.physmem.perBankRdBursts::5 37 # Per bank write bursts 55system.physmem.perBankRdBursts::6 46 # Per bank write bursts 56system.physmem.perBankRdBursts::7 10 # Per bank write bursts 57system.physmem.perBankRdBursts::8 4 # Per bank write bursts --- 17 unchanged lines hidden (view full) --- 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 50system.physmem.perBankRdBursts::1 48 # Per bank write bursts 51system.physmem.perBankRdBursts::2 19 # Per bank write bursts 52system.physmem.perBankRdBursts::3 45 # Per bank write bursts 53system.physmem.perBankRdBursts::4 19 # Per bank write bursts 54system.physmem.perBankRdBursts::5 37 # Per bank write bursts 55system.physmem.perBankRdBursts::6 46 # Per bank write bursts 56system.physmem.perBankRdBursts::7 10 # Per bank write bursts 57system.physmem.perBankRdBursts::8 4 # Per bank write bursts --- 17 unchanged lines hidden (view full) --- 75system.physmem.perBankWrBursts::10 0 # Per bank write bursts 76system.physmem.perBankWrBursts::11 0 # Per bank write bursts 77system.physmem.perBankWrBursts::12 0 # Per bank write bursts 78system.physmem.perBankWrBursts::13 0 # Per bank write bursts 79system.physmem.perBankWrBursts::14 0 # Per bank write bursts 80system.physmem.perBankWrBursts::15 0 # Per bank write bursts 81system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 82system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 83system.physmem.totGap 18779500 # Total gap between requests | 83system.physmem.totGap 19004500 # Total gap between requests |
| 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) | 84system.physmem.readPktSize::0 0 # Read request sizes (log2) 85system.physmem.readPktSize::1 0 # Read request sizes (log2) 86system.physmem.readPktSize::2 0 # Read request sizes (log2) 87system.physmem.readPktSize::3 0 # Read request sizes (log2) 88system.physmem.readPktSize::4 0 # Read request sizes (log2) 89system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 90system.physmem.readPktSize::6 443 # Read request sizes (log2) | 90system.physmem.readPktSize::6 445 # Read request sizes (log2) |
| 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see | 91system.physmem.writePktSize::0 0 # Write request sizes (log2) 92system.physmem.writePktSize::1 0 # Write request sizes (log2) 93system.physmem.writePktSize::2 0 # Write request sizes (log2) 94system.physmem.writePktSize::3 0 # Write request sizes (log2) 95system.physmem.writePktSize::4 0 # Write request sizes (log2) 96system.physmem.writePktSize::5 0 # Write request sizes (log2) 97system.physmem.writePktSize::6 0 # Write request sizes (log2) 98system.physmem.rdQLenPdf::0 246 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 194system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation | 104system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 187system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 193system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 194system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation |
| 195system.physmem.bytesPerActivate::mean 427.682540 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 292.140083 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 354.445538 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 18 28.57% 39.68% # Bytes accessed per row activation | 195system.physmem.bytesPerActivate::mean 429.714286 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::gmean 289.613657 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::stdev 357.341954 # Bytes accessed per row activation 198system.physmem.bytesPerActivate::0-127 8 12.70% 12.70% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::128-255 17 26.98% 39.68% # Bytes accessed per row activation |
| 200system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation | 200system.physmem.bytesPerActivate::256-383 11 17.46% 57.14% # Bytes accessed per row activation |
| 201system.physmem.bytesPerActivate::384-511 7 11.11% 68.25% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 1 1.59% 69.84% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 4 6.35% 76.19% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 1 1.59% 77.78% # Bytes accessed per row activation | 201system.physmem.bytesPerActivate::384-511 6 9.52% 66.67% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::512-639 3 4.76% 71.43% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::640-767 2 3.17% 74.60% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::768-895 2 3.17% 77.78% # Bytes accessed per row activation |
| 205system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation | 205system.physmem.bytesPerActivate::896-1023 2 3.17% 80.95% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::1024-1151 12 19.05% 100.00% # Bytes accessed per row activation 207system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation |
| 208system.physmem.totQLat 3401243 # Total ticks spent queuing 209system.physmem.totMemAccLat 11707493 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 2215000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 7677.75 # Average queueing delay per DRAM burst | 208system.physmem.totQLat 4296708 # Total ticks spent queuing 209system.physmem.totMemAccLat 12640458 # Total ticks spent from burst creation until serviced by the DRAM 210system.physmem.totBusLat 2225000 # Total ticks spent in databus transfers 211system.physmem.avgQLat 9655.52 # Average queueing delay per DRAM burst |
| 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 212system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 213system.physmem.avgMemAccLat 26427.75 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 1506.40 # Average DRAM read bandwidth in MiByte/s | 213system.physmem.avgMemAccLat 28405.52 # Average memory access latency per DRAM burst 214system.physmem.avgRdBW 1495.33 # Average DRAM read bandwidth in MiByte/s |
| 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 215system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 216system.physmem.avgRdBWSys 1506.40 # Average system read bandwidth in MiByte/s | 216system.physmem.avgRdBWSys 1495.33 # Average system read bandwidth in MiByte/s |
| 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 217system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 218system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 219system.physmem.busUtil 11.77 # Data bus utilization in percentage 220system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads | 219system.physmem.busUtil 11.68 # Data bus utilization in percentage 220system.physmem.busUtilRead 11.68 # Data bus utilization in percentage for reads |
| 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 221system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 222system.physmem.avgRdQLen 1.80 # Average read queue length when enqueuing | 222system.physmem.avgRdQLen 1.86 # Average read queue length when enqueuing |
| 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 223system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 224system.physmem.readRowHits 371 # Number of row buffer hits during reads | 224system.physmem.readRowHits 373 # Number of row buffer hits during reads |
| 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 225system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 226system.physmem.readRowHitRate 83.75 # Row buffer hit rate for reads | 226system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads |
| 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 227system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 228system.physmem.avgGap 42391.65 # Average gap between requests 229system.physmem.pageHitRate 83.75 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 2160600 # Energy for read commands per rank (pJ) | 228system.physmem.avgGap 42706.74 # Average gap between requests 229system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 230system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) 231system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) 232system.physmem_0.readEnergy 2152800 # Energy for read commands per rank (pJ) |
| 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 233system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 234system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 235system.physmem_0.actBackEnergy 10755900 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 64500 # Energy for precharge background per rank (pJ) 237system.physmem_0.totalEnergy 14453835 # Total energy per rank (pJ) 238system.physmem_0.averagePower 912.921838 # Core power per rank (mW) 239system.physmem_0.memoryStateTime::IDLE 51750 # Time in different power states | 235system.physmem_0.actBackEnergy 10689210 # Energy for active background per rank (pJ) 236system.physmem_0.preBackEnergy 123000 # Energy for precharge background per rank (pJ) 237system.physmem_0.totalEnergy 14426160 # Total energy per rank (pJ) 238system.physmem_0.averagePower 911.173851 # Core power per rank (mW) 239system.physmem_0.memoryStateTime::IDLE 148750 # Time in different power states |
| 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 240system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 241system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::ACT 15274500 # Time in different power states | 242system.physmem_0.memoryStateTime::ACT 15177500 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 244system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 245system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 243system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 244system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 245system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 246system.physmem_1.readEnergy 811200 # Energy for read commands per rank (pJ) 247system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 248system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 249system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) 252system.physmem_1.averagePower 811.289436 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states | 249system.physmem_1.actBackEnergy 10733670 # Energy for active background per rank (pJ) 250system.physmem_1.preBackEnergy 84000 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 12844635 # Total energy per rank (pJ) 252system.physmem_1.averagePower 811.282804 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 1145250 # Time in different power states |
| 254system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 254system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 256system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states | 256system.physmem_1.memoryStateTime::ACT 15228250 # Time in different power states |
| 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states 259system.cpu.branchPred.lookups 2438 # Number of BP lookups 260system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted | 258system.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states 259system.cpu.branchPred.lookups 2439 # Number of BP lookups 260system.cpu.branchPred.condPredicted 1443 # Number of conditional branches predicted |
| 261system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups | 261system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups |
| 263system.cpu.branchPred.BTBHits 449 # Number of BTB hits | 263system.cpu.branchPred.BTBHits 448 # Number of BTB hits |
| 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 265system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage | 265system.cpu.branchPred.BTBHitPct 48.961749 # BTB Hit Percentage |
| 266system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 272system.cpu_clk_domain.clock 500 # Clock period in ticks | 266system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 272system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses |
| 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 13 # Number of system calls | 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 13 # Number of system calls |
| 394system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states 395system.cpu.numCycles 37643 # number of cpu cycles simulated | 394system.cpu.pwrStateResidencyTicks::ON 19046000 # Cumulative time (in ticks) in various power states 395system.cpu.numCycles 38093 # number of cpu cycles simulated |
| 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 398system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked | 398system.cpu.fetch.icacheStallCycles 6117 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 11468 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 2439 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 747 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 8723 # Number of cycles fetch has run and was not squashing or blocked |
| 403system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing | 403system.cpu.fetch.SquashCycles 1091 # Number of cycles fetch has spent squashing |
| 404system.cpu.fetch.MiscStallCycles 169 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 405system.cpu.fetch.PendingTrapStallCycles 272 # Number of stall cycles due to pending traps 406system.cpu.fetch.IcacheWaitRetryStallCycles 412 # Number of stall cycles due to full MSHR 407system.cpu.fetch.CacheLines 3904 # Number of cache lines fetched | 404system.cpu.fetch.MiscStallCycles 171 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 405system.cpu.fetch.PendingTrapStallCycles 274 # Number of stall cycles due to pending traps 406system.cpu.fetch.IcacheWaitRetryStallCycles 416 # Number of stall cycles due to full MSHR 407system.cpu.fetch.CacheLines 3907 # Number of cache lines fetched |
| 408system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed | 408system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed |
| 409system.cpu.fetch.rateDist::samples 15772 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::mean 0.863365 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::stdev 1.208800 # Number of instructions fetched each cycle (Total) | 409system.cpu.fetch.rateDist::samples 16246 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.rateDist::mean 0.839530 # Number of instructions fetched each cycle (Total) 411system.cpu.fetch.rateDist::stdev 1.200509 # Number of instructions fetched each cycle (Total) |
| 412system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 412system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 413system.cpu.fetch.rateDist::0 9389 59.53% 59.53% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::1 2507 15.90% 75.42% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::2 518 3.28% 78.71% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::3 3358 21.29% 100.00% # Number of instructions fetched each cycle (Total) | 413system.cpu.fetch.rateDist::0 9855 60.66% 60.66% # Number of instructions fetched each cycle (Total) 414system.cpu.fetch.rateDist::1 2507 15.43% 76.09% # Number of instructions fetched each cycle (Total) 415system.cpu.fetch.rateDist::2 520 3.20% 79.29% # Number of instructions fetched each cycle (Total) 416system.cpu.fetch.rateDist::3 3364 20.71% 100.00% # Number of instructions fetched each cycle (Total) |
| 417system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 417system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 418system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 419system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 420system.cpu.fetch.rateDist::total 15772 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.branchRate 0.064766 # Number of branch fetches per cycle 422system.cpu.fetch.rate 0.304280 # Number of inst fetches per cycle 423system.cpu.decode.IdleCycles 5832 # Number of cycles decode is idle 424system.cpu.decode.BlockedCycles 4243 # Number of cycles decode is blocked | 420system.cpu.fetch.rateDist::total 16246 # Number of instructions fetched each cycle (Total) 421system.cpu.fetch.branchRate 0.064028 # Number of branch fetches per cycle 422system.cpu.fetch.rate 0.301053 # Number of inst fetches per cycle 423system.cpu.decode.IdleCycles 5842 # Number of cycles decode is idle 424system.cpu.decode.BlockedCycles 4705 # Number of cycles decode is blocked |
| 425system.cpu.decode.RunCycles 5178 # Number of cycles decode is running | 425system.cpu.decode.RunCycles 5178 # Number of cycles decode is running |
| 426system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking | 426system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking |
| 427system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing | 427system.cpu.decode.SquashCycles 386 # Number of cycles decode is squashing |
| 428system.cpu.decode.BranchResolved 373 # Number of times decode resolved a branch 429system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction 430system.cpu.decode.DecodedInsts 10169 # Number of instructions handled by decode 431system.cpu.decode.SquashedInsts 1675 # Number of squashed instructions handled by decode | 428system.cpu.decode.BranchResolved 375 # Number of times decode resolved a branch 429system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction 430system.cpu.decode.DecodedInsts 10177 # Number of instructions handled by decode 431system.cpu.decode.SquashedInsts 1679 # Number of squashed instructions handled by decode |
| 432system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing | 432system.cpu.rename.SquashCycles 386 # Number of cycles rename is squashing |
| 433system.cpu.rename.IdleCycles 6945 # Number of cycles rename is idle 434system.cpu.rename.BlockCycles 1086 # Number of cycles rename is blocking 435system.cpu.rename.serializeStallCycles 2318 # count of cycles rename stalled for serializing inst 436system.cpu.rename.RunCycles 4187 # Number of cycles rename is running 437system.cpu.rename.UnblockCycles 850 # Number of cycles rename is unblocking 438system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename 439system.cpu.rename.SquashedInsts 454 # Number of squashed instructions processed by rename 440system.cpu.rename.ROBFullEvents 23 # Number of times rename has blocked due to ROB full | 433system.cpu.rename.IdleCycles 6957 # Number of cycles rename is idle 434system.cpu.rename.BlockCycles 1136 # Number of cycles rename is blocking 435system.cpu.rename.serializeStallCycles 2347 # count of cycles rename stalled for serializing inst 436system.cpu.rename.RunCycles 4188 # Number of cycles rename is running 437system.cpu.rename.UnblockCycles 1232 # Number of cycles rename is unblocking 438system.cpu.rename.RenamedInsts 9097 # Number of instructions processed by rename 439system.cpu.rename.SquashedInsts 461 # Number of squashed instructions processed by rename 440system.cpu.rename.ROBFullEvents 24 # Number of times rename has blocked due to ROB full |
| 441system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full | 441system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 442system.cpu.rename.LQFullEvents 28 # Number of times rename has blocked due to LQ full |
| 443system.cpu.rename.SQFullEvents 744 # Number of times rename has blocked due to SQ full 444system.cpu.rename.RenamedOperands 9450 # Number of destination operands rename has renamed 445system.cpu.rename.RenameLookups 41121 # Number of register rename lookups that rename has made 446system.cpu.rename.int_rename_lookups 9999 # Number of integer rename lookups | 443system.cpu.rename.SQFullEvents 1125 # Number of times rename has blocked due to SQ full 444system.cpu.rename.RenamedOperands 9457 # Number of destination operands rename has renamed 445system.cpu.rename.RenameLookups 41127 # Number of register rename lookups that rename has made 446system.cpu.rename.int_rename_lookups 9997 # Number of integer rename lookups |
| 447system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 448system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 447system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 448system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 449system.cpu.rename.UndoneMaps 3956 # Number of HB maps that are undone due to squashing | 449system.cpu.rename.UndoneMaps 3963 # Number of HB maps that are undone due to squashing |
| 450system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 451system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed | 450system.cpu.rename.serializingInsts 29 # count of serializing insts renamed 451system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed |
| 452system.cpu.rename.skidInsts 331 # count of insts added to the skid buffer 453system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit. 454system.cpu.memDep0.insertedStores 1291 # Number of stores inserted to the mem dependence unit. | 452system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer 453system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. 454system.cpu.memDep0.insertedStores 1284 # Number of stores inserted to the mem dependence unit. |
| 455system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 456system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 457system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) 458system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ | 455system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 456system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 457system.cpu.iq.iqInstsAdded 8515 # Number of instructions added to the IQ (excludes non-spec) 458system.cpu.iq.iqNonSpecInstsAdded 38 # Number of non-speculative instructions added to the IQ |
| 459system.cpu.iq.iqInstsIssued 7234 # Number of instructions issued 460system.cpu.iq.iqSquashedInstsIssued 175 # Number of squashed instructions issued | 459system.cpu.iq.iqInstsIssued 7229 # Number of instructions issued 460system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued |
| 461system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling | 461system.cpu.iq.iqSquashedInstsExamined 3175 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 462system.cpu.iq.iqSquashedOperandsExamined 8237 # Number of squashed operands that are examined and possibly removed from graph | 462system.cpu.iq.iqSquashedOperandsExamined 8254 # Number of squashed operands that are examined and possibly removed from graph |
| 463system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed | 463system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed |
| 464system.cpu.iq.issued_per_cycle::samples 15772 # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::mean 0.458661 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::stdev 0.847067 # Number of insts issued each cycle | 464system.cpu.iq.issued_per_cycle::samples 16246 # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::mean 0.444971 # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::stdev 0.838160 # Number of insts issued each cycle |
| 467system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 467system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 468system.cpu.iq.issued_per_cycle::0 11502 72.93% 72.93% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::1 1999 12.67% 85.60% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::2 1621 10.28% 95.88% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::3 607 3.85% 99.73% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::4 43 0.27% 100.00% # Number of insts issued each cycle | 468system.cpu.iq.issued_per_cycle::0 11980 73.74% 73.74% # Number of insts issued each cycle 469system.cpu.iq.issued_per_cycle::1 1997 12.29% 86.03% # Number of insts issued each cycle 470system.cpu.iq.issued_per_cycle::2 1618 9.96% 95.99% # Number of insts issued each cycle 471system.cpu.iq.issued_per_cycle::3 608 3.74% 99.74% # Number of insts issued each cycle 472system.cpu.iq.issued_per_cycle::4 43 0.26% 100.00% # Number of insts issued each cycle |
| 473system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle | 473system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 474system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 475system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 476system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 477system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 478system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 479system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle |
| 480system.cpu.iq.issued_per_cycle::total 15772 # Number of insts issued each cycle | 480system.cpu.iq.issued_per_cycle::total 16246 # Number of insts issued each cycle |
| 481system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 481system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 482system.cpu.iq.fu_full::IntAlu 415 28.78% 28.78% # attempts to use FU when none available 483system.cpu.iq.fu_full::IntMult 0 0.00% 28.78% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntDiv 0 0.00% 28.78% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.78% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.78% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.78% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatMult 0 0.00% 28.78% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.78% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.78% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.78% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.78% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.78% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.78% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.78% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMult 0 0.00% 28.78% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.78% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdShift 0 0.00% 28.78% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.78% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.78% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.78% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.78% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.78% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.78% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.78% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.78% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.78% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.78% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.78% # attempts to use FU when none available 511system.cpu.iq.fu_full::MemRead 474 32.87% 61.65% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemWrite 553 38.35% 100.00% # attempts to use FU when none available | 482system.cpu.iq.fu_full::IntAlu 416 28.89% 28.89% # attempts to use FU when none available 483system.cpu.iq.fu_full::IntMult 0 0.00% 28.89% # attempts to use FU when none available 484system.cpu.iq.fu_full::IntDiv 0 0.00% 28.89% # attempts to use FU when none available 485system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.89% # attempts to use FU when none available 486system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.89% # attempts to use FU when none available 487system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.89% # attempts to use FU when none available 488system.cpu.iq.fu_full::FloatMult 0 0.00% 28.89% # attempts to use FU when none available 489system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.89% # attempts to use FU when none available 490system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.89% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.89% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.89% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.89% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.89% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.89% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.89% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdMult 0 0.00% 28.89% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.89% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdShift 0 0.00% 28.89% # attempts to use FU when none available 500system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.89% # attempts to use FU when none available 501system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.89% # attempts to use FU when none available 502system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.89% # attempts to use FU when none available 503system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.89% # attempts to use FU when none available 504system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.89% # attempts to use FU when none available 505system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.89% # attempts to use FU when none available 506system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.89% # attempts to use FU when none available 507system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.89% # attempts to use FU when none available 508system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.89% # attempts to use FU when none available 509system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.89% # attempts to use FU when none available 510system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.89% # attempts to use FU when none available 511system.cpu.iq.fu_full::MemRead 475 32.99% 61.87% # attempts to use FU when none available 512system.cpu.iq.fu_full::MemWrite 549 38.12% 100.00% # attempts to use FU when none available |
| 513system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 514system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 513system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 514system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 515system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 516system.cpu.iq.FU_type_0::IntAlu 4534 62.68% 62.68% # Type of FU issued 517system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.75% # Type of FU issued 518system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.75% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.75% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.75% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.75% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.75% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.75% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.75% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.75% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.75% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.75% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.75% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.75% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.75% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.75% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.75% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.75% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.75% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.75% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.75% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.75% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.75% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.75% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.75% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.79% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.79% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.79% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.79% # Type of FU issued 545system.cpu.iq.FU_type_0::MemRead 1605 22.19% 84.97% # Type of FU issued 546system.cpu.iq.FU_type_0::MemWrite 1087 15.03% 100.00% # Type of FU issued | 516system.cpu.iq.FU_type_0::IntAlu 4534 62.72% 62.72% # Type of FU issued 517system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.79% # Type of FU issued 518system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.79% # Type of FU issued 519system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.79% # Type of FU issued 520system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.79% # Type of FU issued 521system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.79% # Type of FU issued 522system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.79% # Type of FU issued 523system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.79% # Type of FU issued 524system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.79% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.79% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.79% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.79% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.79% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.79% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.79% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.79% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.79% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.79% # Type of FU issued 534system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.79% # Type of FU issued 535system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.79% # Type of FU issued 536system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.79% # Type of FU issued 537system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.79% # Type of FU issued 538system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.79% # Type of FU issued 539system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.79% # Type of FU issued 540system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.79% # Type of FU issued 541system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.83% # Type of FU issued 542system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.83% # Type of FU issued 543system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.83% # Type of FU issued 544system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.83% # Type of FU issued 545system.cpu.iq.FU_type_0::MemRead 1606 22.22% 85.05% # Type of FU issued 546system.cpu.iq.FU_type_0::MemWrite 1081 14.95% 100.00% # Type of FU issued |
| 547system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 548system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 547system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 548system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 549system.cpu.iq.FU_type_0::total 7234 # Type of FU issued 550system.cpu.iq.rate 0.192174 # Inst issue rate 551system.cpu.iq.fu_busy_cnt 1442 # FU busy when requested 552system.cpu.iq.fu_busy_rate 0.199336 # FU busy rate (busy events/executed inst) 553system.cpu.iq.int_inst_queue_reads 31813 # Number of integer instruction queue reads | 549system.cpu.iq.FU_type_0::total 7229 # Type of FU issued 550system.cpu.iq.rate 0.189772 # Inst issue rate 551system.cpu.iq.fu_busy_cnt 1440 # FU busy when requested 552system.cpu.iq.fu_busy_rate 0.199198 # FU busy rate (busy events/executed inst) 553system.cpu.iq.int_inst_queue_reads 32277 # Number of integer instruction queue reads |
| 554system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes | 554system.cpu.iq.int_inst_queue_writes 11719 # Number of integer instruction queue writes |
| 555system.cpu.iq.int_inst_queue_wakeup_accesses 6621 # Number of integer instruction queue wakeup accesses | 555system.cpu.iq.int_inst_queue_wakeup_accesses 6614 # Number of integer instruction queue wakeup accesses |
| 556system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 557system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 558system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 556system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 557system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 558system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 559system.cpu.iq.int_alu_accesses 8648 # Number of integer alu accesses | 559system.cpu.iq.int_alu_accesses 8641 # Number of integer alu accesses |
| 560system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses | 560system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses |
| 561system.cpu.iew.lsq.thread0.forwLoads 11 # Number of loads that had data forwarded from stores | 561system.cpu.iew.lsq.thread0.forwLoads 12 # Number of loads that had data forwarded from stores |
| 562system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 562system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 563system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed | 563system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed |
| 564system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 565system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 564system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 565system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 566system.cpu.iew.lsq.thread0.squashedStores 353 # Number of stores squashed | 566system.cpu.iew.lsq.thread0.squashedStores 346 # Number of stores squashed |
| 567system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 568system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 569system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 570system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 571system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 572system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing | 567system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 568system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 569system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 570system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 571system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 572system.cpu.iew.iewSquashCycles 386 # Number of cycles IEW is squashing |
| 573system.cpu.iew.iewBlockCycles 336 # Number of cycles IEW is blocking | 573system.cpu.iew.iewBlockCycles 339 # Number of cycles IEW is blocking |
| 574system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 575system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ 576system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 574system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 575system.cpu.iew.iewDispatchedInsts 8566 # Number of instructions dispatched to IQ 576system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 577system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions 578system.cpu.iew.iewDispStoreInsts 1291 # Number of dispatched store instructions | 577system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions 578system.cpu.iew.iewDispStoreInsts 1284 # Number of dispatched store instructions |
| 579system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 580system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 581system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 582system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 583system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly 584system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly 585system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute | 579system.cpu.iew.iewDispNonSpecInsts 26 # Number of dispatched non-speculative instructions 580system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 581system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 582system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 583system.cpu.iew.predictedTakenIncorrect 59 # Number of branches that were predicted taken incorrectly 584system.cpu.iew.predictedNotTakenIncorrect 319 # Number of branches that were predicted not taken incorrectly 585system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute |
| 586system.cpu.iew.iewExecutedInsts 6824 # Number of executed instructions 587system.cpu.iew.iewExecLoadInsts 1421 # Number of load instructions executed 588system.cpu.iew.iewExecSquashedInsts 410 # Number of squashed instructions skipped in execute | 586system.cpu.iew.iewExecutedInsts 6820 # Number of executed instructions 587system.cpu.iew.iewExecLoadInsts 1423 # Number of load instructions executed 588system.cpu.iew.iewExecSquashedInsts 409 # Number of squashed instructions skipped in execute |
| 589system.cpu.iew.exec_swp 0 # number of swp insts executed 590system.cpu.iew.exec_nop 13 # number of nop insts executed | 589system.cpu.iew.exec_swp 0 # number of swp insts executed 590system.cpu.iew.exec_nop 13 # number of nop insts executed |
| 591system.cpu.iew.exec_refs 2451 # number of memory reference insts executed 592system.cpu.iew.exec_branches 1299 # Number of branches executed 593system.cpu.iew.exec_stores 1030 # Number of stores executed 594system.cpu.iew.exec_rate 0.181282 # Inst execution rate 595system.cpu.iew.wb_sent 6681 # cumulative count of insts sent to commit 596system.cpu.iew.wb_count 6637 # cumulative count of insts written-back 597system.cpu.iew.wb_producers 2986 # num instructions producing a value 598system.cpu.iew.wb_consumers 5424 # num instructions consuming a value 599system.cpu.iew.wb_rate 0.176314 # insts written-back per cycle 600system.cpu.iew.wb_fanout 0.550516 # average fanout of values written-back 601system.cpu.commit.commitSquashedInsts 2706 # The number of squashed insts skipped by commit | 591system.cpu.iew.exec_refs 2448 # number of memory reference insts executed 592system.cpu.iew.exec_branches 1296 # Number of branches executed 593system.cpu.iew.exec_stores 1025 # Number of stores executed 594system.cpu.iew.exec_rate 0.179036 # Inst execution rate 595system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit 596system.cpu.iew.wb_count 6630 # cumulative count of insts written-back 597system.cpu.iew.wb_producers 2985 # num instructions producing a value 598system.cpu.iew.wb_consumers 5422 # num instructions consuming a value 599system.cpu.iew.wb_rate 0.174048 # insts written-back per cycle 600system.cpu.iew.wb_fanout 0.550535 # average fanout of values written-back 601system.cpu.commit.commitSquashedInsts 2710 # The number of squashed insts skipped by commit |
| 602system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 603system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted | 602system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 603system.cpu.commit.branchMispredicts 365 # The number of times a branch was mispredicted |
| 604system.cpu.commit.committed_per_cycle::samples 15204 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::mean 0.353723 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::stdev 0.993092 # Number of insts commited each cycle | 604system.cpu.commit.committed_per_cycle::samples 15677 # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::mean 0.343050 # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::stdev 0.979995 # Number of insts commited each cycle |
| 607system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 607system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 608system.cpu.commit.committed_per_cycle::0 12538 82.47% 82.47% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::1 1405 9.24% 91.71% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::2 597 3.93% 95.63% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::3 300 1.97% 97.61% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::4 170 1.12% 98.72% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::5 79 0.52% 99.24% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::7 28 0.18% 99.72% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::8 43 0.28% 100.00% # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::0 13011 82.99% 82.99% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::1 1405 8.96% 91.96% # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::2 598 3.81% 95.77% # Number of insts commited each cycle 611system.cpu.commit.committed_per_cycle::3 299 1.91% 97.68% # Number of insts commited each cycle 612system.cpu.commit.committed_per_cycle::4 169 1.08% 98.76% # Number of insts commited each cycle 613system.cpu.commit.committed_per_cycle::5 80 0.51% 99.27% # Number of insts commited each cycle 614system.cpu.commit.committed_per_cycle::6 44 0.28% 99.55% # Number of insts commited each cycle 615system.cpu.commit.committed_per_cycle::7 28 0.18% 99.73% # Number of insts commited each cycle 616system.cpu.commit.committed_per_cycle::8 43 0.27% 100.00% # Number of insts commited each cycle |
| 617system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 617system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 618system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 619system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 620system.cpu.commit.committed_per_cycle::total 15204 # Number of insts commited each cycle | 620system.cpu.commit.committed_per_cycle::total 15677 # Number of insts commited each cycle |
| 621system.cpu.commit.committedInsts 4592 # Number of instructions committed 622system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 623system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 624system.cpu.commit.refs 1965 # Number of memory references committed 625system.cpu.commit.loads 1027 # Number of loads committed 626system.cpu.commit.membars 12 # Number of memory barriers committed 627system.cpu.commit.branches 1008 # Number of branches committed 628system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 659system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 661system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 662system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 663system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 666system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached | 621system.cpu.commit.committedInsts 4592 # Number of instructions committed 622system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 623system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 624system.cpu.commit.refs 1965 # Number of memory references committed 625system.cpu.commit.loads 1027 # Number of loads committed 626system.cpu.commit.membars 12 # Number of memory barriers committed 627system.cpu.commit.branches 1008 # Number of branches committed 628system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 659system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 660system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 661system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 662system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 663system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 664system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 665system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 666system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached |
| 667system.cpu.rob.rob_reads 23088 # The number of ROB reads 668system.cpu.rob.rob_writes 16743 # The number of ROB writes 669system.cpu.timesIdled 215 # Number of times that the entire CPU went into an idle state and unscheduled itself 670system.cpu.idleCycles 21871 # Total number of cycles that the CPU has spent unscheduled due to idling | 667system.cpu.rob.rob_reads 23565 # The number of ROB reads 668system.cpu.rob.rob_writes 16751 # The number of ROB writes 669system.cpu.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself 670system.cpu.idleCycles 21847 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 671system.cpu.committedInsts 4592 # Number of Instructions Simulated 672system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated | 671system.cpu.committedInsts 4592 # Number of Instructions Simulated 672system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated |
| 673system.cpu.cpi 8.197517 # CPI: Cycles Per Instruction 674system.cpu.cpi_total 8.197517 # CPI: Total CPI of All Threads 675system.cpu.ipc 0.121988 # IPC: Instructions Per Cycle 676system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads 677system.cpu.int_regfile_reads 6777 # number of integer regfile reads 678system.cpu.int_regfile_writes 3787 # number of integer regfile writes | 673system.cpu.cpi 8.295514 # CPI: Cycles Per Instruction 674system.cpu.cpi_total 8.295514 # CPI: Total CPI of All Threads 675system.cpu.ipc 0.120547 # IPC: Instructions Per Cycle 676system.cpu.ipc_total 0.120547 # IPC: Total IPC of All Threads 677system.cpu.int_regfile_reads 6772 # number of integer regfile reads 678system.cpu.int_regfile_writes 3788 # number of integer regfile writes |
| 679system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 679system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 680system.cpu.cc_regfile_reads 24229 # number of cc regfile reads 681system.cpu.cc_regfile_writes 2921 # number of cc regfile writes 682system.cpu.misc_regfile_reads 2564 # number of misc regfile reads | 680system.cpu.cc_regfile_reads 24217 # number of cc regfile reads 681system.cpu.cc_regfile_writes 2924 # number of cc regfile writes 682system.cpu.misc_regfile_reads 2559 # number of misc regfile reads |
| 683system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 683system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 684system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 684system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 685system.cpu.dcache.tags.replacements 1 # number of replacements | 685system.cpu.dcache.tags.replacements 1 # number of replacements |
| 686system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use | 686system.cpu.dcache.tags.tagsinuse 84.349867 # Cycle average of tags in use |
| 687system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. 688system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 689system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. 690system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 687system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. 688system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 689system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. 690system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 691system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor 692system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy 693system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy | 691system.cpu.dcache.tags.occ_blocks::cpu.data 84.349867 # Average occupied blocks per requestor 692system.cpu.dcache.tags.occ_percent::cpu.data 0.164746 # Average percentage of cache occupancy 693system.cpu.dcache.tags.occ_percent::total 0.164746 # Average percentage of cache occupancy |
| 694system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id | 694system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id |
| 695system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 696system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id | 695system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 696system.cpu.dcache.tags.age_task_id_blocks_1024::1 89 # Occupied blocks per task id |
| 697system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id | 697system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id |
| 698system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses 699system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses 700system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 698system.cpu.dcache.tags.tag_accesses 4725 # Number of tag accesses 699system.cpu.dcache.tags.data_accesses 4725 # Number of data accesses 700system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 701system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits 702system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits 703system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 704system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 705system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 706system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 707system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 708system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 709system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits 710system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits 711system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits 712system.cpu.dcache.overall_hits::total 1910 # number of overall hits | 701system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits 702system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits 703system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 704system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 705system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 706system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 707system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 708system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 709system.cpu.dcache.demand_hits::cpu.data 1910 # number of demand (read+write) hits 710system.cpu.dcache.demand_hits::total 1910 # number of demand (read+write) hits 711system.cpu.dcache.overall_hits::cpu.data 1910 # number of overall hits 712system.cpu.dcache.overall_hits::total 1910 # number of overall hits |
| 713system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 714system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses | 713system.cpu.dcache.ReadReq_misses::cpu.data 168 # number of ReadReq misses 714system.cpu.dcache.ReadReq_misses::total 168 # number of ReadReq misses |
| 715system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 716system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 717system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 718system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 715system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 716system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 717system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 718system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 719system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses 722system.cpu.dcache.overall_misses::total 358 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 10679500 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 10679500 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 7608000 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 7608000 # number of WriteReq miss cycles 727system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles 728system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles 729system.cpu.dcache.demand_miss_latency::cpu.data 18287500 # number of demand (read+write) miss cycles 730system.cpu.dcache.demand_miss_latency::total 18287500 # number of demand (read+write) miss cycles 731system.cpu.dcache.overall_miss_latency::cpu.data 18287500 # number of overall miss cycles 732system.cpu.dcache.overall_miss_latency::total 18287500 # number of overall miss cycles 733system.cpu.dcache.ReadReq_accesses::cpu.data 1355 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.ReadReq_accesses::total 1355 # number of ReadReq accesses(hits+misses) | 719system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses 720system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses 721system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses 722system.cpu.dcache.overall_misses::total 359 # number of overall misses 723system.cpu.dcache.ReadReq_miss_latency::cpu.data 10937500 # number of ReadReq miss cycles 724system.cpu.dcache.ReadReq_miss_latency::total 10937500 # number of ReadReq miss cycles 725system.cpu.dcache.WriteReq_miss_latency::cpu.data 9601000 # number of WriteReq miss cycles 726system.cpu.dcache.WriteReq_miss_latency::total 9601000 # number of WriteReq miss cycles 727system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 127000 # number of LoadLockedReq miss cycles 728system.cpu.dcache.LoadLockedReq_miss_latency::total 127000 # number of LoadLockedReq miss cycles 729system.cpu.dcache.demand_miss_latency::cpu.data 20538500 # number of demand (read+write) miss cycles 730system.cpu.dcache.demand_miss_latency::total 20538500 # number of demand (read+write) miss cycles 731system.cpu.dcache.overall_miss_latency::cpu.data 20538500 # number of overall miss cycles 732system.cpu.dcache.overall_miss_latency::total 20538500 # number of overall miss cycles 733system.cpu.dcache.ReadReq_accesses::cpu.data 1356 # number of ReadReq accesses(hits+misses) 734system.cpu.dcache.ReadReq_accesses::total 1356 # number of ReadReq accesses(hits+misses) |
| 735system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 737system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 738system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 739system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 740system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 735system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 736system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 737system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 738system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 739system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 740system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 741system.cpu.dcache.demand_accesses::cpu.data 2268 # number of demand (read+write) accesses 742system.cpu.dcache.demand_accesses::total 2268 # number of demand (read+write) accesses 743system.cpu.dcache.overall_accesses::cpu.data 2268 # number of overall (read+write) accesses 744system.cpu.dcache.overall_accesses::total 2268 # number of overall (read+write) accesses 745system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123247 # miss rate for ReadReq accesses 746system.cpu.dcache.ReadReq_miss_rate::total 0.123247 # miss rate for ReadReq accesses | 741system.cpu.dcache.demand_accesses::cpu.data 2269 # number of demand (read+write) accesses 742system.cpu.dcache.demand_accesses::total 2269 # number of demand (read+write) accesses 743system.cpu.dcache.overall_accesses::cpu.data 2269 # number of overall (read+write) accesses 744system.cpu.dcache.overall_accesses::total 2269 # number of overall (read+write) accesses 745system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123894 # miss rate for ReadReq accesses 746system.cpu.dcache.ReadReq_miss_rate::total 0.123894 # miss rate for ReadReq accesses |
| 747system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 748system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses | 747system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 748system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 749system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 750system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses |
| 751system.cpu.dcache.demand_miss_rate::cpu.data 0.157848 # miss rate for demand accesses 752system.cpu.dcache.demand_miss_rate::total 0.157848 # miss rate for demand accesses 753system.cpu.dcache.overall_miss_rate::cpu.data 0.157848 # miss rate for overall accesses 754system.cpu.dcache.overall_miss_rate::total 0.157848 # miss rate for overall accesses 755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63949.101796 # average ReadReq miss latency 756system.cpu.dcache.ReadReq_avg_miss_latency::total 63949.101796 # average ReadReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39832.460733 # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total 39832.460733 # average WriteReq miss latency 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 51082.402235 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency | 751system.cpu.dcache.demand_miss_rate::cpu.data 0.158219 # miss rate for demand accesses 752system.cpu.dcache.demand_miss_rate::total 0.158219 # miss rate for demand accesses 753system.cpu.dcache.overall_miss_rate::cpu.data 0.158219 # miss rate for overall accesses 754system.cpu.dcache.overall_miss_rate::total 0.158219 # miss rate for overall accesses 755system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 65104.166667 # average ReadReq miss latency 756system.cpu.dcache.ReadReq_avg_miss_latency::total 65104.166667 # average ReadReq miss latency 757system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50267.015707 # average WriteReq miss latency 758system.cpu.dcache.WriteReq_avg_miss_latency::total 50267.015707 # average WriteReq miss latency 759system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63500 # average LoadLockedReq miss latency 760system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63500 # average LoadLockedReq miss latency 761system.cpu.dcache.demand_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency 762system.cpu.dcache.demand_avg_miss_latency::total 57210.306407 # average overall miss latency 763system.cpu.dcache.overall_avg_miss_latency::cpu.data 57210.306407 # average overall miss latency 764system.cpu.dcache.overall_avg_miss_latency::total 57210.306407 # average overall miss latency |
| 765system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 765system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 766system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked | 766system.cpu.dcache.blocked_cycles::no_targets 1304 # number of cycles access was blocked |
| 767system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 769system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 767system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 768system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 769system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 770system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked | 770system.cpu.dcache.avg_blocked_cycles::no_targets 72.444444 # average number of cycles each access was blocked |
| 771system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 772system.cpu.dcache.writebacks::total 1 # number of writebacks | 771system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 772system.cpu.dcache.writebacks::total 1 # number of writebacks |
| 773system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 774system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits | 773system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits 774system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits |
| 775system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 776system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 777system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 778system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 775system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 776system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 777system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 778system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 779system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits 780system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits 781system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits 782system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits | 779system.cpu.dcache.demand_mshr_hits::cpu.data 215 # number of demand (read+write) MSHR hits 780system.cpu.dcache.demand_mshr_hits::total 215 # number of demand (read+write) MSHR hits 781system.cpu.dcache.overall_mshr_hits::cpu.data 215 # number of overall MSHR hits 782system.cpu.dcache.overall_mshr_hits::total 215 # number of overall MSHR hits |
| 783system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 784system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 785system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 786system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 787system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 788system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 789system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 790system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses | 783system.cpu.dcache.ReadReq_mshr_misses::cpu.data 103 # number of ReadReq MSHR misses 784system.cpu.dcache.ReadReq_mshr_misses::total 103 # number of ReadReq MSHR misses 785system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 786system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 787system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 788system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 789system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 790system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses |
| 791system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6934000 # number of ReadReq MSHR miss cycles 792system.cpu.dcache.ReadReq_mshr_miss_latency::total 6934000 # number of ReadReq MSHR miss cycles 793system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2433000 # number of WriteReq MSHR miss cycles 794system.cpu.dcache.WriteReq_mshr_miss_latency::total 2433000 # number of WriteReq MSHR miss cycles 795system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9367000 # number of demand (read+write) MSHR miss cycles 796system.cpu.dcache.demand_mshr_miss_latency::total 9367000 # number of demand (read+write) MSHR miss cycles 797system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9367000 # number of overall MSHR miss cycles 798system.cpu.dcache.overall_mshr_miss_latency::total 9367000 # number of overall MSHR miss cycles 799system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076015 # mshr miss rate for ReadReq accesses 800system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076015 # mshr miss rate for ReadReq accesses | 791system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7149000 # number of ReadReq MSHR miss cycles 792system.cpu.dcache.ReadReq_mshr_miss_latency::total 7149000 # number of ReadReq MSHR miss cycles 793system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2700500 # number of WriteReq MSHR miss cycles 794system.cpu.dcache.WriteReq_mshr_miss_latency::total 2700500 # number of WriteReq MSHR miss cycles 795system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9849500 # number of demand (read+write) MSHR miss cycles 796system.cpu.dcache.demand_mshr_miss_latency::total 9849500 # number of demand (read+write) MSHR miss cycles 797system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9849500 # number of overall MSHR miss cycles 798system.cpu.dcache.overall_mshr_miss_latency::total 9849500 # number of overall MSHR miss cycles 799system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075959 # mshr miss rate for ReadReq accesses 800system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075959 # mshr miss rate for ReadReq accesses |
| 801system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 802system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses | 801system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 802system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses |
| 803system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for demand accesses 804system.cpu.dcache.demand_mshr_miss_rate::total 0.063492 # mshr miss rate for demand accesses 805system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063492 # mshr miss rate for overall accesses 806system.cpu.dcache.overall_mshr_miss_rate::total 0.063492 # mshr miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency 808system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency 809system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency 810system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency 811system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 812system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 813system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 814system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 815system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 803system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for demand accesses 804system.cpu.dcache.demand_mshr_miss_rate::total 0.063464 # mshr miss rate for demand accesses 805system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063464 # mshr miss rate for overall accesses 806system.cpu.dcache.overall_mshr_miss_rate::total 0.063464 # mshr miss rate for overall accesses 807system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69407.766990 # average ReadReq mshr miss latency 808system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69407.766990 # average ReadReq mshr miss latency 809system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 65865.853659 # average WriteReq mshr miss latency 810system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 65865.853659 # average WriteReq mshr miss latency 811system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency 812system.cpu.dcache.demand_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency 813system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 68399.305556 # average overall mshr miss latency 814system.cpu.dcache.overall_avg_mshr_miss_latency::total 68399.305556 # average overall mshr miss latency 815system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 816system.cpu.icache.tags.replacements 44 # number of replacements | 816system.cpu.icache.tags.replacements 44 # number of replacements |
| 817system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use 818system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. | 817system.cpu.icache.tags.tagsinuse 137.872552 # Cycle average of tags in use 818system.cpu.icache.tags.total_refs 3542 # Total number of references to valid blocks. |
| 819system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. | 819system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. |
| 820system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. | 820system.cpu.icache.tags.avg_refs 11.846154 # Average number of references to valid blocks. |
| 821system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 821system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 822system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor 823system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy 824system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy | 822system.cpu.icache.tags.occ_blocks::cpu.inst 137.872552 # Average occupied blocks per requestor 823system.cpu.icache.tags.occ_percent::cpu.inst 0.269282 # Average percentage of cache occupancy 824system.cpu.icache.tags.occ_percent::total 0.269282 # Average percentage of cache occupancy |
| 825system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id | 825system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id |
| 826system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 827system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id | 826system.cpu.icache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id 827system.cpu.icache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id |
| 828system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id | 828system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id |
| 829system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses 830system.cpu.icache.tags.data_accesses 8101 # Number of data accesses 831system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states 832system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits 833system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits 834system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits 835system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits 836system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits 837system.cpu.icache.overall_hits::total 3540 # number of overall hits 838system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses 839system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses 840system.cpu.icache.demand_misses::cpu.inst 361 # number of demand (read+write) misses 841system.cpu.icache.demand_misses::total 361 # number of demand (read+write) misses 842system.cpu.icache.overall_misses::cpu.inst 361 # number of overall misses 843system.cpu.icache.overall_misses::total 361 # number of overall misses 844system.cpu.icache.ReadReq_miss_latency::cpu.inst 22435492 # number of ReadReq miss cycles 845system.cpu.icache.ReadReq_miss_latency::total 22435492 # number of ReadReq miss cycles 846system.cpu.icache.demand_miss_latency::cpu.inst 22435492 # number of demand (read+write) miss cycles 847system.cpu.icache.demand_miss_latency::total 22435492 # number of demand (read+write) miss cycles 848system.cpu.icache.overall_miss_latency::cpu.inst 22435492 # number of overall miss cycles 849system.cpu.icache.overall_miss_latency::total 22435492 # number of overall miss cycles 850system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses) 851system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses) 852system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses 853system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses 854system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses 855system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses 856system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092540 # miss rate for ReadReq accesses 857system.cpu.icache.ReadReq_miss_rate::total 0.092540 # miss rate for ReadReq accesses 858system.cpu.icache.demand_miss_rate::cpu.inst 0.092540 # miss rate for demand accesses 859system.cpu.icache.demand_miss_rate::total 0.092540 # miss rate for demand accesses 860system.cpu.icache.overall_miss_rate::cpu.inst 0.092540 # miss rate for overall accesses 861system.cpu.icache.overall_miss_rate::total 0.092540 # miss rate for overall accesses 862system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62148.177285 # average ReadReq miss latency 863system.cpu.icache.ReadReq_avg_miss_latency::total 62148.177285 # average ReadReq miss latency 864system.cpu.icache.demand_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency 865system.cpu.icache.demand_avg_miss_latency::total 62148.177285 # average overall miss latency 866system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency 867system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency 868system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked 869system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked | 829system.cpu.icache.tags.tag_accesses 8107 # Number of tag accesses 830system.cpu.icache.tags.data_accesses 8107 # Number of data accesses 831system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states 832system.cpu.icache.ReadReq_hits::cpu.inst 3542 # number of ReadReq hits 833system.cpu.icache.ReadReq_hits::total 3542 # number of ReadReq hits 834system.cpu.icache.demand_hits::cpu.inst 3542 # number of demand (read+write) hits 835system.cpu.icache.demand_hits::total 3542 # number of demand (read+write) hits 836system.cpu.icache.overall_hits::cpu.inst 3542 # number of overall hits 837system.cpu.icache.overall_hits::total 3542 # number of overall hits 838system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 839system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 840system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 841system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 842system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 843system.cpu.icache.overall_misses::total 362 # number of overall misses 844system.cpu.icache.ReadReq_miss_latency::cpu.inst 22563992 # number of ReadReq miss cycles 845system.cpu.icache.ReadReq_miss_latency::total 22563992 # number of ReadReq miss cycles 846system.cpu.icache.demand_miss_latency::cpu.inst 22563992 # number of demand (read+write) miss cycles 847system.cpu.icache.demand_miss_latency::total 22563992 # number of demand (read+write) miss cycles 848system.cpu.icache.overall_miss_latency::cpu.inst 22563992 # number of overall miss cycles 849system.cpu.icache.overall_miss_latency::total 22563992 # number of overall miss cycles 850system.cpu.icache.ReadReq_accesses::cpu.inst 3904 # number of ReadReq accesses(hits+misses) 851system.cpu.icache.ReadReq_accesses::total 3904 # number of ReadReq accesses(hits+misses) 852system.cpu.icache.demand_accesses::cpu.inst 3904 # number of demand (read+write) accesses 853system.cpu.icache.demand_accesses::total 3904 # number of demand (read+write) accesses 854system.cpu.icache.overall_accesses::cpu.inst 3904 # number of overall (read+write) accesses 855system.cpu.icache.overall_accesses::total 3904 # number of overall (read+write) accesses 856system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092725 # miss rate for ReadReq accesses 857system.cpu.icache.ReadReq_miss_rate::total 0.092725 # miss rate for ReadReq accesses 858system.cpu.icache.demand_miss_rate::cpu.inst 0.092725 # miss rate for demand accesses 859system.cpu.icache.demand_miss_rate::total 0.092725 # miss rate for demand accesses 860system.cpu.icache.overall_miss_rate::cpu.inst 0.092725 # miss rate for overall accesses 861system.cpu.icache.overall_miss_rate::total 0.092725 # miss rate for overall accesses 862system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62331.469613 # average ReadReq miss latency 863system.cpu.icache.ReadReq_avg_miss_latency::total 62331.469613 # average ReadReq miss latency 864system.cpu.icache.demand_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency 865system.cpu.icache.demand_avg_miss_latency::total 62331.469613 # average overall miss latency 866system.cpu.icache.overall_avg_miss_latency::cpu.inst 62331.469613 # average overall miss latency 867system.cpu.icache.overall_avg_miss_latency::total 62331.469613 # average overall miss latency 868system.cpu.icache.blocked_cycles::no_mshrs 8558 # number of cycles access was blocked 869system.cpu.icache.blocked_cycles::no_targets 35 # number of cycles access was blocked |
| 870system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked 871system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked | 870system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked 871system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 872system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked 873system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked | 872system.cpu.icache.avg_blocked_cycles::no_mshrs 90.084211 # average number of cycles each access was blocked 873system.cpu.icache.avg_blocked_cycles::no_targets 35 # average number of cycles each access was blocked |
| 874system.cpu.icache.writebacks::writebacks 44 # number of writebacks 875system.cpu.icache.writebacks::total 44 # number of writebacks | 874system.cpu.icache.writebacks::writebacks 44 # number of writebacks 875system.cpu.icache.writebacks::total 44 # number of writebacks |
| 876system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits 877system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 878system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits 879system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 880system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits 881system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits | 876system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits 877system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits 878system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits 879system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits 880system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits 881system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits |
| 882system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses 883system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses 884system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses 885system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses 886system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses 887system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses | 882system.cpu.icache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses 883system.cpu.icache.ReadReq_mshr_misses::total 299 # number of ReadReq MSHR misses 884system.cpu.icache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses 885system.cpu.icache.demand_mshr_misses::total 299 # number of demand (read+write) MSHR misses 886system.cpu.icache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses 887system.cpu.icache.overall_mshr_misses::total 299 # number of overall MSHR misses |
| 888system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19775992 # number of ReadReq MSHR miss cycles 889system.cpu.icache.ReadReq_mshr_miss_latency::total 19775992 # number of ReadReq MSHR miss cycles 890system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19775992 # number of demand (read+write) MSHR miss cycles 891system.cpu.icache.demand_mshr_miss_latency::total 19775992 # number of demand (read+write) MSHR miss cycles 892system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19775992 # number of overall MSHR miss cycles 893system.cpu.icache.overall_mshr_miss_latency::total 19775992 # number of overall MSHR miss cycles 894system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses 895system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses 896system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses 897system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses 898system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 899system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 900system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency 901system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency 902system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 903system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 904system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 905system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 906system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 888system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19836992 # number of ReadReq MSHR miss cycles 889system.cpu.icache.ReadReq_mshr_miss_latency::total 19836992 # number of ReadReq MSHR miss cycles 890system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19836992 # number of demand (read+write) MSHR miss cycles 891system.cpu.icache.demand_mshr_miss_latency::total 19836992 # number of demand (read+write) MSHR miss cycles 892system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19836992 # number of overall MSHR miss cycles 893system.cpu.icache.overall_mshr_miss_latency::total 19836992 # number of overall MSHR miss cycles 894system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for ReadReq accesses 895system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076588 # mshr miss rate for ReadReq accesses 896system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for demand accesses 897system.cpu.icache.demand_mshr_miss_rate::total 0.076588 # mshr miss rate for demand accesses 898system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076588 # mshr miss rate for overall accesses 899system.cpu.icache.overall_mshr_miss_rate::total 0.076588 # mshr miss rate for overall accesses 900system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66344.454849 # average ReadReq mshr miss latency 901system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66344.454849 # average ReadReq mshr miss latency 902system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency 903system.cpu.icache.demand_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency 904system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66344.454849 # average overall mshr miss latency 905system.cpu.icache.overall_avg_mshr_miss_latency::total 66344.454849 # average overall mshr miss latency 906system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 907system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 908system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 909system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 910system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 911system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 912system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 907system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 908system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 909system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 910system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 911system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 912system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 913system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 913system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 914system.cpu.l2cache.tags.replacements 0 # number of replacements | 914system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 915system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use 916system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks. 917system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. 918system.cpu.l2cache.tags.avg_refs 0.229167 # Average number of references to valid blocks. | 915system.cpu.l2cache.tags.tagsinuse 17.395386 # Cycle average of tags in use 916system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 917system.cpu.l2cache.tags.sampled_refs 41 # Sample count of references to valid blocks. 918system.cpu.l2cache.tags.avg_refs 0.073171 # Average number of references to valid blocks. |
| 919system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 919system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 920system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor 921system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor 922system.cpu.l2cache.tags.occ_percent::writebacks 0.000645 # Average percentage of cache occupancy 923system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000564 # Average percentage of cache occupancy 924system.cpu.l2cache.tags.occ_percent::total 0.001209 # Average percentage of cache occupancy 925system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 926system.cpu.l2cache.tags.occ_task_id_blocks::1024 32 # Occupied blocks per task id | 920system.cpu.l2cache.tags.occ_blocks::writebacks 9.233331 # Average occupied blocks per requestor 921system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.162055 # Average occupied blocks per requestor 922system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy 923system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000498 # Average percentage of cache occupancy 924system.cpu.l2cache.tags.occ_percent::total 0.001062 # Average percentage of cache occupancy 925system.cpu.l2cache.tags.occ_task_id_blocks::1022 13 # Occupied blocks per task id 926system.cpu.l2cache.tags.occ_task_id_blocks::1024 28 # Occupied blocks per task id |
| 927system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id | 927system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id |
| 928system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 930system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 931system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 932system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id 933system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses 934system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses 935system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 928system.cpu.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::0 23 # Occupied blocks per task id 930system.cpu.l2cache.tags.age_task_id_blocks_1024::1 5 # Occupied blocks per task id 931system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000793 # Percentage of cache occupancy per task id 932system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001709 # Percentage of cache occupancy per task id 933system.cpu.l2cache.tags.tag_accesses 7676 # Number of tag accesses 934system.cpu.l2cache.tags.data_accesses 7676 # Number of data accesses 935system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 936system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 937system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits | 936system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 937system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits |
| 938system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 939system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits | 938system.cpu.l2cache.ReadExReq_hits::cpu.data 10 # number of ReadExReq hits 939system.cpu.l2cache.ReadExReq_hits::total 10 # number of ReadExReq hits |
| 940system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 941system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits | 940system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 941system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits |
| 942system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 943system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits | |
| 944system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits | 942system.cpu.l2cache.demand_hits::cpu.inst 8 # number of demand (read+write) hits |
| 945system.cpu.l2cache.demand_hits::cpu.data 13 # number of demand (read+write) hits 946system.cpu.l2cache.demand_hits::total 21 # number of demand (read+write) hits | 943system.cpu.l2cache.demand_hits::cpu.data 10 # number of demand (read+write) hits 944system.cpu.l2cache.demand_hits::total 18 # number of demand (read+write) hits |
| 947system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits | 945system.cpu.l2cache.overall_hits::cpu.inst 8 # number of overall hits |
| 948system.cpu.l2cache.overall_hits::cpu.data 13 # number of overall hits 949system.cpu.l2cache.overall_hits::total 21 # number of overall hits 950system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 951system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses | 946system.cpu.l2cache.overall_hits::cpu.data 10 # number of overall hits 947system.cpu.l2cache.overall_hits::total 18 # number of overall hits 948system.cpu.l2cache.ReadExReq_misses::cpu.data 31 # number of ReadExReq misses 949system.cpu.l2cache.ReadExReq_misses::total 31 # number of ReadExReq misses |
| 952system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses 953system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses | 950system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 291 # number of ReadCleanReq misses 951system.cpu.l2cache.ReadCleanReq_misses::total 291 # number of ReadCleanReq misses |
| 954system.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 955system.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses | 952system.cpu.l2cache.ReadSharedReq_misses::cpu.data 103 # number of ReadSharedReq misses 953system.cpu.l2cache.ReadSharedReq_misses::total 103 # number of ReadSharedReq misses |
| 956system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses | 954system.cpu.l2cache.demand_misses::cpu.inst 291 # number of demand (read+write) misses |
| 957system.cpu.l2cache.demand_misses::cpu.data 131 # number of demand (read+write) misses 958system.cpu.l2cache.demand_misses::total 422 # number of demand (read+write) misses | 955system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses 956system.cpu.l2cache.demand_misses::total 425 # number of demand (read+write) misses |
| 959system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses | 957system.cpu.l2cache.overall_misses::cpu.inst 291 # number of overall misses |
| 960system.cpu.l2cache.overall_misses::cpu.data 131 # number of overall misses 961system.cpu.l2cache.overall_misses::total 422 # number of overall misses 962system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2299000 # number of ReadExReq miss cycles 963system.cpu.l2cache.ReadExReq_miss_latency::total 2299000 # number of ReadExReq miss cycles 964system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19417500 # number of ReadCleanReq miss cycles 965system.cpu.l2cache.ReadCleanReq_miss_latency::total 19417500 # number of ReadCleanReq miss cycles 966system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6760500 # number of ReadSharedReq miss cycles 967system.cpu.l2cache.ReadSharedReq_miss_latency::total 6760500 # number of ReadSharedReq miss cycles 968system.cpu.l2cache.demand_miss_latency::cpu.inst 19417500 # number of demand (read+write) miss cycles 969system.cpu.l2cache.demand_miss_latency::cpu.data 9059500 # number of demand (read+write) miss cycles 970system.cpu.l2cache.demand_miss_latency::total 28477000 # number of demand (read+write) miss cycles 971system.cpu.l2cache.overall_miss_latency::cpu.inst 19417500 # number of overall miss cycles 972system.cpu.l2cache.overall_miss_latency::cpu.data 9059500 # number of overall miss cycles 973system.cpu.l2cache.overall_miss_latency::total 28477000 # number of overall miss cycles | 958system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses 959system.cpu.l2cache.overall_misses::total 425 # number of overall misses 960system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2572500 # number of ReadExReq miss cycles 961system.cpu.l2cache.ReadExReq_miss_latency::total 2572500 # number of ReadExReq miss cycles 962system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 19478500 # number of ReadCleanReq miss cycles 963system.cpu.l2cache.ReadCleanReq_miss_latency::total 19478500 # number of ReadCleanReq miss cycles 964system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 6989500 # number of ReadSharedReq miss cycles 965system.cpu.l2cache.ReadSharedReq_miss_latency::total 6989500 # number of ReadSharedReq miss cycles 966system.cpu.l2cache.demand_miss_latency::cpu.inst 19478500 # number of demand (read+write) miss cycles 967system.cpu.l2cache.demand_miss_latency::cpu.data 9562000 # number of demand (read+write) miss cycles 968system.cpu.l2cache.demand_miss_latency::total 29040500 # number of demand (read+write) miss cycles 969system.cpu.l2cache.overall_miss_latency::cpu.inst 19478500 # number of overall miss cycles 970system.cpu.l2cache.overall_miss_latency::cpu.data 9562000 # number of overall miss cycles 971system.cpu.l2cache.overall_miss_latency::total 29040500 # number of overall miss cycles |
| 974system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 975system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 976system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 977system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 978system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) 979system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) 980system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 981system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) 982system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses 983system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 984system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses 985system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses 986system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 987system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses | 972system.cpu.l2cache.WritebackClean_accesses::writebacks 33 # number of WritebackClean accesses(hits+misses) 973system.cpu.l2cache.WritebackClean_accesses::total 33 # number of WritebackClean accesses(hits+misses) 974system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 975system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 976system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 299 # number of ReadCleanReq accesses(hits+misses) 977system.cpu.l2cache.ReadCleanReq_accesses::total 299 # number of ReadCleanReq accesses(hits+misses) 978system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 103 # number of ReadSharedReq accesses(hits+misses) 979system.cpu.l2cache.ReadSharedReq_accesses::total 103 # number of ReadSharedReq accesses(hits+misses) 980system.cpu.l2cache.demand_accesses::cpu.inst 299 # number of demand (read+write) accesses 981system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 982system.cpu.l2cache.demand_accesses::total 443 # number of demand (read+write) accesses 983system.cpu.l2cache.overall_accesses::cpu.inst 299 # number of overall (read+write) accesses 984system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 985system.cpu.l2cache.overall_accesses::total 443 # number of overall (read+write) accesses |
| 988system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 989system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses | 986system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.756098 # miss rate for ReadExReq accesses 987system.cpu.l2cache.ReadExReq_miss_rate::total 0.756098 # miss rate for ReadExReq accesses |
| 990system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses 991system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses | 988system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.973244 # miss rate for ReadCleanReq accesses 989system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.973244 # miss rate for ReadCleanReq accesses |
| 992system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.980583 # miss rate for ReadSharedReq accesses 993system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.980583 # miss rate for ReadSharedReq accesses | 990system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 991system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| 994system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses | 992system.cpu.l2cache.demand_miss_rate::cpu.inst 0.973244 # miss rate for demand accesses |
| 995system.cpu.l2cache.demand_miss_rate::cpu.data 0.909722 # miss rate for demand accesses 996system.cpu.l2cache.demand_miss_rate::total 0.952596 # miss rate for demand accesses | 993system.cpu.l2cache.demand_miss_rate::cpu.data 0.930556 # miss rate for demand accesses 994system.cpu.l2cache.demand_miss_rate::total 0.959368 # miss rate for demand accesses |
| 997system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses | 995system.cpu.l2cache.overall_miss_rate::cpu.inst 0.973244 # miss rate for overall accesses |
| 998system.cpu.l2cache.overall_miss_rate::cpu.data 0.909722 # miss rate for overall accesses 999system.cpu.l2cache.overall_miss_rate::total 0.952596 # miss rate for overall accesses 1000system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 76633.333333 # average ReadExReq miss latency 1001system.cpu.l2cache.ReadExReq_avg_miss_latency::total 76633.333333 # average ReadExReq miss latency 1002system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66726.804124 # average ReadCleanReq miss latency 1003system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66726.804124 # average ReadCleanReq miss latency 1004system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66935.643564 # average ReadSharedReq miss latency 1005system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66935.643564 # average ReadSharedReq miss latency 1006system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency 1007system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency 1008system.cpu.l2cache.demand_avg_miss_latency::total 67481.042654 # average overall miss latency 1009system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66726.804124 # average overall miss latency 1010system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency 1011system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency | 996system.cpu.l2cache.overall_miss_rate::cpu.data 0.930556 # miss rate for overall accesses 997system.cpu.l2cache.overall_miss_rate::total 0.959368 # miss rate for overall accesses 998system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 82983.870968 # average ReadExReq miss latency 999system.cpu.l2cache.ReadExReq_avg_miss_latency::total 82983.870968 # average ReadExReq miss latency 1000system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 66936.426117 # average ReadCleanReq miss latency 1001system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 66936.426117 # average ReadCleanReq miss latency 1002system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 67859.223301 # average ReadSharedReq miss latency 1003system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 67859.223301 # average ReadSharedReq miss latency 1004system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency 1005system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency 1006system.cpu.l2cache.demand_avg_miss_latency::total 68330.588235 # average overall miss latency 1007system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66936.426117 # average overall miss latency 1008system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71358.208955 # average overall miss latency 1009system.cpu.l2cache.overall_avg_miss_latency::total 68330.588235 # average overall miss latency |
| 1012system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1013system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1014system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1015system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1016system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1017system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 1010system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1011system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1012system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1013system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1014system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1015system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1016system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data 1 # number of ReadExReq MSHR hits 1017system.cpu.l2cache.ReadExReq_mshr_hits::total 1 # number of ReadExReq MSHR hits |
|
| 1018system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1019system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1020system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1021system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1022system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits | 1018system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1019system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1020system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1021system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1022system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits |
| 1023system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1024system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits | 1023system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 1024system.cpu.l2cache.demand_mshr_hits::total 7 # number of demand (read+write) MSHR hits |
| 1025system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits | 1025system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits |
| 1026system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1027system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits | 1026system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 1027system.cpu.l2cache.overall_mshr_hits::total 7 # number of overall MSHR hits |
| 1028system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses 1029system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses 1030system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1031system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 1032system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses 1033system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses | 1028system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 53 # number of HardPFReq MSHR misses 1029system.cpu.l2cache.HardPFReq_mshr_misses::total 53 # number of HardPFReq MSHR misses 1030system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1031system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 1032system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 290 # number of ReadCleanReq MSHR misses 1033system.cpu.l2cache.ReadCleanReq_mshr_misses::total 290 # number of ReadCleanReq MSHR misses |
| 1034system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 96 # number of ReadSharedReq MSHR misses 1035system.cpu.l2cache.ReadSharedReq_mshr_misses::total 96 # number of ReadSharedReq MSHR misses | 1034system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 98 # number of ReadSharedReq MSHR misses 1035system.cpu.l2cache.ReadSharedReq_mshr_misses::total 98 # number of ReadSharedReq MSHR misses |
| 1036system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses | 1036system.cpu.l2cache.demand_mshr_misses::cpu.inst 290 # number of demand (read+write) MSHR misses |
| 1037system.cpu.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses 1038system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses | 1037system.cpu.l2cache.demand_mshr_misses::cpu.data 128 # number of demand (read+write) MSHR misses 1038system.cpu.l2cache.demand_mshr_misses::total 418 # number of demand (read+write) MSHR misses |
| 1039system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses | 1039system.cpu.l2cache.overall_mshr_misses::cpu.inst 290 # number of overall MSHR misses |
| 1040system.cpu.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses | 1040system.cpu.l2cache.overall_mshr_misses::cpu.data 128 # number of overall MSHR misses |
| 1041system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses | 1041system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 53 # number of overall MSHR misses |
| 1042system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 1043system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of HardPFReq MSHR miss cycles 1044system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1908926 # number of HardPFReq MSHR miss cycles 1045system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2119000 # number of ReadExReq MSHR miss cycles 1046system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2119000 # number of ReadExReq MSHR miss cycles 1047system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17622000 # number of ReadCleanReq MSHR miss cycles 1048system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17622000 # number of ReadCleanReq MSHR miss cycles 1049system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 5892000 # number of ReadSharedReq MSHR miss cycles 1050system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 5892000 # number of ReadSharedReq MSHR miss cycles 1051system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17622000 # number of demand (read+write) MSHR miss cycles 1052system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8011000 # number of demand (read+write) MSHR miss cycles 1053system.cpu.l2cache.demand_mshr_miss_latency::total 25633000 # number of demand (read+write) MSHR miss cycles 1054system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17622000 # number of overall MSHR miss cycles 1055system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8011000 # number of overall MSHR miss cycles 1056system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1908926 # number of overall MSHR miss cycles 1057system.cpu.l2cache.overall_mshr_miss_latency::total 27541926 # number of overall MSHR miss cycles | 1042system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses 1043system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of HardPFReq MSHR miss cycles 1044system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 3053926 # number of HardPFReq MSHR miss cycles 1045system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2154000 # number of ReadExReq MSHR miss cycles 1046system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2154000 # number of ReadExReq MSHR miss cycles 1047system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 17682000 # number of ReadCleanReq MSHR miss cycles 1048system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 17682000 # number of ReadCleanReq MSHR miss cycles 1049system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6104000 # number of ReadSharedReq MSHR miss cycles 1050system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6104000 # number of ReadSharedReq MSHR miss cycles 1051system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17682000 # number of demand (read+write) MSHR miss cycles 1052system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8258000 # number of demand (read+write) MSHR miss cycles 1053system.cpu.l2cache.demand_mshr_miss_latency::total 25940000 # number of demand (read+write) MSHR miss cycles 1054system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17682000 # number of overall MSHR miss cycles 1055system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8258000 # number of overall MSHR miss cycles 1056system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 3053926 # number of overall MSHR miss cycles 1057system.cpu.l2cache.overall_mshr_miss_latency::total 28993926 # number of overall MSHR miss cycles |
| 1058system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1059system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1060system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses | 1058system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1059system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1060system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1061system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1062system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for ReadCleanReq accesses 1063system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.969900 # mshr miss rate for ReadCleanReq accesses |
| 1064system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.932039 # mshr miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.932039 # mshr miss rate for ReadSharedReq accesses | 1064system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.951456 # mshr miss rate for ReadSharedReq accesses 1065system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.951456 # mshr miss rate for ReadSharedReq accesses |
| 1066system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses | 1066system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for demand accesses |
| 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for demand accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::total 0.939052 # mshr miss rate for demand accesses | 1067system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for demand accesses 1068system.cpu.l2cache.demand_mshr_miss_rate::total 0.943567 # mshr miss rate for demand accesses |
| 1069system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses | 1069system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.969900 # mshr miss rate for overall accesses |
| 1070system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.875000 # mshr miss rate for overall accesses | 1070system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.888889 # mshr miss rate for overall accesses |
| 1071system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1071system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1072system.cpu.l2cache.overall_mshr_miss_rate::total 1.058691 # mshr miss rate for overall accesses 1073system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average HardPFReq mshr miss latency 1074system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 36017.471698 # average HardPFReq mshr miss latency 1075system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70633.333333 # average ReadExReq mshr miss latency 1076system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70633.333333 # average ReadExReq mshr miss latency 1077system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60765.517241 # average ReadCleanReq mshr miss latency 1078system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60765.517241 # average ReadCleanReq mshr miss latency 1079system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61375 # average ReadSharedReq mshr miss latency 1080system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency 1081system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1082system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1083system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency 1084system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1085system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1086system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency 1087system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency | 1072system.cpu.l2cache.overall_mshr_miss_rate::total 1.063205 # mshr miss rate for overall accesses 1073system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average HardPFReq mshr miss latency 1074system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 57621.245283 # average HardPFReq mshr miss latency 1075system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71800 # average ReadExReq mshr miss latency 1076system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71800 # average ReadExReq mshr miss latency 1077system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 60972.413793 # average ReadCleanReq mshr miss latency 1078system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 60972.413793 # average ReadCleanReq mshr miss latency 1079system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 62285.714286 # average ReadSharedReq mshr miss latency 1080system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 62285.714286 # average ReadSharedReq mshr miss latency 1081system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency 1082system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency 1083system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62057.416268 # average overall mshr miss latency 1084system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60972.413793 # average overall mshr miss latency 1085system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64515.625000 # average overall mshr miss latency 1086system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 57621.245283 # average overall mshr miss latency 1087system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61558.229299 # average overall mshr miss latency |
| 1088system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. | 1088system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1091system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. 1092system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1093system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1094system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states | 1091system.cpu.toL2Bus.snoop_filter.tot_snoops 26 # Total number of snoops made to the snoop filter. 1092system.cpu.toL2Bus.snoop_filter.hit_single_snoops 24 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1093system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 2 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1094system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states |
| 1095system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1096system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution | 1095system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1096system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution |
| 1097system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution | |
| 1098system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1099system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1100system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1101system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1102system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 1103system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) 1104system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) 1105system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) 1106system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) 1107system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) 1108system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) | 1097system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1098system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1099system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1100system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1101system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution 1102system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 # Packet count per connected master and slave (bytes) 1103system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 # Packet count per connected master and slave (bytes) 1104system.cpu.toL2Bus.pkt_count::total 930 # Packet count per connected master and slave (bytes) 1105system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 # Cumulative packet size per connected master and slave (bytes) 1106system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 # Cumulative packet size per connected master and slave (bytes) 1107system.cpu.toL2Bus.pkt_size::total 31168 # Cumulative packet size per connected master and slave (bytes) |
| 1109system.cpu.toL2Bus.snoops 454 # Total snoops (count) | 1108system.cpu.toL2Bus.snoops 69 # Total snoops (count) |
| 1110system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) | 1109system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1111system.cpu.toL2Bus.snoop_fanout::samples 897 # Request fanout histogram 1112system.cpu.toL2Bus.snoop_fanout::mean 0.549610 # Request fanout histogram 1113system.cpu.toL2Bus.snoop_fanout::stdev 0.582523 # Request fanout histogram | 1110system.cpu.toL2Bus.snoop_fanout::samples 512 # Request fanout histogram 1111system.cpu.toL2Bus.snoop_fanout::mean 0.134766 # Request fanout histogram 1112system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 # Request fanout histogram |
| 1114system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1113system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1115system.cpu.toL2Bus.snoop_fanout::0 445 49.61% 49.61% # Request fanout histogram 1116system.cpu.toL2Bus.snoop_fanout::1 411 45.82% 95.43% # Request fanout histogram 1117system.cpu.toL2Bus.snoop_fanout::2 41 4.57% 100.00% # Request fanout histogram | 1114system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% # Request fanout histogram 1115system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% # Request fanout histogram 1116system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% # Request fanout histogram |
| 1118system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1119system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1120system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram | 1117system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1118system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 1119system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| 1121system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram | 1120system.cpu.toL2Bus.snoop_fanout::total 512 # Request fanout histogram |
| 1122system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) 1123system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1124system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) 1125system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1126system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) | 1121system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) 1122system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1123system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) 1124system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1125system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) |
| 1127system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) 1128system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states 1129system.membus.trans_dist::ReadResp 412 # Transaction distribution | 1126system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 1127system.membus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 1128system.membus.snoop_filter.hit_single_requests 35 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1129system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1130system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 1131system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1132system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1133system.membus.pwrStateResidencyTicks::UNDEFINED 19046000 # Cumulative time (in ticks) in various power states 1134system.membus.trans_dist::ReadResp 414 # Transaction distribution |
| 1130system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1131system.membus.trans_dist::ReadExResp 30 # Transaction distribution | 1135system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1136system.membus.trans_dist::ReadExResp 30 # Transaction distribution |
| 1132system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 1133system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) 1134system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) 1135system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) 1136system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) | 1137system.membus.trans_dist::ReadSharedReq 415 # Transaction distribution 1138system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 # Packet count per connected master and slave (bytes) 1139system.membus.pkt_count::total 889 # Packet count per connected master and slave (bytes) 1140system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 1141system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) |
| 1137system.membus.snoops 0 # Total snoops (count) 1138system.membus.snoopTraffic 0 # Total snoop traffic (bytes) | 1142system.membus.snoops 0 # Total snoops (count) 1143system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| 1139system.membus.snoop_fanout::samples 443 # Request fanout histogram | 1144system.membus.snoop_fanout::samples 445 # Request fanout histogram |
| 1140system.membus.snoop_fanout::mean 0 # Request fanout histogram 1141system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1142system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1145system.membus.snoop_fanout::mean 0 # Request fanout histogram 1146system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1147system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1143system.membus.snoop_fanout::0 443 100.00% 100.00% # Request fanout histogram | 1148system.membus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram |
| 1144system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1145system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1146system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1147system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1149system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1150system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1151system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1152system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1148system.membus.snoop_fanout::total 443 # Request fanout histogram 1149system.membus.reqLayer0.occupancy 561444 # Layer occupancy (ticks) | 1153system.membus.snoop_fanout::total 445 # Request fanout histogram 1154system.membus.reqLayer0.occupancy 562944 # Layer occupancy (ticks) |
| 1150system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) | 1155system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) |
| 1151system.membus.respLayer1.occupancy 2329257 # Layer occupancy (ticks) 1152system.membus.respLayer1.utilization 12.4 # Layer utilization (%) | 1156system.membus.respLayer1.occupancy 2340257 # Layer occupancy (ticks) 1157system.membus.respLayer1.utilization 12.3 # Layer utilization (%) |
| 1153 1154---------- End Simulation Statistics ---------- | 1158 1159---------- End Simulation Statistics ---------- |