| stats.txt (11515:c48c7cc5a522) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18821000 # Number of ticks simulated 5final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18821000 # Number of ticks simulated 5final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 77535 # Simulator instruction rate (inst/s) 8host_op_rate 90790 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 317684946 # Simulator tick rate (ticks/s) 10host_mem_usage 305172 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 84019 # Simulator instruction rate (inst/s) 8host_op_rate 98384 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 344256847 # Simulator tick rate (ticks/s) 10host_mem_usage 306884 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 249system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) 251system.physmem_1.averagePower 811.289436 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 19system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 20system.physmem.bytes_read::total 28352 # Number of bytes read from this memory 21system.physmem.bytes_inst_read::cpu.inst 18560 # Number of instructions bytes read from this memory 22system.physmem.bytes_inst_read::total 18560 # Number of instructions bytes read from this memory 23system.physmem.num_reads::cpu.inst 290 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.data 126 # Number of read requests responded to by this memory --- 225 unchanged lines hidden (view full) --- 250system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 251system.physmem_1.totalEnergy 12844740 # Total energy per rank (pJ) 252system.physmem_1.averagePower 811.289436 # Core power per rank (mW) 253system.physmem_1.memoryStateTime::IDLE 945250 # Time in different power states 254system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 255system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 256system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states 257system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 258system.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 257system.cpu.branchPred.lookups 2438 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 449 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 266system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 267system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 268system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 269system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 270system.cpu_clk_domain.clock 500 # Clock period in ticks | 259system.cpu.branchPred.lookups 2438 # Number of BP lookups 260system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted 261system.cpu.branchPred.condIncorrect 524 # Number of conditional branches incorrect 262system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups 263system.cpu.branchPred.BTBHits 449 # Number of BTB hits 264system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 265system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage 266system.cpu.branchPred.usedRAS 286 # Number of times the RAS was used to get a target. 267system.cpu.branchPred.RASInCorrect 57 # Number of incorrect RAS predictions. 268system.cpu.branchPred.indirectLookups 163 # Number of indirect predictor lookups. 269system.cpu.branchPred.indirectHits 13 # Number of indirect target hits. 270system.cpu.branchPred.indirectMisses 150 # Number of indirect misses. 271system.cpu.branchPredindirectMispredicted 60 # Number of mispredicted indirect branches. 272system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 273system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 271system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 292system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 293system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 294system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 295system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 296system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 297system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 298system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 299system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 274system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 275system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 276system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 277system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 278system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 279system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 280system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 281system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 295system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 296system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 297system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 298system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 299system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 300system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 301system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 302system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 303system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 300system.cpu.dtb.walker.walks 0 # Table walker walks requested 301system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 304system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 305system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 321system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 322system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 323system.cpu.dtb.read_accesses 0 # DTB read accesses 324system.cpu.dtb.write_accesses 0 # DTB write accesses 325system.cpu.dtb.inst_accesses 0 # ITB inst accesses 326system.cpu.dtb.hits 0 # DTB hits 327system.cpu.dtb.misses 0 # DTB misses 328system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.walker.walks 0 # Table walker walks requested 305system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 306system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 307system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 308system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 309system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 310system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 311system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 325system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 326system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 327system.cpu.dtb.read_accesses 0 # DTB read accesses 328system.cpu.dtb.write_accesses 0 # DTB write accesses 329system.cpu.dtb.inst_accesses 0 # ITB inst accesses 330system.cpu.dtb.hits 0 # DTB hits 331system.cpu.dtb.misses 0 # DTB misses 332system.cpu.dtb.accesses 0 # DTB accesses |
| 333system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 329system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 333system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 334system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 350system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 351system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 352system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 353system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 354system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 355system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 356system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 357system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 334system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 335system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 336system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 337system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 338system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 339system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 340system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 341system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 13 unchanged lines hidden (view full) --- 355system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 356system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 357system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 358system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 359system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 360system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 361system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 362system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 363system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 358system.cpu.itb.walker.walks 0 # Table walker walks requested 359system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 362system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 363system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 364system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 365system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 380system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 381system.cpu.itb.read_accesses 0 # DTB read accesses 382system.cpu.itb.write_accesses 0 # DTB write accesses 383system.cpu.itb.inst_accesses 0 # ITB inst accesses 384system.cpu.itb.hits 0 # DTB hits 385system.cpu.itb.misses 0 # DTB misses 386system.cpu.itb.accesses 0 # DTB accesses 387system.cpu.workload.num_syscalls 13 # Number of system calls | 364system.cpu.itb.walker.walks 0 # Table walker walks requested 365system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 366system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 367system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 368system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 369system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 370system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 371system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst --- 14 unchanged lines hidden (view full) --- 386system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 387system.cpu.itb.read_accesses 0 # DTB read accesses 388system.cpu.itb.write_accesses 0 # DTB write accesses 389system.cpu.itb.inst_accesses 0 # ITB inst accesses 390system.cpu.itb.hits 0 # DTB hits 391system.cpu.itb.misses 0 # DTB misses 392system.cpu.itb.accesses 0 # DTB accesses 393system.cpu.workload.num_syscalls 13 # Number of system calls |
| 394system.cpu.pwrStateResidencyTicks::ON 18821000 # Cumulative time (in ticks) in various power states |
|
| 388system.cpu.numCycles 37643 # number of cpu cycles simulated 389system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 390system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 391system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss 392system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed 393system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 394system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken 395system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 669system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads 670system.cpu.int_regfile_reads 6777 # number of integer regfile reads 671system.cpu.int_regfile_writes 3787 # number of integer regfile writes 672system.cpu.fp_regfile_reads 16 # number of floating regfile reads 673system.cpu.cc_regfile_reads 24229 # number of cc regfile reads 674system.cpu.cc_regfile_writes 2921 # number of cc regfile writes 675system.cpu.misc_regfile_reads 2562 # number of misc regfile reads 676system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 395system.cpu.numCycles 37643 # number of cpu cycles simulated 396system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 397system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 398system.cpu.fetch.icacheStallCycles 6083 # Number of cycles fetch is stalled on an Icache miss 399system.cpu.fetch.Insts 11454 # Number of instructions fetch has processed 400system.cpu.fetch.Branches 2438 # Number of branches that fetch encountered 401system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken 402system.cpu.fetch.Cycles 8291 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 676system.cpu.ipc_total 0.121988 # IPC: Total IPC of All Threads 677system.cpu.int_regfile_reads 6777 # number of integer regfile reads 678system.cpu.int_regfile_writes 3787 # number of integer regfile writes 679system.cpu.fp_regfile_reads 16 # number of floating regfile reads 680system.cpu.cc_regfile_reads 24229 # number of cc regfile reads 681system.cpu.cc_regfile_writes 2921 # number of cc regfile writes 682system.cpu.misc_regfile_reads 2562 # number of misc regfile reads 683system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 684system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 677system.cpu.dcache.tags.replacements 1 # number of replacements 678system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use 679system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. 680system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 681system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. 682system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 683system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor 684system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy 685system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy 686system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 688system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 689system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 690system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses 691system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses | 685system.cpu.dcache.tags.replacements 1 # number of replacements 686system.cpu.dcache.tags.tagsinuse 84.368926 # Cycle average of tags in use 687system.cpu.dcache.tags.total_refs 1930 # Total number of references to valid blocks. 688system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 689system.cpu.dcache.tags.avg_refs 13.496503 # Average number of references to valid blocks. 690system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 691system.cpu.dcache.tags.occ_blocks::cpu.data 84.368926 # Average occupied blocks per requestor 692system.cpu.dcache.tags.occ_percent::cpu.data 0.164783 # Average percentage of cache occupancy 693system.cpu.dcache.tags.occ_percent::total 0.164783 # Average percentage of cache occupancy 694system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 695system.cpu.dcache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id 696system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 697system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 698system.cpu.dcache.tags.tag_accesses 4723 # Number of tag accesses 699system.cpu.dcache.tags.data_accesses 4723 # Number of data accesses |
| 700system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 692system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits 693system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits 694system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 695system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 696system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 697system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 698system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 699system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 98 unchanged lines hidden (view full) --- 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency | 701system.cpu.dcache.ReadReq_hits::cpu.data 1188 # number of ReadReq hits 702system.cpu.dcache.ReadReq_hits::total 1188 # number of ReadReq hits 703system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 704system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 705system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 706system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 707system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 708system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits --- 98 unchanged lines hidden (view full) --- 807system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency 808system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency 809system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency 810system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency 811system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 812system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 813system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 814system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency |
| 815system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 806system.cpu.icache.tags.replacements 44 # number of replacements 807system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use 808system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. 809system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. 810system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. 811system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 812system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor 813system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy 814system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy 815system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 817system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 818system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id 819system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses 820system.cpu.icache.tags.data_accesses 8101 # Number of data accesses | 816system.cpu.icache.tags.replacements 44 # number of replacements 817system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use 818system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. 819system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. 820system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. 821system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 822system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor 823system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy 824system.cpu.icache.tags.occ_percent::total 0.269317 # Average percentage of cache occupancy 825system.cpu.icache.tags.occ_task_id_blocks::1024 255 # Occupied blocks per task id 826system.cpu.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id 827system.cpu.icache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id 828system.cpu.icache.tags.occ_task_id_percent::1024 0.498047 # Percentage of cache occupancy per task id 829system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses 830system.cpu.icache.tags.data_accesses 8101 # Number of data accesses |
| 831system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 821system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits 822system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits 823system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits 824system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits 825system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits 826system.cpu.icache.overall_hits::total 3540 # number of overall hits 827system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses 828system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency | 832system.cpu.icache.ReadReq_hits::cpu.inst 3540 # number of ReadReq hits 833system.cpu.icache.ReadReq_hits::total 3540 # number of ReadReq hits 834system.cpu.icache.demand_hits::cpu.inst 3540 # number of demand (read+write) hits 835system.cpu.icache.demand_hits::total 3540 # number of demand (read+write) hits 836system.cpu.icache.overall_hits::cpu.inst 3540 # number of overall hits 837system.cpu.icache.overall_hits::total 3540 # number of overall hits 838system.cpu.icache.ReadReq_misses::cpu.inst 361 # number of ReadReq misses 839system.cpu.icache.ReadReq_misses::total 361 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 898system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 899system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 900system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency 901system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency 902system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 903system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 904system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 905system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency |
| 906system.cpu.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 895system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 896system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 897system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 898system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 899system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 900system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing | 907system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 908system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 909system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 910system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 911system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 912system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 913system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 901system.cpu.l2cache.tags.replacements 0 # number of replacements 902system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use 903system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks. 904system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. 905system.cpu.l2cache.tags.avg_refs 0.229167 # Average number of references to valid blocks. 906system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 907system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor --- 5 unchanged lines hidden (view full) --- 914system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 915system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 918system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 919system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id 920system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses 921system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses | 914system.cpu.l2cache.tags.replacements 0 # number of replacements 915system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use 916system.cpu.l2cache.tags.total_refs 11 # Total number of references to valid blocks. 917system.cpu.l2cache.tags.sampled_refs 48 # Sample count of references to valid blocks. 918system.cpu.l2cache.tags.avg_refs 0.229167 # Average number of references to valid blocks. 919system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 920system.cpu.l2cache.tags.occ_blocks::writebacks 10.572819 # Average occupied blocks per requestor 921system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.233490 # Average occupied blocks per requestor --- 5 unchanged lines hidden (view full) --- 927system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 928system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 929system.cpu.l2cache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 930system.cpu.l2cache.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id 931system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 932system.cpu.l2cache.tags.occ_task_id_percent::1024 0.001953 # Percentage of cache occupancy per task id 933system.cpu.l2cache.tags.tag_accesses 7675 # Number of tag accesses 934system.cpu.l2cache.tags.data_accesses 7675 # Number of data accesses |
| 935system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 922system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 923system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 924system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 925system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 926system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 927system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits 928system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 929system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits --- 142 unchanged lines hidden (view full) --- 1072system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency 1074system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1075system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1076system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1077system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. 1078system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1079system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 936system.cpu.l2cache.WritebackClean_hits::writebacks 33 # number of WritebackClean hits 937system.cpu.l2cache.WritebackClean_hits::total 33 # number of WritebackClean hits 938system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 939system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 940system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 8 # number of ReadCleanReq hits 941system.cpu.l2cache.ReadCleanReq_hits::total 8 # number of ReadCleanReq hits 942system.cpu.l2cache.ReadSharedReq_hits::cpu.data 2 # number of ReadSharedReq hits 943system.cpu.l2cache.ReadSharedReq_hits::total 2 # number of ReadSharedReq hits --- 142 unchanged lines hidden (view full) --- 1086system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency 1087system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency 1088system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1089system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1090system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1091system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. 1092system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1093system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 1094system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 1080system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution 1082system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution 1083system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1084system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1085system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1086system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1087system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 1104system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1105system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram 1106system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) 1107system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1108system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) 1109system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1110system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1111system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) | 1095system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1096system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution 1097system.cpu.toL2Bus.trans_dist::CleanEvict 385 # Transaction distribution 1098system.cpu.toL2Bus.trans_dist::HardPFReq 69 # Transaction distribution 1099system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1100system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1101system.cpu.toL2Bus.trans_dist::ReadCleanReq 299 # Transaction distribution 1102system.cpu.toL2Bus.trans_dist::ReadSharedReq 103 # Transaction distribution --- 16 unchanged lines hidden (view full) --- 1119system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram 1120system.cpu.toL2Bus.snoop_fanout::total 897 # Request fanout histogram 1121system.cpu.toL2Bus.reqLayer0.occupancy 289000 # Layer occupancy (ticks) 1122system.cpu.toL2Bus.reqLayer0.utilization 1.5 # Layer utilization (%) 1123system.cpu.toL2Bus.respLayer0.occupancy 448999 # Layer occupancy (ticks) 1124system.cpu.toL2Bus.respLayer0.utilization 2.4 # Layer utilization (%) 1125system.cpu.toL2Bus.respLayer1.occupancy 216995 # Layer occupancy (ticks) 1126system.cpu.toL2Bus.respLayer1.utilization 1.2 # Layer utilization (%) |
| 1127system.membus.pwrStateResidencyTicks::UNDEFINED 18821000 # Cumulative time (in ticks) in various power states |
|
| 1112system.membus.trans_dist::ReadResp 412 # Transaction distribution 1113system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1114system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1115system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 1116system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) 1117system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) 1118system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) 1119system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 1128system.membus.trans_dist::ReadResp 412 # Transaction distribution 1129system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1130system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1131system.membus.trans_dist::ReadSharedReq 413 # Transaction distribution 1132system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 885 # Packet count per connected master and slave (bytes) 1133system.membus.pkt_count::total 885 # Packet count per connected master and slave (bytes) 1134system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28288 # Cumulative packet size per connected master and slave (bytes) 1135system.membus.pkt_size::total 28288 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |