| stats.txt (11440:76b5639162af) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18821000 # Number of ticks simulated 5final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18821000 # Number of ticks simulated 5final_tick 18821000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 9099 # Simulator instruction rate (inst/s) 8host_op_rate 10656 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 37131488 # Simulator tick rate (ticks/s) 10host_mem_usage 241712 # Number of bytes of host memory used 11host_seconds 0.50 # Real time elapsed on the host | 7host_inst_rate 49791 # Simulator instruction rate (inst/s) 8host_op_rate 58299 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 203978556 # Simulator tick rate (ticks/s) 10host_mem_usage 266084 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory --- 734 unchanged lines hidden (view full) --- 754system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency 755system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency 756system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 760system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked | 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18560 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8064 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 28352 # Number of bytes read from this memory --- 734 unchanged lines hidden (view full) --- 754system.cpu.dcache.overall_avg_miss_latency::cpu.data 51082.402235 # average overall miss latency 755system.cpu.dcache.overall_avg_miss_latency::total 51082.402235 # average overall miss latency 756system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.dcache.blocked_cycles::no_targets 818 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 760system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.dcache.avg_blocked_cycles::no_targets 45.444444 # average number of cycles each access was blocked |
| 762system.cpu.dcache.fast_writes 0 # number of fast writes performed 763system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 764system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 765system.cpu.dcache.writebacks::total 1 # number of writebacks 766system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 767system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 768system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 769system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 770system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 771system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 800system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency 801system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency 802system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency 803system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency 804system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 805system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 806system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 807system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency | 762system.cpu.dcache.writebacks::writebacks 1 # number of writebacks 763system.cpu.dcache.writebacks::total 1 # number of writebacks 764system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits 765system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits 766system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 767system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 768system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 769system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 28 unchanged lines hidden (view full) --- 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67320.388350 # average ReadReq mshr miss latency 799system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67320.388350 # average ReadReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59341.463415 # average WriteReq mshr miss latency 801system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59341.463415 # average WriteReq mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 803system.cpu.dcache.demand_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65048.611111 # average overall mshr miss latency 805system.cpu.dcache.overall_avg_mshr_miss_latency::total 65048.611111 # average overall mshr miss latency |
| 808system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 809system.cpu.icache.tags.replacements 44 # number of replacements 810system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use 811system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. 812system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. 813system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. 814system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 815system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor 816system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 858system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency 859system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency 860system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked 861system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 862system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked 863system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 864system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked 865system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked | 806system.cpu.icache.tags.replacements 44 # number of replacements 807system.cpu.icache.tags.tagsinuse 137.890102 # Cycle average of tags in use 808system.cpu.icache.tags.total_refs 3540 # Total number of references to valid blocks. 809system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. 810system.cpu.icache.tags.avg_refs 11.839465 # Average number of references to valid blocks. 811system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 812system.cpu.icache.tags.occ_blocks::cpu.inst 137.890102 # Average occupied blocks per requestor 813system.cpu.icache.tags.occ_percent::cpu.inst 0.269317 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 855system.cpu.icache.overall_avg_miss_latency::cpu.inst 62148.177285 # average overall miss latency 856system.cpu.icache.overall_avg_miss_latency::total 62148.177285 # average overall miss latency 857system.cpu.icache.blocked_cycles::no_mshrs 8414 # number of cycles access was blocked 858system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 859system.cpu.icache.blocked::no_mshrs 95 # number of cycles access was blocked 860system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 861system.cpu.icache.avg_blocked_cycles::no_mshrs 88.568421 # average number of cycles each access was blocked 862system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked |
| 866system.cpu.icache.fast_writes 0 # number of fast writes performed 867system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 868system.cpu.icache.writebacks::writebacks 44 # number of writebacks 869system.cpu.icache.writebacks::total 44 # number of writebacks 870system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits 871system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 872system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits 873system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 874system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits 875system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 892system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 893system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 894system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency 895system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency 896system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 897system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 898system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 899system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency | 863system.cpu.icache.writebacks::writebacks 44 # number of writebacks 864system.cpu.icache.writebacks::total 44 # number of writebacks 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 62 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 62 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 62 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 62 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 62 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 66140.441472 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 66140.441472 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 66140.441472 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 66140.441472 # average overall mshr miss latency |
| 900system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 901system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 902system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 903system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 904system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 905system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 906system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 907system.cpu.l2cache.tags.replacements 0 # number of replacements 908system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use --- 93 unchanged lines hidden (view full) --- 1002system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency 1003system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency 1004system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 1005system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1006system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1007system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1008system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1009system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 895system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 896system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 897system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 898system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 899system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 900system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 901system.cpu.l2cache.tags.replacements 0 # number of replacements 902system.cpu.l2cache.tags.tagsinuse 19.806308 # Cycle average of tags in use --- 93 unchanged lines hidden (view full) --- 996system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69156.488550 # average overall miss latency 997system.cpu.l2cache.overall_avg_miss_latency::total 67481.042654 # average overall miss latency 998system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 999system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 1000system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 1001system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1002system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1003system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 1010system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1011system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 1012system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1013system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1014system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1015system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1016system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1017system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1018system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1019system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits --- 54 unchanged lines hidden (view full) --- 1074system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency 1075system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1076system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1077system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency 1078system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1079system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1080system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency 1081system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency | 1004system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 1 # number of ReadCleanReq MSHR hits 1005system.cpu.l2cache.ReadCleanReq_mshr_hits::total 1 # number of ReadCleanReq MSHR hits 1006system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 5 # number of ReadSharedReq MSHR hits 1007system.cpu.l2cache.ReadSharedReq_mshr_hits::total 5 # number of ReadSharedReq MSHR hits 1008system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1009system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1010system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1011system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits --- 54 unchanged lines hidden (view full) --- 1066system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61375 # average ReadSharedReq mshr miss latency 1067system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1068system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1069system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61617.788462 # average overall mshr miss latency 1070system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60765.517241 # average overall mshr miss latency 1071system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63579.365079 # average overall mshr miss latency 1072system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 36017.471698 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58724.788913 # average overall mshr miss latency |
| 1082system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 1083system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1084system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1085system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1086system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. 1087system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1088system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1089system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1090system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution --- 55 unchanged lines hidden --- | 1074system.cpu.toL2Bus.snoop_filter.tot_requests 488 # Total number of requests made to the snoop filter. 1075system.cpu.toL2Bus.snoop_filter.hit_single_requests 74 # Number of requests hitting in the snoop filter with a single holder of the requested data. 1076system.cpu.toL2Bus.snoop_filter.hit_multi_requests 12 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 1077system.cpu.toL2Bus.snoop_filter.tot_snoops 411 # Total number of snoops made to the snoop filter. 1078system.cpu.toL2Bus.snoop_filter.hit_single_snoops 370 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 1079system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 41 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 1080system.cpu.toL2Bus.trans_dist::ReadResp 401 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::WritebackClean 45 # Transaction distribution --- 55 unchanged lines hidden --- |