| stats.txt (10892:bd37e25fb3b7) | stats.txt (10944:412eb87b1cfc) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 17777000 # Number of ticks simulated 5final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 17777000 # Number of ticks simulated 5final_tick 17777000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 63568 # Simulator instruction rate (inst/s) 8host_op_rate 74435 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 246000775 # Simulator tick rate (ticks/s) 10host_mem_usage 307848 # Number of bytes of host memory used | 7host_inst_rate 63242 # Simulator instruction rate (inst/s) 8host_op_rate 74054 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 244740900 # Simulator tick rate (ticks/s) 10host_mem_usage 307828 # Number of bytes of host memory used |
| 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory --- 70 unchanged lines hidden (view full) --- 89system.physmem.readPktSize::6 407 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) | 11host_seconds 0.07 # Real time elapsed on the host 12sim_insts 4592 # Number of instructions simulated 13sim_ops 5378 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory --- 70 unchanged lines hidden (view full) --- 89system.physmem.readPktSize::6 407 # Read request sizes (log2) 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 97system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see | 98system.physmem.rdQLenPdf::1 126 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see |
| 101system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see | 101system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see |
| 103system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see | 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see | 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see |
| 106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see | 106system.physmem.rdQLenPdf::9 2 # What read queue length does an incoming req see |
| 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see --- 84 unchanged lines hidden (view full) --- 199system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation | 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see --- 84 unchanged lines hidden (view full) --- 199system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation |
| 207system.physmem.totQLat 3256492 # Total ticks spent queuing 208system.physmem.totMemAccLat 10887742 # Total ticks spent from burst creation until serviced by the DRAM | 207system.physmem.totQLat 3130500 # Total ticks spent queuing 208system.physmem.totMemAccLat 10761750 # Total ticks spent from burst creation until serviced by the DRAM |
| 209system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers | 209system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers |
| 210system.physmem.avgQLat 8001.21 # Average queueing delay per DRAM burst | 210system.physmem.avgQLat 7691.65 # Average queueing delay per DRAM burst |
| 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.physmem.avgMemAccLat 26751.21 # Average memory access latency per DRAM burst | 212system.physmem.avgMemAccLat 26441.65 # Average memory access latency per DRAM burst |
| 213system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 11.45 # Data bus utilization in percentage 219system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 213system.physmem.avgRdBW 1465.26 # Average DRAM read bandwidth in MiByte/s 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 215system.physmem.avgRdBWSys 1465.26 # Average system read bandwidth in MiByte/s 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 218system.physmem.busUtil 11.45 # Data bus utilization in percentage 219system.physmem.busUtilRead 11.45 # Data bus utilization in percentage for reads 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 221system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 1.81 # Average read queue length when enqueuing |
| 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 340 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 43644.96 # Average gap between requests 228system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 340 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes 225system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 227system.physmem.avgGap 43644.96 # Average gap between requests 228system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 234system.physmem_0.actBackEnergy 10756755 # Energy for active background per rank (pJ) | 234system.physmem_0.actBackEnergy 10766160 # Energy for active background per rank (pJ) |
| 235system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) | 235system.physmem_0.preBackEnergy 63750 # Energy for precharge background per rank (pJ) |
| 236system.physmem_0.totalEnergy 14336940 # Total energy per rank (pJ) 237system.physmem_0.averagePower 905.538607 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 334000 # Time in different power states | 236system.physmem_0.totalEnergy 14346345 # Total energy per rank (pJ) 237system.physmem_0.averagePower 905.346375 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 321250 # Time in different power states |
| 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 241system.physmem_0.memoryStateTime::ACT 15275500 # Time in different power states | 241system.physmem_0.memoryStateTime::ACT 15288250 # Time in different power states |
| 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 248system.physmem_1.actBackEnergy 10156545 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 590250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12758160 # Total energy per rank (pJ) 251system.physmem_1.averagePower 805.820938 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 942000 # Time in different power states | 248system.physmem_1.actBackEnergy 10149705 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 596250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12757320 # Total energy per rank (pJ) 251system.physmem_1.averagePower 805.767883 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 952000 # Time in different power states |
| 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 255system.physmem_1.memoryStateTime::ACT 14384250 # Time in different power states | 255system.physmem_1.memoryStateTime::ACT 14374250 # Time in different power states |
| 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2336 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 442 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage --- 115 unchanged lines hidden (view full) --- 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls 384system.cpu.numCycles 35555 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2336 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1386 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 508 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 837 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 442 # Number of BTB hits 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 263system.cpu.branchPred.BTBHitPct 52.807646 # BTB Hit Percentage --- 115 unchanged lines hidden (view full) --- 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls 384system.cpu.numCycles 35555 # number of cpu cycles simulated 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 387system.cpu.fetch.icacheStallCycles 6172 # Number of cycles fetch is stalled on an Icache miss | 387system.cpu.fetch.icacheStallCycles 6171 # Number of cycles fetch is stalled on an Icache miss |
| 388system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken | 388system.cpu.fetch.Insts 11259 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 2336 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 731 # Number of branches that fetch has predicted taken |
| 391system.cpu.fetch.Cycles 7501 # Number of cycles fetch has run and was not squashing or blocked | 391system.cpu.fetch.Cycles 7640 # Number of cycles fetch has run and was not squashing or blocked |
| 392system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps 395system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched 397system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed | 392system.cpu.fetch.SquashCycles 1059 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 155 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps 395system.cpu.fetch.IcacheWaitRetryStallCycles 318 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 3825 # Number of cache lines fetched 397system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed |
| 398system.cpu.fetch.rateDist::samples 14978 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 0.878021 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.210560 # Number of instructions fetched each cycle (Total) | 398system.cpu.fetch.rateDist::samples 15116 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 0.870204 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.208015 # Number of instructions fetched each cycle (Total) |
| 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 402system.cpu.fetch.rateDist::0 8782 58.63% 58.63% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 2458 16.41% 75.04% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 521 3.48% 78.52% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 3217 21.48% 100.00% # Number of instructions fetched each cycle (Total) | 402system.cpu.fetch.rateDist::0 8919 59.00% 59.00% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 2458 16.26% 75.26% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 521 3.45% 78.71% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 3218 21.29% 100.00% # Number of instructions fetched each cycle (Total) |
| 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 409system.cpu.fetch.rateDist::total 14978 # Number of instructions fetched each cycle (Total) | 409system.cpu.fetch.rateDist::total 15116 # Number of instructions fetched each cycle (Total) |
| 410system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle | 410system.cpu.fetch.branchRate 0.065701 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.316664 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 5920 # Number of cycles decode is idle |
| 413system.cpu.decode.BlockedCycles 3520 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 5039 # Number of cycles decode is running | 413system.cpu.decode.BlockedCycles 3659 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 5038 # Number of cycles decode is running |
| 415system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction | 415system.cpu.decode.UnblockCycles 131 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 368 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction |
| 419system.cpu.decode.DecodedInsts 9859 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 1620 # Number of squashed instructions handled by decode | 419system.cpu.decode.DecodedInsts 9862 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 1622 # Number of squashed instructions handled by decode |
| 421system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle | 421system.cpu.rename.SquashCycles 368 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 6989 # Number of cycles rename is idle |
| 423system.cpu.rename.BlockCycles 960 # Number of cycles rename is blocking | 423system.cpu.rename.BlockCycles 961 # Number of cycles rename is blocking |
| 424system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst | 424system.cpu.rename.serializeStallCycles 1965 # count of cycles rename stalled for serializing inst |
| 425system.cpu.rename.RunCycles 4095 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 601 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 8880 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 409 # Number of squashed instructions processed by rename | 425system.cpu.rename.RunCycles 4094 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 739 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 8883 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 411 # Number of squashed instructions processed by rename |
| 429system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full | 429system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full |
| 432system.cpu.rename.SQFullEvents 527 # Number of times rename has blocked due to SQ full 433system.cpu.rename.RenamedOperands 9231 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 40283 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 9759 # Number of integer rename lookups | 432system.cpu.rename.SQFullEvents 665 # Number of times rename has blocked due to SQ full 433system.cpu.rename.RenamedOperands 9235 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 40294 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 9761 # Number of integer rename lookups |
| 436system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 436system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 438system.cpu.rename.UndoneMaps 3737 # Number of HB maps that are undone due to squashing | 438system.cpu.rename.UndoneMaps 3741 # Number of HB maps that are undone due to squashing |
| 439system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer | 439system.cpu.rename.serializingInsts 30 # count of serializing insts renamed 440system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer |
| 442system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. | 442system.cpu.memDep0.insertedLoads 1807 # Number of loads inserted to the mem dependence unit. |
| 443system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 443system.cpu.memDep0.insertedStores 1277 # Number of stores inserted to the mem dependence unit. 444system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 446system.cpu.iq.iqInstsAdded 8347 # Number of instructions added to the IQ (excludes non-spec) | 446system.cpu.iq.iqInstsAdded 8348 # Number of instructions added to the IQ (excludes non-spec) |
| 447system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ | 447system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ |
| 448system.cpu.iq.iqInstsIssued 7144 # Number of instructions issued | 448system.cpu.iq.iqInstsIssued 7146 # Number of instructions issued |
| 449system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued | 449system.cpu.iq.iqSquashedInstsIssued 184 # Number of squashed instructions issued |
| 450system.cpu.iq.iqSquashedInstsExamined 3008 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 7841 # Number of squashed operands that are examined and possibly removed from graph | 450system.cpu.iq.iqSquashedInstsExamined 3009 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 7843 # Number of squashed operands that are examined and possibly removed from graph |
| 452system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed | 452system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| 453system.cpu.iq.issued_per_cycle::samples 14978 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 0.476966 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 0.861224 # Number of insts issued each cycle | 453system.cpu.iq.issued_per_cycle::samples 15116 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 0.472744 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 0.858488 # Number of insts issued each cycle |
| 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 457system.cpu.iq.issued_per_cycle::0 10780 71.97% 71.97% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 1947 13.00% 84.97% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 1601 10.69% 95.66% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 605 4.04% 99.70% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::0 10916 72.21% 72.21% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 1949 12.89% 85.11% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 1601 10.59% 95.70% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 605 4.00% 99.70% # Number of insts issued each cycle |
| 461system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle | 461system.cpu.iq.issued_per_cycle::4 45 0.30% 100.00% # Number of insts issued each cycle 462system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::total 14978 # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::total 15116 # Number of insts issued each cycle |
| 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 471system.cpu.iq.fu_full::IntAlu 411 28.90% 28.90% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 28.90% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 28.90% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.90% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.90% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.90% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 28.90% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.90% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.90% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.90% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.90% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.90% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.90% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.90% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.90% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 28.90% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.90% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 28.90% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.90% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.90% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.90% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.90% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.90% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.90% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.90% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.90% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.90% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.90% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.90% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 464 32.63% 61.53% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 547 38.47% 100.00% # attempts to use FU when none available | 471system.cpu.iq.fu_full::IntAlu 412 28.93% 28.93% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 28.93% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 28.93% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.93% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.93% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.93% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 28.93% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.93% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.93% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.93% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.93% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.93% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.93% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.93% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.93% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 28.93% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.93% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 28.93% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.93% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.93% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.93% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.93% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.93% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.93% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.93% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.93% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.93% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.93% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.93% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 465 32.65% 61.59% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 547 38.41% 100.00% # attempts to use FU when none available |
| 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 505system.cpu.iq.FU_type_0::IntAlu 4467 62.53% 62.53% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.60% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.60% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.60% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.60% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.60% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.60% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.60% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.60% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.60% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.60% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.60% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.60% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.60% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.60% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.60% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.60% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.60% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.60% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.60% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.60% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.60% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.60% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.60% # Type of FU issued | 505system.cpu.iq.FU_type_0::IntAlu 4468 62.52% 62.52% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.59% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.59% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.59% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.59% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.59% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.59% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.59% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.59% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.59% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.59% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.59% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.59% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.59% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.59% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.59% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.59% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.59% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.59% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.59% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.59% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.59% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.59% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.59% # Type of FU issued |
| 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued | 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.64% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.64% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.64% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.64% # Type of FU issued |
| 534system.cpu.iq.FU_type_0::MemRead 1588 22.23% 84.87% # Type of FU issued | 534system.cpu.iq.FU_type_0::MemRead 1589 22.24% 84.87% # Type of FU issued |
| 535system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 535system.cpu.iq.FU_type_0::MemWrite 1081 15.13% 100.00% # Type of FU issued 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::total 7144 # Type of FU issued 539system.cpu.iq.rate 0.200928 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 1422 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.199048 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 30828 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 11385 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses | 538system.cpu.iq.FU_type_0::total 7146 # Type of FU issued 539system.cpu.iq.rate 0.200984 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 1424 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.199272 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 30972 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 11387 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 6551 # Number of integer instruction queue wakeup accesses |
| 545system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 545system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads 546system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 548system.cpu.iq.int_alu_accesses 8538 # Number of integer alu accesses | 548system.cpu.iq.int_alu_accesses 8542 # Number of integer alu accesses |
| 549system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 549system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 552system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed | 552system.cpu.iew.lsq.thread0.squashedLoads 780 # Number of loads squashed |
| 553system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 558system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 561system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing | 553system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 555system.cpu.iew.lsq.thread0.squashedStores 339 # Number of stores squashed 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 558system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 561system.cpu.iew.iewSquashCycles 368 # Number of cycles IEW is squashing |
| 562system.cpu.iew.iewBlockCycles 356 # Number of cycles IEW is blocking | 562system.cpu.iew.iewBlockCycles 357 # Number of cycles IEW is blocking |
| 563system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking | 563system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking |
| 564system.cpu.iew.iewDispatchedInsts 8400 # Number of instructions dispatched to IQ | 564system.cpu.iew.iewDispatchedInsts 8401 # Number of instructions dispatched to IQ |
| 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 566system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions | 566system.cpu.iew.iewDispLoadInsts 1807 # Number of dispatched load instructions |
| 567system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute | 567system.cpu.iew.iewDispStoreInsts 1277 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 6 # Number of times the LSQ has become full, causing a stall 571system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 572system.cpu.iew.predictedTakenIncorrect 67 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 361 # Number of branch mispredicts detected at execute |
| 575system.cpu.iew.iewExecutedInsts 6741 # Number of executed instructions | 575system.cpu.iew.iewExecutedInsts 6742 # Number of executed instructions |
| 576system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed | 576system.cpu.iew.iewExecLoadInsts 1404 # Number of load instructions executed |
| 577system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute | 577system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute |
| 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 14 # number of nop insts executed 580system.cpu.iew.exec_refs 2427 # number of memory reference insts executed 581system.cpu.iew.exec_branches 1272 # Number of branches executed 582system.cpu.iew.exec_stores 1023 # Number of stores executed | 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 14 # number of nop insts executed 580system.cpu.iew.exec_refs 2427 # number of memory reference insts executed 581system.cpu.iew.exec_branches 1272 # Number of branches executed 582system.cpu.iew.exec_stores 1023 # Number of stores executed |
| 583system.cpu.iew.exec_rate 0.189594 # Inst execution rate 584system.cpu.iew.wb_sent 6608 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 6566 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 2973 # num instructions producing a value 587system.cpu.iew.wb_consumers 5368 # num instructions consuming a value | 583system.cpu.iew.exec_rate 0.189622 # Inst execution rate 584system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 6567 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 2975 # num instructions producing a value 587system.cpu.iew.wb_consumers 5372 # num instructions consuming a value |
| 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 589system.cpu.iew.wb_rate 0.184672 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.553838 # average fanout of values written-back | 589system.cpu.iew.wb_rate 0.184700 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.553797 # average fanout of values written-back |
| 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 592system.cpu.commit.commitSquashedInsts 2565 # The number of squashed insts skipped by commit | 592system.cpu.commit.commitSquashedInsts 2568 # The number of squashed insts skipped by commit |
| 593system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted | 593system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards 594system.cpu.commit.branchMispredicts 347 # The number of times a branch was mispredicted |
| 595system.cpu.commit.committed_per_cycle::samples 14437 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.372515 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.021269 # Number of insts commited each cycle | 595system.cpu.commit.committed_per_cycle::samples 14574 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.369013 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.017093 # Number of insts commited each cycle |
| 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 599system.cpu.commit.committed_per_cycle::0 11787 81.64% 81.64% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 1388 9.61% 91.26% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 602 4.17% 95.43% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 293 2.03% 97.46% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 168 1.16% 98.62% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 78 0.54% 99.16% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 45 0.31% 99.47% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 11924 81.82% 81.82% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 1388 9.52% 91.34% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 602 4.13% 95.47% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 293 2.01% 97.48% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 168 1.15% 98.63% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 78 0.54% 99.17% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 45 0.31% 99.48% # Number of insts commited each cycle |
| 606system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 606system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 611system.cpu.commit.committed_per_cycle::total 14437 # Number of insts commited each cycle | 611system.cpu.commit.committed_per_cycle::total 14574 # Number of insts commited each cycle |
| 612system.cpu.commit.committedInsts 4592 # Number of instructions committed 613system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 1965 # Number of memory references committed 616system.cpu.commit.loads 1027 # Number of loads committed 617system.cpu.commit.membars 12 # Number of memory barriers committed 618system.cpu.commit.branches 1008 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 657system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached | 612system.cpu.commit.committedInsts 4592 # Number of instructions committed 613system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 1965 # Number of memory references committed 616system.cpu.commit.loads 1027 # Number of loads committed 617system.cpu.commit.membars 12 # Number of memory barriers committed 618system.cpu.commit.branches 1008 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 30 unchanged lines hidden (view full) --- 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5378 # Class of committed instruction 657system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached |
| 658system.cpu.rob.rob_reads 22180 # The number of ROB reads 659system.cpu.rob.rob_writes 16432 # The number of ROB writes | 658system.cpu.rob.rob_reads 22320 # The number of ROB reads 659system.cpu.rob.rob_writes 16439 # The number of ROB writes |
| 660system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself | 660system.cpu.timesIdled 214 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 661system.cpu.idleCycles 20577 # Total number of cycles that the CPU has spent unscheduled due to idling | 661system.cpu.idleCycles 20439 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 662system.cpu.committedInsts 4592 # Number of Instructions Simulated 663system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 664system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads 666system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle 667system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads | 662system.cpu.committedInsts 4592 # Number of Instructions Simulated 663system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated 664system.cpu.cpi 7.742814 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 7.742814 # CPI: Total CPI of All Threads 666system.cpu.ipc 0.129152 # IPC: Instructions Per Cycle 667system.cpu.ipc_total 0.129152 # IPC: Total IPC of All Threads |
| 668system.cpu.int_regfile_reads 6717 # number of integer regfile reads | 668system.cpu.int_regfile_reads 6718 # number of integer regfile reads |
| 669system.cpu.int_regfile_writes 3745 # number of integer regfile writes 670system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 669system.cpu.int_regfile_writes 3745 # number of integer regfile writes 670system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 671system.cpu.cc_regfile_reads 23956 # number of cc regfile reads 672system.cpu.cc_regfile_writes 2895 # number of cc regfile writes | 671system.cpu.cc_regfile_reads 23959 # number of cc regfile reads 672system.cpu.cc_regfile_writes 2898 # number of cc regfile writes |
| 673system.cpu.misc_regfile_reads 2607 # number of misc regfile reads 674system.cpu.misc_regfile_writes 24 # number of misc regfile writes 675system.cpu.dcache.tags.replacements 1 # number of replacements | 673system.cpu.misc_regfile_reads 2607 # number of misc regfile reads 674system.cpu.misc_regfile_writes 24 # number of misc regfile writes 675system.cpu.dcache.tags.replacements 1 # number of replacements |
| 676system.cpu.dcache.tags.tagsinuse 84.382295 # Cycle average of tags in use | 676system.cpu.dcache.tags.tagsinuse 84.292966 # Cycle average of tags in use |
| 677system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. 678system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 679system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. 680system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 677system.cpu.dcache.tags.total_refs 1915 # Total number of references to valid blocks. 678system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 679system.cpu.dcache.tags.avg_refs 13.485915 # Average number of references to valid blocks. 680system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 681system.cpu.dcache.tags.occ_blocks::cpu.data 84.382295 # Average occupied blocks per requestor 682system.cpu.dcache.tags.occ_percent::cpu.data 0.164809 # Average percentage of cache occupancy 683system.cpu.dcache.tags.occ_percent::total 0.164809 # Average percentage of cache occupancy | 681system.cpu.dcache.tags.occ_blocks::cpu.data 84.292966 # Average occupied blocks per requestor 682system.cpu.dcache.tags.occ_percent::cpu.data 0.164635 # Average percentage of cache occupancy 683system.cpu.dcache.tags.occ_percent::total 0.164635 # Average percentage of cache occupancy |
| 684system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 685system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 687system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id 688system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses 689system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses 690system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits 691system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits --- 14 unchanged lines hidden (view full) --- 706system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 707system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 708system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses 709system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses 710system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses 711system.cpu.dcache.overall_misses::total 358 # number of overall misses 712system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles 713system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles | 684system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 685system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id 687system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id 688system.cpu.dcache.tags.tag_accesses 4692 # Number of tag accesses 689system.cpu.dcache.tags.data_accesses 4692 # Number of data accesses 690system.cpu.dcache.ReadReq_hits::cpu.data 1173 # number of ReadReq hits 691system.cpu.dcache.ReadReq_hits::total 1173 # number of ReadReq hits --- 14 unchanged lines hidden (view full) --- 706system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 707system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 708system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses 709system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses 710system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses 711system.cpu.dcache.overall_misses::total 358 # number of overall misses 712system.cpu.dcache.ReadReq_miss_latency::cpu.data 9199500 # number of ReadReq miss cycles 713system.cpu.dcache.ReadReq_miss_latency::total 9199500 # number of ReadReq miss cycles |
| 714system.cpu.dcache.WriteReq_miss_latency::cpu.data 7245500 # number of WriteReq miss cycles 715system.cpu.dcache.WriteReq_miss_latency::total 7245500 # number of WriteReq miss cycles | 714system.cpu.dcache.WriteReq_miss_latency::cpu.data 7717500 # number of WriteReq miss cycles 715system.cpu.dcache.WriteReq_miss_latency::total 7717500 # number of WriteReq miss cycles |
| 716system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles 717system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles | 716system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 125000 # number of LoadLockedReq miss cycles 717system.cpu.dcache.LoadLockedReq_miss_latency::total 125000 # number of LoadLockedReq miss cycles |
| 718system.cpu.dcache.demand_miss_latency::cpu.data 16445000 # number of demand (read+write) miss cycles 719system.cpu.dcache.demand_miss_latency::total 16445000 # number of demand (read+write) miss cycles 720system.cpu.dcache.overall_miss_latency::cpu.data 16445000 # number of overall miss cycles 721system.cpu.dcache.overall_miss_latency::total 16445000 # number of overall miss cycles | 718system.cpu.dcache.demand_miss_latency::cpu.data 16917000 # number of demand (read+write) miss cycles 719system.cpu.dcache.demand_miss_latency::total 16917000 # number of demand (read+write) miss cycles 720system.cpu.dcache.overall_miss_latency::cpu.data 16917000 # number of overall miss cycles 721system.cpu.dcache.overall_miss_latency::total 16917000 # number of overall miss cycles |
| 722system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) 723system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 738system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 739system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 740system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses 741system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses 742system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses 743system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency 745system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency | 722system.cpu.dcache.ReadReq_accesses::cpu.data 1340 # number of ReadReq accesses(hits+misses) 723system.cpu.dcache.ReadReq_accesses::total 1340 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) --- 8 unchanged lines hidden (view full) --- 738system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 739system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 740system.cpu.dcache.demand_miss_rate::cpu.data 0.158899 # miss rate for demand accesses 741system.cpu.dcache.demand_miss_rate::total 0.158899 # miss rate for demand accesses 742system.cpu.dcache.overall_miss_rate::cpu.data 0.158899 # miss rate for overall accesses 743system.cpu.dcache.overall_miss_rate::total 0.158899 # miss rate for overall accesses 744system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55086.826347 # average ReadReq miss latency 745system.cpu.dcache.ReadReq_avg_miss_latency::total 55086.826347 # average ReadReq miss latency |
| 746system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37934.554974 # average WriteReq miss latency 747system.cpu.dcache.WriteReq_avg_miss_latency::total 37934.554974 # average WriteReq miss latency | 746system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 40405.759162 # average WriteReq miss latency 747system.cpu.dcache.WriteReq_avg_miss_latency::total 40405.759162 # average WriteReq miss latency |
| 748system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency | 748system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 62500 # average LoadLockedReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 62500 # average LoadLockedReq miss latency |
| 750system.cpu.dcache.demand_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency 751system.cpu.dcache.demand_avg_miss_latency::total 45935.754190 # average overall miss latency 752system.cpu.dcache.overall_avg_miss_latency::cpu.data 45935.754190 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::total 45935.754190 # average overall miss latency | 750system.cpu.dcache.demand_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency 751system.cpu.dcache.demand_avg_miss_latency::total 47254.189944 # average overall miss latency 752system.cpu.dcache.overall_avg_miss_latency::cpu.data 47254.189944 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::total 47254.189944 # average overall miss latency |
| 754system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 754system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 755system.cpu.dcache.blocked_cycles::no_targets 731 # number of cycles access was blocked | 755system.cpu.dcache.blocked_cycles::no_targets 829 # number of cycles access was blocked |
| 756system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 757system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 758system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 756system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 757system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 758system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 759system.cpu.dcache.avg_blocked_cycles::no_targets 40.611111 # average number of cycles each access was blocked | 759system.cpu.dcache.avg_blocked_cycles::no_targets 46.055556 # average number of cycles each access was blocked |
| 760system.cpu.dcache.fast_writes 0 # number of fast writes performed 761system.cpu.dcache.cache_copies 0 # number of cache copies performed 762system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits 763system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 764system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 765system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 766system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 767system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 6 unchanged lines hidden (view full) --- 774system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 776system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 777system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 778system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 779system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses 780system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles | 760system.cpu.dcache.fast_writes 0 # number of fast writes performed 761system.cpu.dcache.cache_copies 0 # number of cache copies performed 762system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits 763system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 764system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 765system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 766system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 767system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits --- 6 unchanged lines hidden (view full) --- 774system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 776system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 777system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 778system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 779system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses 780system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5829500 # number of ReadReq MSHR miss cycles 781system.cpu.dcache.ReadReq_mshr_miss_latency::total 5829500 # number of ReadReq MSHR miss cycles |
| 782system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2385500 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::total 2385500 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8215000 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::total 8215000 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8215000 # number of overall MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::total 8215000 # number of overall MSHR miss cycles | 782system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2454500 # number of WriteReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::total 2454500 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8284000 # number of demand (read+write) MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::total 8284000 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8284000 # number of overall MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::total 8284000 # number of overall MSHR miss cycles |
| 788system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for demand accesses 793system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses 794system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses 795system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency | 788system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076119 # mshr miss rate for ReadReq accesses 789system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076119 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for demand accesses 793system.cpu.dcache.demand_mshr_miss_rate::total 0.063471 # mshr miss rate for demand accesses 794system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063471 # mshr miss rate for overall accesses 795system.cpu.dcache.overall_mshr_miss_rate::total 0.063471 # mshr miss rate for overall accesses 796system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 57151.960784 # average ReadReq mshr miss latency 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 57151.960784 # average ReadReq mshr miss latency |
| 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 58182.926829 # average WriteReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 58182.926829 # average WriteReq mshr miss latency 800system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency 802system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57447.552448 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::total 57447.552448 # average overall mshr miss latency | 798system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59865.853659 # average WriteReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59865.853659 # average WriteReq mshr miss latency 800system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency 802system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57930.069930 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::total 57930.069930 # average overall mshr miss latency |
| 804system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu.icache.tags.replacements 42 # number of replacements | 804system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu.icache.tags.replacements 42 # number of replacements |
| 806system.cpu.icache.tags.tagsinuse 136.424572 # Cycle average of tags in use | 806system.cpu.icache.tags.tagsinuse 136.256883 # Cycle average of tags in use |
| 807system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. 808system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 809system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. 810system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 807system.cpu.icache.tags.total_refs 3459 # Total number of references to valid blocks. 808system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 809system.cpu.icache.tags.avg_refs 11.725424 # Average number of references to valid blocks. 810system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 811system.cpu.icache.tags.occ_blocks::cpu.inst 136.424572 # Average occupied blocks per requestor 812system.cpu.icache.tags.occ_percent::cpu.inst 0.266454 # Average percentage of cache occupancy 813system.cpu.icache.tags.occ_percent::total 0.266454 # Average percentage of cache occupancy | 811system.cpu.icache.tags.occ_blocks::cpu.inst 136.256883 # Average occupied blocks per requestor 812system.cpu.icache.tags.occ_percent::cpu.inst 0.266127 # Average percentage of cache occupancy 813system.cpu.icache.tags.occ_percent::total 0.266127 # Average percentage of cache occupancy |
| 814system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id | 814system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id |
| 815system.cpu.icache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::1 92 # Occupied blocks per task id | 815system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id |
| 817system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 818system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses 819system.cpu.icache.tags.data_accesses 7941 # Number of data accesses 820system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits 821system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits 822system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits 823system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits 824system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits 825system.cpu.icache.overall_hits::total 3459 # number of overall hits 826system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 827system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 828system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 829system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 830system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 831system.cpu.icache.overall_misses::total 364 # number of overall misses | 817system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 818system.cpu.icache.tags.tag_accesses 7941 # Number of tag accesses 819system.cpu.icache.tags.data_accesses 7941 # Number of data accesses 820system.cpu.icache.ReadReq_hits::cpu.inst 3459 # number of ReadReq hits 821system.cpu.icache.ReadReq_hits::total 3459 # number of ReadReq hits 822system.cpu.icache.demand_hits::cpu.inst 3459 # number of demand (read+write) hits 823system.cpu.icache.demand_hits::total 3459 # number of demand (read+write) hits 824system.cpu.icache.overall_hits::cpu.inst 3459 # number of overall hits 825system.cpu.icache.overall_hits::total 3459 # number of overall hits 826system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 827system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 828system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 829system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 830system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 831system.cpu.icache.overall_misses::total 364 # number of overall misses |
| 832system.cpu.icache.ReadReq_miss_latency::cpu.inst 21691493 # number of ReadReq miss cycles 833system.cpu.icache.ReadReq_miss_latency::total 21691493 # number of ReadReq miss cycles 834system.cpu.icache.demand_miss_latency::cpu.inst 21691493 # number of demand (read+write) miss cycles 835system.cpu.icache.demand_miss_latency::total 21691493 # number of demand (read+write) miss cycles 836system.cpu.icache.overall_miss_latency::cpu.inst 21691493 # number of overall miss cycles 837system.cpu.icache.overall_miss_latency::total 21691493 # number of overall miss cycles | 832system.cpu.icache.ReadReq_miss_latency::cpu.inst 21567493 # number of ReadReq miss cycles 833system.cpu.icache.ReadReq_miss_latency::total 21567493 # number of ReadReq miss cycles 834system.cpu.icache.demand_miss_latency::cpu.inst 21567493 # number of demand (read+write) miss cycles 835system.cpu.icache.demand_miss_latency::total 21567493 # number of demand (read+write) miss cycles 836system.cpu.icache.overall_miss_latency::cpu.inst 21567493 # number of overall miss cycles 837system.cpu.icache.overall_miss_latency::total 21567493 # number of overall miss cycles |
| 838system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) 839system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) 840system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses 841system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses 842system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses 843system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses 844system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses 845system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses 846system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses 847system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses 848system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses 849system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses | 838system.cpu.icache.ReadReq_accesses::cpu.inst 3823 # number of ReadReq accesses(hits+misses) 839system.cpu.icache.ReadReq_accesses::total 3823 # number of ReadReq accesses(hits+misses) 840system.cpu.icache.demand_accesses::cpu.inst 3823 # number of demand (read+write) accesses 841system.cpu.icache.demand_accesses::total 3823 # number of demand (read+write) accesses 842system.cpu.icache.overall_accesses::cpu.inst 3823 # number of overall (read+write) accesses 843system.cpu.icache.overall_accesses::total 3823 # number of overall (read+write) accesses 844system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.095213 # miss rate for ReadReq accesses 845system.cpu.icache.ReadReq_miss_rate::total 0.095213 # miss rate for ReadReq accesses 846system.cpu.icache.demand_miss_rate::cpu.inst 0.095213 # miss rate for demand accesses 847system.cpu.icache.demand_miss_rate::total 0.095213 # miss rate for demand accesses 848system.cpu.icache.overall_miss_rate::cpu.inst 0.095213 # miss rate for overall accesses 849system.cpu.icache.overall_miss_rate::total 0.095213 # miss rate for overall accesses |
| 850system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59592.013736 # average ReadReq miss latency 851system.cpu.icache.ReadReq_avg_miss_latency::total 59592.013736 # average ReadReq miss latency 852system.cpu.icache.demand_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency 853system.cpu.icache.demand_avg_miss_latency::total 59592.013736 # average overall miss latency 854system.cpu.icache.overall_avg_miss_latency::cpu.inst 59592.013736 # average overall miss latency 855system.cpu.icache.overall_avg_miss_latency::total 59592.013736 # average overall miss latency 856system.cpu.icache.blocked_cycles::no_mshrs 8521 # number of cycles access was blocked | 850system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59251.354396 # average ReadReq miss latency 851system.cpu.icache.ReadReq_avg_miss_latency::total 59251.354396 # average ReadReq miss latency 852system.cpu.icache.demand_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency 853system.cpu.icache.demand_avg_miss_latency::total 59251.354396 # average overall miss latency 854system.cpu.icache.overall_avg_miss_latency::cpu.inst 59251.354396 # average overall miss latency 855system.cpu.icache.overall_avg_miss_latency::total 59251.354396 # average overall miss latency 856system.cpu.icache.blocked_cycles::no_mshrs 8431 # number of cycles access was blocked |
| 857system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 858system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked 859system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked | 857system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 858system.cpu.icache.blocked::no_mshrs 89 # number of cycles access was blocked 859system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 860system.cpu.icache.avg_blocked_cycles::no_mshrs 95.741573 # average number of cycles each access was blocked | 860system.cpu.icache.avg_blocked_cycles::no_mshrs 94.730337 # average number of cycles each access was blocked |
| 861system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked 862system.cpu.icache.fast_writes 0 # number of fast writes performed 863system.cpu.icache.cache_copies 0 # number of cache copies performed 864system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 865system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 866system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 867system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 868system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 869system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 870system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 871system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 872system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 873system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 874system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 875system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses | 861system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked 862system.cpu.icache.fast_writes 0 # number of fast writes performed 863system.cpu.icache.cache_copies 0 # number of cache copies performed 864system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 865system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 866system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 867system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 868system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 869system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 870system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 871system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 872system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 873system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 874system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 875system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses |
| 876system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18899993 # number of ReadReq MSHR miss cycles 877system.cpu.icache.ReadReq_mshr_miss_latency::total 18899993 # number of ReadReq MSHR miss cycles 878system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18899993 # number of demand (read+write) MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::total 18899993 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18899993 # number of overall MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::total 18899993 # number of overall MSHR miss cycles | 876system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18780993 # number of ReadReq MSHR miss cycles 877system.cpu.icache.ReadReq_mshr_miss_latency::total 18780993 # number of ReadReq MSHR miss cycles 878system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18780993 # number of demand (read+write) MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::total 18780993 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18780993 # number of overall MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::total 18780993 # number of overall MSHR miss cycles |
| 882system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses 883system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses 884system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses 885system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses 886system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses 887system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses | 882system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for ReadReq accesses 883system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077426 # mshr miss rate for ReadReq accesses 884system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for demand accesses 885system.cpu.icache.demand_mshr_miss_rate::total 0.077426 # mshr miss rate for demand accesses 886system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077426 # mshr miss rate for overall accesses 887system.cpu.icache.overall_mshr_miss_rate::total 0.077426 # mshr miss rate for overall accesses |
| 888system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63851.327703 # average ReadReq mshr miss latency 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63851.327703 # average ReadReq mshr miss latency 890system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency 892system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63851.327703 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::total 63851.327703 # average overall mshr miss latency | 888system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63449.300676 # average ReadReq mshr miss latency 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63449.300676 # average ReadReq mshr miss latency 890system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency 892system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63449.300676 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::total 63449.300676 # average overall mshr miss latency |
| 894system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 895system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 896system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 897system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 898system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 899system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 900system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 901system.cpu.l2cache.tags.replacements 0 # number of replacements | 894system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 895system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 896system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 897system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 898system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 899system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 900system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 901system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 902system.cpu.l2cache.tags.tagsinuse 193.028614 # Cycle average of tags in use | 902system.cpu.l2cache.tags.tagsinuse 192.829480 # Cycle average of tags in use |
| 903system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. 904system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. 905system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. 906system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 903system.cpu.l2cache.tags.total_refs 74 # Total number of references to valid blocks. 904system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. 905system.cpu.l2cache.tags.avg_refs 0.203297 # Average number of references to valid blocks. 906system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 907system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.716720 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.data 45.124038 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.187855 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008467 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.data 0.002754 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000561 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::total 0.011782 # Average percentage of cache occupancy | 907system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.531593 # Average occupied blocks per requestor 908system.cpu.l2cache.tags.occ_blocks::cpu.data 45.093662 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.204225 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008455 # Average percentage of cache occupancy 911system.cpu.l2cache.tags.occ_percent::cpu.data 0.002752 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::total 0.011769 # Average percentage of cache occupancy |
| 914system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 915system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id | 914system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 915system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 916system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id |
| 918system.cpu.l2cache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id | 918system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id |
| 920system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 921system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id 922system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses 923system.cpu.l2cache.tags.data_accesses 7941 # Number of data accesses 924system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 925system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 926system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 23 # number of ReadCleanReq hits 927system.cpu.l2cache.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 940system.cpu.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 941system.cpu.l2cache.ReadSharedReq_misses::total 83 # number of ReadSharedReq misses 942system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 943system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses 944system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses 945system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 946system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses 947system.cpu.l2cache.overall_misses::total 386 # number of overall misses | 920system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 921system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id 922system.cpu.l2cache.tags.tag_accesses 7941 # Number of tag accesses 923system.cpu.l2cache.tags.data_accesses 7941 # Number of data accesses 924system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 925system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 926system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 23 # number of ReadCleanReq hits 927system.cpu.l2cache.ReadCleanReq_hits::total 23 # number of ReadCleanReq hits --- 12 unchanged lines hidden (view full) --- 940system.cpu.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses 941system.cpu.l2cache.ReadSharedReq_misses::total 83 # number of ReadSharedReq misses 942system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses 943system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses 944system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses 945system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses 946system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses 947system.cpu.l2cache.overall_misses::total 386 # number of overall misses |
| 948system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2251000 # number of ReadExReq miss cycles 949system.cpu.l2cache.ReadExReq_miss_latency::total 2251000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18451000 # number of ReadCleanReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::total 18451000 # number of ReadCleanReq miss cycles | 948system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2320000 # number of ReadExReq miss cycles 949system.cpu.l2cache.ReadExReq_miss_latency::total 2320000 # number of ReadExReq miss cycles 950system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 18332000 # number of ReadCleanReq miss cycles 951system.cpu.l2cache.ReadCleanReq_miss_latency::total 18332000 # number of ReadCleanReq miss cycles |
| 952system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles | 952system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5549000 # number of ReadSharedReq miss cycles 953system.cpu.l2cache.ReadSharedReq_miss_latency::total 5549000 # number of ReadSharedReq miss cycles |
| 954system.cpu.l2cache.demand_miss_latency::cpu.inst 18451000 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.data 7800000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::total 26251000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.inst 18451000 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.data 7800000 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::total 26251000 # number of overall miss cycles | 954system.cpu.l2cache.demand_miss_latency::cpu.inst 18332000 # number of demand (read+write) miss cycles 955system.cpu.l2cache.demand_miss_latency::cpu.data 7869000 # number of demand (read+write) miss cycles 956system.cpu.l2cache.demand_miss_latency::total 26201000 # number of demand (read+write) miss cycles 957system.cpu.l2cache.overall_miss_latency::cpu.inst 18332000 # number of overall miss cycles 958system.cpu.l2cache.overall_miss_latency::cpu.data 7869000 # number of overall miss cycles 959system.cpu.l2cache.overall_miss_latency::total 26201000 # number of overall miss cycles |
| 960system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) 963system.cpu.l2cache.ReadCleanReq_accesses::total 296 # number of ReadCleanReq accesses(hits+misses) 964system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 102 # number of ReadSharedReq accesses(hits+misses) 965system.cpu.l2cache.ReadSharedReq_accesses::total 102 # number of ReadSharedReq accesses(hits+misses) 966system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 967system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 976system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.813725 # miss rate for ReadSharedReq accesses 977system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.813725 # miss rate for ReadSharedReq accesses 978system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses 979system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses 980system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses 981system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses 982system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses 983system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses | 960system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 296 # number of ReadCleanReq accesses(hits+misses) 963system.cpu.l2cache.ReadCleanReq_accesses::total 296 # number of ReadCleanReq accesses(hits+misses) 964system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 102 # number of ReadSharedReq accesses(hits+misses) 965system.cpu.l2cache.ReadSharedReq_accesses::total 102 # number of ReadSharedReq accesses(hits+misses) 966system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses 967system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses --- 8 unchanged lines hidden (view full) --- 976system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.813725 # miss rate for ReadSharedReq accesses 977system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.813725 # miss rate for ReadSharedReq accesses 978system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses 979system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses 980system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses 981system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses 982system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses 983system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses |
| 984system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75033.333333 # average ReadExReq miss latency 985system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75033.333333 # average ReadExReq miss latency 986system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67586.080586 # average ReadCleanReq miss latency 987system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67586.080586 # average ReadCleanReq miss latency | 984system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77333.333333 # average ReadExReq miss latency 985system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77333.333333 # average ReadExReq miss latency 986system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 67150.183150 # average ReadCleanReq miss latency 987system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 67150.183150 # average ReadCleanReq miss latency |
| 988system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency 989system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency | 988system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 66855.421687 # average ReadSharedReq miss latency 989system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 66855.421687 # average ReadSharedReq miss latency |
| 990system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency 991system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency 992system.cpu.l2cache.demand_avg_miss_latency::total 68007.772021 # average overall miss latency 993system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67586.080586 # average overall miss latency 994system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69026.548673 # average overall miss latency 995system.cpu.l2cache.overall_avg_miss_latency::total 68007.772021 # average overall miss latency | 990system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency 991system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency 992system.cpu.l2cache.demand_avg_miss_latency::total 67878.238342 # average overall miss latency 993system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67150.183150 # average overall miss latency 994system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69637.168142 # average overall miss latency 995system.cpu.l2cache.overall_avg_miss_latency::total 67878.238342 # average overall miss latency |
| 996system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 997system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 998system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 999system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1000system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1001system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1002system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1003system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 1021system.cpu.l2cache.ReadSharedReq_mshr_misses::total 78 # number of ReadSharedReq MSHR misses 1022system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 1023system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses 1024system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses 1025system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 1026system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 1027system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses 1028system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses | 996system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 997system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 998system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 999system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 1000system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 1001system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 1002system.cpu.l2cache.fast_writes 0 # number of fast writes performed 1003system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 1021system.cpu.l2cache.ReadSharedReq_mshr_misses::total 78 # number of ReadSharedReq MSHR misses 1022system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses 1023system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses 1024system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses 1025system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses 1026system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 1027system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses 1028system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses |
| 1029system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of HardPFReq MSHR miss cycles 1030system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1697924 # number of HardPFReq MSHR miss cycles 1031system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071000 # number of ReadExReq MSHR miss cycles 1032system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071000 # number of ReadExReq MSHR miss cycles 1033system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16769500 # number of ReadCleanReq MSHR miss cycles 1034system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16769500 # number of ReadCleanReq MSHR miss cycles | 1029system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of HardPFReq MSHR miss cycles 1030system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1625926 # number of HardPFReq MSHR miss cycles 1031system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2140000 # number of ReadExReq MSHR miss cycles 1032system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2140000 # number of ReadExReq MSHR miss cycles 1033system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 16650500 # number of ReadCleanReq MSHR miss cycles 1034system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 16650500 # number of ReadCleanReq MSHR miss cycles |
| 1035system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles 1036system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles | 1035system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4788500 # number of ReadSharedReq MSHR miss cycles 1036system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4788500 # number of ReadSharedReq MSHR miss cycles |
| 1037system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16769500 # number of demand (read+write) MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6859500 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::total 23629000 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16769500 # number of overall MSHR miss cycles 1041system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6859500 # number of overall MSHR miss cycles 1042system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1697924 # number of overall MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::total 25326924 # number of overall MSHR miss cycles | 1037system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16650500 # number of demand (read+write) MSHR miss cycles 1038system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6928500 # number of demand (read+write) MSHR miss cycles 1039system.cpu.l2cache.demand_mshr_miss_latency::total 23579000 # number of demand (read+write) MSHR miss cycles 1040system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16650500 # number of overall MSHR miss cycles 1041system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6928500 # number of overall MSHR miss cycles 1042system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1625926 # number of overall MSHR miss cycles 1043system.cpu.l2cache.overall_mshr_miss_latency::total 25204926 # number of overall MSHR miss cycles |
| 1044system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1045system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1046system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1047system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1048system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses 1049system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses 1050system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses 1051system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses 1052system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses 1053system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses 1054system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses 1055system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses 1056system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses 1057system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1058system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses | 1044system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1045system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1046system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1047system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1048system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadCleanReq accesses 1049system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.918919 # mshr miss rate for ReadCleanReq accesses 1050system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadSharedReq accesses 1051system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.764706 # mshr miss rate for ReadSharedReq accesses 1052system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses 1053system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses 1054system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses 1055system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses 1056system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses 1057system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 1058system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses |
| 1059system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average HardPFReq mshr miss latency 1060system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 35373.416667 # average HardPFReq mshr miss latency 1061system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69033.333333 # average ReadExReq mshr miss latency 1062system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69033.333333 # average ReadExReq mshr miss latency 1063system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61652.573529 # average ReadCleanReq mshr miss latency 1064system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61652.573529 # average ReadCleanReq mshr miss latency | 1059system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average HardPFReq mshr miss latency 1060system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 33873.458333 # average HardPFReq mshr miss latency 1061system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71333.333333 # average ReadExReq mshr miss latency 1062system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71333.333333 # average ReadExReq mshr miss latency 1063system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 61215.073529 # average ReadCleanReq mshr miss latency 1064system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 61215.073529 # average ReadCleanReq mshr miss latency |
| 1065system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency 1066system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency | 1065system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 61391.025641 # average ReadSharedReq mshr miss latency 1066system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 61391.025641 # average ReadSharedReq mshr miss latency |
| 1067system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency 1068system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency 1069system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62181.578947 # average overall mshr miss latency 1070system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61652.573529 # average overall mshr miss latency 1071system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63513.888889 # average overall mshr miss latency 1072system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 35373.416667 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59175.056075 # average overall mshr miss latency | 1067system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency 1068system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency 1069system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62050 # average overall mshr miss latency 1070system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61215.073529 # average overall mshr miss latency 1071system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64152.777778 # average overall mshr miss latency 1072system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 33873.458333 # average overall mshr miss latency 1073system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58890.014019 # average overall mshr miss latency |
| 1074system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution --- 35 unchanged lines hidden (view full) --- 1117system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1118system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1119system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram 1120system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1121system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1122system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1123system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1124system.membus.snoop_fanout::total 407 # Request fanout histogram | 1074system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 1075system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 1076system.cpu.toL2Bus.trans_dist::CleanEvict 32 # Transaction distribution 1077system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution 1078system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1079system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1080system.cpu.toL2Bus.trans_dist::ReadCleanReq 296 # Transaction distribution 1081system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution --- 35 unchanged lines hidden (view full) --- 1117system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1118system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1119system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram 1120system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1121system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1122system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1123system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1124system.membus.snoop_fanout::total 407 # Request fanout histogram |
| 1125system.membus.reqLayer0.occupancy 510442 # Layer occupancy (ticks) | 1125system.membus.reqLayer0.occupancy 514444 # Layer occupancy (ticks) |
| 1126system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) | 1126system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) |
| 1127system.membus.respLayer1.occupancy 2136258 # Layer occupancy (ticks) | 1127system.membus.respLayer1.occupancy 2136000 # Layer occupancy (ticks) |
| 1128system.membus.respLayer1.utilization 12.0 # Layer utilization (%) 1129 1130---------- End Simulation Statistics ---------- | 1128system.membus.respLayer1.utilization 12.0 # Layer utilization (%) 1129 1130---------- End Simulation Statistics ---------- |