| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 17911000 # Number of ticks simulated 5final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 61363 # Simulator instruction rate (inst/s) 8host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) --- 641 unchanged lines hidden (view full) --- 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 657system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 17911000 # Number of ticks simulated 5final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 61363 # Simulator instruction rate (inst/s) 8host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) --- 641 unchanged lines hidden (view full) --- 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5377 # Class of committed instruction 657system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached |
| 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 659system.cpu.rob.rob_reads 22696 # The number of ROB reads 660system.cpu.rob.rob_writes 16433 # The number of ROB writes 661system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling 663system.cpu.committedInsts 4591 # Number of Instructions Simulated 664system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 665system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads --- 454 unchanged lines hidden --- | 658system.cpu.rob.rob_reads 22696 # The number of ROB reads 659system.cpu.rob.rob_writes 16433 # The number of ROB writes 660system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 661system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling 662system.cpu.committedInsts 4591 # Number of Instructions Simulated 663system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated 664system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction 665system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads --- 454 unchanged lines hidden --- |