| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16487000 # Number of ticks simulated 5final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000018 # Number of seconds simulated 4sim_ticks 17911000 # Number of ticks simulated 5final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 33036 # Simulator instruction rate (inst/s) 8host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 118603969 # Simulator tick rate (ticks/s) 10host_mem_usage 248576 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host | 7host_inst_rate 61363 # Simulator instruction rate (inst/s) 8host_op_rate 71855 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 239307903 # Simulator tick rate (ticks/s) 10host_mem_usage 305224 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory | 16system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory |
| 17system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory | 17system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory |
| 19system.physmem.bytes_read::total 26048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory | 19system.physmem.bytes_read::total 25984 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17344 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17344 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 271 # Number of read requests responded to by this memory |
| 23system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory | 23system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory |
| 25system.physmem.num_reads::total 407 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 408 # Number of read requests accepted | 25system.physmem.num_reads::total 406 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 407 # Number of read requests accepted |
| 37system.physmem.writeReqs 0 # Number of write requests accepted | 37system.physmem.writeReqs 0 # Number of write requests accepted |
| 38system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue | 38system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue |
| 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 40system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM | 40system.physmem.bytesReadDRAM 26048 # Total number of bytes read from DRAM |
| 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 43system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side | 43system.physmem.bytesReadSys 26048 # Total read bytes from the system interface side |
| 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 88 # Per bank write bursts 49system.physmem.perBankRdBursts::1 45 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts | 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 48system.physmem.perBankRdBursts::0 88 # Per bank write bursts 49system.physmem.perBankRdBursts::1 45 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts |
| 51system.physmem.perBankRdBursts::3 45 # Per bank write bursts | 51system.physmem.perBankRdBursts::3 44 # Per bank write bursts |
| 52system.physmem.perBankRdBursts::4 18 # Per bank write bursts 53system.physmem.perBankRdBursts::5 32 # Per bank write bursts 54system.physmem.perBankRdBursts::6 37 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 7 # Per bank write bursts 58system.physmem.perBankRdBursts::10 26 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts --- 14 unchanged lines hidden (view full) --- 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 52system.physmem.perBankRdBursts::4 18 # Per bank write bursts 53system.physmem.perBankRdBursts::5 32 # Per bank write bursts 54system.physmem.perBankRdBursts::6 37 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 7 # Per bank write bursts 58system.physmem.perBankRdBursts::10 26 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts --- 14 unchanged lines hidden (view full) --- 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 82system.physmem.totGap 16473500 # Total gap between requests | 82system.physmem.totGap 17897500 # Total gap between requests |
| 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) | 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 89system.physmem.readPktSize::6 408 # Read request sizes (log2) | 89system.physmem.readPktSize::6 407 # Read request sizes (log2) |
| 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) | 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 97system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see | 99system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see |
| 100system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see | 100system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 3 # What read queue length does an incoming req see |
| 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 73 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see --- 73 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 207system.physmem.totQLat 3192729 # Total ticks spent queuing 208system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst | 193system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation 207system.physmem.totQLat 3190492 # Total ticks spent queuing 208system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst |
| 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s | 212system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s |
| 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s | 215system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s |
| 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 218system.physmem.busUtil 12.37 # Data bus utilization in percentage 219system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads | 218system.physmem.busUtil 11.36 # Data bus utilization in percentage 219system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads |
| 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 221system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing |
| 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 342 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 223system.physmem.readRowHits 342 # Number of row buffer hits during reads 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 225system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads | 225system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads |
| 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.physmem.avgGap 40376.23 # Average gap between requests 228system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) | 227system.physmem.avgGap 43974.20 # Average gap between requests 228system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) |
| 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) | 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) |
| 236system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) 237system.physmem_0.averagePower 918.403600 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states | 236system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) 237system.physmem_0.averagePower 903.874941 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states |
| 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 241system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states | 241system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states |
| 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 243system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) | 243system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) |
| 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 248system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) 251system.physmem_1.averagePower 817.101847 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states | 248system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) 251system.physmem_1.averagePower 805.131217 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states |
| 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 255system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states | 255system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states |
| 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2361 # Number of BP lookups | 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2361 # Number of BP lookups |
| 258system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted | 258system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted |
| 259system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups | 259system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups |
| 261system.cpu.branchPred.BTBHits 473 # Number of BTB hits | 261system.cpu.branchPred.BTBHits 476 # Number of BTB hits |
| 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 263system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. | 263system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. 265system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. |
| 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls | 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst --- 102 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls |
| 384system.cpu.numCycles 32975 # number of cpu cycles simulated | 384system.cpu.numCycles 35823 # number of cpu cycles simulated |
| 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 387system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed | 387system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed |
| 389system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered | 389system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered |
| 390system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked | 390system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked |
| 392system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing | 392system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing |
| 393system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps 395system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched | 393system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps 395system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched |
| 397system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed | 397system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed |
| 398system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) | 398system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) |
| 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 402system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) | 402system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) |
| 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 409system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 5035 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst | 409system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 5024 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst |
| 425system.cpu.rename.RunCycles 4080 # Number of cycles rename is running | 425system.cpu.rename.RunCycles 4080 # Number of cycles rename is running |
| 426system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename 429system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full | 426system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename 429system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full |
| 430system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full | 430system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full |
| 431system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full 432system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full 433system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups | 431system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full 432system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full 433system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups 436system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups |
| 437system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 437system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 438system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 31 # count of serializing insts renamed | 438system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing 439system.cpu.rename.serializingInsts 30 # count of serializing insts renamed |
| 440system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed | 440system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed |
| 441system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. | 441system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. |
| 444system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 444system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 446system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) | 446system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) |
| 447system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ | 447system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ |
| 448system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued | 448system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued |
| 449system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued | 449system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued |
| 450system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph | 450system.cpu.iq.iqSquashedInstsExamined 2794 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph |
| 452system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed | 452system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| 453system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle | 453system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle |
| 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 457system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle |
| 462system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle | 462system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle |
| 469system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle |
| 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 471system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available | 471system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available |
| 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 505system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued | 505system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued |
| 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 538system.cpu.iq.FU_type_0::total 7157 # Type of FU issued 539system.cpu.iq.rate 0.217043 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses | 538system.cpu.iq.FU_type_0::total 7136 # Type of FU issued 539system.cpu.iq.rate 0.199202 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 11164 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses |
| 545system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads | 545system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads |
| 546system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes | 546system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes |
| 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 548system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses | 548system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses |
| 549system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses | 549system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses |
| 550system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores | 550system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores |
| 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 552system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed | 552system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed |
| 553system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 553system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 554system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 555system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed | 555system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed |
| 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 558system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked | 558system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked |
| 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 561system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ | 561system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ |
| 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 566system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions | 566system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions |
| 568system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall | 568system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall |
| 570system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall | 570system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall |
| 571system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations | 571system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations |
| 572system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly | 572system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly |
| 574system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute | 574system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute |
| 575system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute | 575system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute |
| 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 14 # number of nop insts executed | 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 14 # number of nop insts executed |
| 580system.cpu.iew.exec_refs 2417 # number of memory reference insts executed 581system.cpu.iew.exec_branches 1277 # Number of branches executed 582system.cpu.iew.exec_stores 1017 # Number of stores executed 583system.cpu.iew.exec_rate 0.205034 # Inst execution rate 584system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 6587 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 2990 # num instructions producing a value 587system.cpu.iew.wb_consumers 5391 # num instructions consuming a value | 580system.cpu.iew.exec_refs 2409 # number of memory reference insts executed 581system.cpu.iew.exec_branches 1271 # Number of branches executed 582system.cpu.iew.exec_stores 1015 # Number of stores executed 583system.cpu.iew.exec_rate 0.188036 # Inst execution rate 584system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 6566 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 2981 # num instructions producing a value 587system.cpu.iew.wb_consumers 5387 # num instructions consuming a value |
| 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 589system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back | 589system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back |
| 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 592system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit | 592system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit |
| 593system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards | 593system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards |
| 594system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle | 594system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle |
| 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 599system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle |
| 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 611system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle | 611system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle |
| 612system.cpu.commit.committedInsts 4591 # Number of instructions committed 613system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 1965 # Number of memory references committed 616system.cpu.commit.loads 1027 # Number of loads committed 617system.cpu.commit.membars 12 # Number of memory barriers committed 618system.cpu.commit.branches 1007 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5377 # Class of committed instruction | 612system.cpu.commit.committedInsts 4591 # Number of instructions committed 613system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 1965 # Number of memory references committed 616system.cpu.commit.loads 1027 # Number of loads committed 617system.cpu.commit.membars 12 # Number of memory barriers committed 618system.cpu.commit.branches 1007 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5377 # Class of committed instruction |
| 657system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached | 657system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached |
| 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 659system.cpu.rob.rob_reads 22003 # The number of ROB reads 660system.cpu.rob.rob_writes 16441 # The number of ROB writes 661system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling | 659system.cpu.rob.rob_reads 22696 # The number of ROB reads 660system.cpu.rob.rob_writes 16433 # The number of ROB writes 661system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 663system.cpu.committedInsts 4591 # Number of Instructions Simulated 664system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated | 663system.cpu.committedInsts 4591 # Number of Instructions Simulated 664system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated |
| 665system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads 667system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 6737 # number of integer regfile reads 670system.cpu.int_regfile_writes 3765 # number of integer regfile writes | 665system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads 667system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 6713 # number of integer regfile reads 670system.cpu.int_regfile_writes 3756 # number of integer regfile writes |
| 671system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 671system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 672system.cpu.cc_regfile_reads 24010 # number of cc regfile reads 673system.cpu.cc_regfile_writes 2910 # number of cc regfile writes 674system.cpu.misc_regfile_reads 2599 # number of misc regfile reads | 672system.cpu.cc_regfile_reads 23929 # number of cc regfile reads 673system.cpu.cc_regfile_writes 2892 # number of cc regfile writes 674system.cpu.misc_regfile_reads 2595 # number of misc regfile reads |
| 675system.cpu.misc_regfile_writes 24 # number of misc regfile writes 676system.cpu.dcache.tags.replacements 1 # number of replacements | 675system.cpu.misc_regfile_writes 24 # number of misc regfile writes 676system.cpu.dcache.tags.replacements 1 # number of replacements |
| 677system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. | 677system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. |
| 679system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. | 679system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. |
| 680system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. | 680system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. |
| 681system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 681system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 682system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy | 682system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy |
| 685system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id | 685system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id |
| 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id | 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id |
| 688system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id | 688system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id |
| 689system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses 690system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses 691system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits 692system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits | 689system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses 690system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses 691system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits 692system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits |
| 693system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 694system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 695system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 696system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 697system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 698system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 693system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 694system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 695system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 696system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 697system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 698system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 699system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits 700system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits 701system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits 702system.cpu.dcache.overall_hits::total 1876 # number of overall hits 703system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses 704system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses | 699system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits 700system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits 701system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits 702system.cpu.dcache.overall_hits::total 1882 # number of overall hits 703system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses 704system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses |
| 705system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 706system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 707system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 708system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 705system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 706system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 707system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 708system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 709system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses 710system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses 711system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses 712system.cpu.dcache.overall_misses::total 369 # number of overall misses 713system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles 714system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles 715system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles 716system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles 717system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles 718system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles 719system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles 720system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles 721system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles 722system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles 723system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) | 709system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses 710system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses 711system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses 712system.cpu.dcache.overall_misses::total 362 # number of overall misses 713system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles 714system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles 715system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles 716system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles 717system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles 718system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles 719system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles 720system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles 721system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles 722system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles 723system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) |
| 725system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 730system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 725system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 730system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 731system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses 732system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses 733system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses 734system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses 735system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses | 731system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses 732system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses 733system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses 734system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses 735system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses |
| 737system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 739system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 740system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses | 737system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 739system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 740system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses |
| 741system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses 742system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses 743system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses 744system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses 745system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency 746system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency 747system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency 748system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency 750system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency | 741system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses 742system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses 743system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses 744system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses 745system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency 746system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency 747system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency 748system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency 750system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency |
| 755system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 755system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 756system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked | 756system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked |
| 757system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 759system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 757system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 759system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 760system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked | 760system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked |
| 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed | 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 763system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits 764system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits | 763system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits 764system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits |
| 765system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 766system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 767system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 768system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 765system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 766system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 767system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 768system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 769system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits | 769system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits |
| 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses | 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses |
| 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses | 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses |
| 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses | 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses |
| 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency | 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency |
| 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.icache.tags.replacements 42 # number of replacements | 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.icache.tags.replacements 42 # number of replacements |
| 807system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use 808system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. 809system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. 810system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. | 807system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use 808system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. 809system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 810system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. |
| 811system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 811system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 812system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor 813system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy 814system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy 815system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 817system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 818system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id 819system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses 820system.cpu.icache.tags.data_accesses 7990 # Number of data accesses 821system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits 822system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits 823system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits 824system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits 825system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits 826system.cpu.icache.overall_hits::total 3485 # number of overall hits 827system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 828system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 829system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 830system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 831system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 832system.cpu.icache.overall_misses::total 362 # number of overall misses 833system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles 834system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles 835system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles 836system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles 837system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles 838system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles 839system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) 840system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) 841system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses 842system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses 843system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses 844system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses 845system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses 846system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses 847system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses 848system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses 849system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses 850system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses 851system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency 852system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency 853system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 854system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency 855system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 856system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency 857system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked 858system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked 859system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked | 812system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor 813system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy 814system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy 815system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id 817system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id 818system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id 819system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses 820system.cpu.icache.tags.data_accesses 7977 # Number of data accesses 821system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits 822system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits 823system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits 824system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits 825system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits 826system.cpu.icache.overall_hits::total 3477 # number of overall hits 827system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses 828system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses 829system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses 830system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses 831system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses 832system.cpu.icache.overall_misses::total 364 # number of overall misses 833system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles 834system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles 835system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles 836system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles 837system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles 838system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles 839system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) 840system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) 841system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses 842system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses 843system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses 844system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses 845system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses 846system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses 847system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses 848system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses 849system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses 850system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses 851system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency 852system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency 853system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency 854system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency 855system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency 856system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency 857system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked 858system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked 859system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked |
| 860system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked | 860system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked |
| 861system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked 862system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked | 861system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked 862system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked |
| 863system.cpu.icache.fast_writes 0 # number of fast writes performed 864system.cpu.icache.cache_copies 0 # number of cache copies performed | 863system.cpu.icache.fast_writes 0 # number of fast writes performed 864system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits 871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 872system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 873system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 874system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 875system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 876system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16894743 # number of ReadReq MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_miss_latency::total 16894743 # number of ReadReq MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16894743 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.demand_mshr_miss_latency::total 16894743 # number of demand (read+write) MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16894743 # number of overall MSHR miss cycles 882system.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles 883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses 885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses 886system.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency | 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits 871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses 872system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses 873system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses 874system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses 875system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses 876system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses 877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18519493 # number of ReadReq MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_miss_latency::total 18519493 # number of ReadReq MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18519493 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.demand_mshr_miss_latency::total 18519493 # number of demand (read+write) MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18519493 # number of overall MSHR miss cycles 882system.cpu.icache.overall_mshr_miss_latency::total 18519493 # number of overall MSHR miss cycles 883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077063 # mshr miss rate for ReadReq accesses 885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for demand accesses 886system.cpu.icache.demand_mshr_miss_rate::total 0.077063 # mshr miss rate for demand accesses 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.077063 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62565.854730 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62565.854730 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency |
| 895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 902system.cpu.l2cache.tags.replacements 0 # number of replacements | 895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing 902system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 903system.cpu.l2cache.tags.tagsinuse 195.136661 # Cycle average of tags in use | 903system.cpu.l2cache.tags.tagsinuse 192.519523 # Cycle average of tags in use |
| 904system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. | 904system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. |
| 905system.cpu.l2cache.tags.sampled_refs 365 # Sample count of references to valid blocks. 906system.cpu.l2cache.tags.avg_refs 0.115068 # Average number of references to valid blocks. | 905system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. 906system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. |
| 907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor 911system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy | 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor 911system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy |
| 915system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id | 915system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id |
| 916system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id | 916system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1022::1 8 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::1 166 # Occupied blocks per task id |
| 921system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id | 921system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id |
| 922system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id 923system.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses 924system.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses | 922system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021240 # Percentage of cache occupancy per task id 923system.cpu.l2cache.tags.tag_accesses 7429 # Number of tag accesses 924system.cpu.l2cache.tags.data_accesses 7429 # Number of data accesses |
| 925system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 926system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits 927system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits 928system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 929system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 930system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits 931system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits 933system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits 935system.cpu.l2cache.overall_hits::total 53 # number of overall hits | 925system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 926system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits 927system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits 928system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 929system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 930system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits 931system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits 933system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits 935system.cpu.l2cache.overall_hits::total 53 # number of overall hits |
| 936system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses | 936system.cpu.l2cache.ReadReq_misses::cpu.inst 273 # number of ReadReq misses |
| 937system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses | 937system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses |
| 938system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses | 938system.cpu.l2cache.ReadReq_misses::total 356 # number of ReadReq misses |
| 939system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 940system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses | 939system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 940system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses |
| 941system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses | 941system.cpu.l2cache.demand_misses::cpu.inst 273 # number of demand (read+write) misses |
| 942system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses | 942system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses |
| 943system.cpu.l2cache.demand_misses::total 387 # number of demand (read+write) misses 944system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses | 943system.cpu.l2cache.demand_misses::total 386 # number of demand (read+write) misses 944system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses |
| 945system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses | 945system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses |
| 946system.cpu.l2cache.overall_misses::total 387 # number of overall misses 947system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles 948system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles 949system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles 955system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles 956system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # number of overall miss cycles 957system.cpu.l2cache.overall_miss_latency::total 23756500 # number of overall miss cycles 958system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) | 946system.cpu.l2cache.overall_misses::total 386 # number of overall misses 947system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18219750 # number of ReadReq miss cycles 948system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5781750 # number of ReadReq miss cycles 949system.cpu.l2cache.ReadReq_miss_latency::total 24001500 # number of ReadReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.inst 18219750 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.data 8035500 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::total 26255250 # number of demand (read+write) miss cycles 955system.cpu.l2cache.overall_miss_latency::cpu.inst 18219750 # number of overall miss cycles 956system.cpu.l2cache.overall_miss_latency::cpu.data 8035500 # number of overall miss cycles 957system.cpu.l2cache.overall_miss_latency::total 26255250 # number of overall miss cycles 958system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) |
| 959system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) | 959system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) |
| 960system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) | 960system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) |
| 961system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) | 961system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) |
| 963system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses | 963system.cpu.l2cache.demand_accesses::cpu.inst 296 # number of demand (read+write) accesses |
| 964system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses | 964system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses |
| 965system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 966system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses | 965system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses 966system.cpu.l2cache.overall_accesses::cpu.inst 296 # number of overall (read+write) accesses |
| 967system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses | 967system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses |
| 968system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 969system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses | 968system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses 969system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922297 # miss rate for ReadReq accesses |
| 970system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses | 970system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses |
| 971system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses | 971system.cpu.l2cache.ReadReq_miss_rate::total 0.894472 # miss rate for ReadReq accesses |
| 972system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 973system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses | 972system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 973system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses |
| 974system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses | 974system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922297 # miss rate for demand accesses |
| 975system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses | 975system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses |
| 976system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses 977system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses | 976system.cpu.l2cache.demand_miss_rate::total 0.879271 # miss rate for demand accesses 977system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses |
| 978system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses | 978system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses |
| 979system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses 980system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency 981system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency 982system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency 983system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency 984system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency 985system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 986system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 987system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency 988system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 989system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 990system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency | 979system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses 980system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency 981system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency 982system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency 983system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency 984system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency 985system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency 986system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency 987system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency 988system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency 989system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency 990system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency |
| 991system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 992system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 993system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 994system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 995system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 996system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu.l2cache.fast_writes 0 # number of fast writes performed 998system.cpu.l2cache.cache_copies 0 # number of cache copies performed 999system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1000system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1001system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 1002system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1003system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1004system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1005system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1006system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1007system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits | 991system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 992system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 993system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 994system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 995system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 996system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu.l2cache.fast_writes 0 # number of fast writes performed 998system.cpu.l2cache.cache_copies 0 # number of cache copies performed 999system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1000system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1001system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 1002system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1003system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1004system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1005system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1006system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1007system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits |
| 1008system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses | 1008system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses |
| 1009system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses | 1009system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses |
| 1010system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses | 1010system.cpu.l2cache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses |
| 1011system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses 1012system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses 1013system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1014system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses | 1011system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses 1012system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses 1013system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1014system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses |
| 1015system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses | 1015system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses |
| 1016system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses | 1016system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses |
| 1017system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses 1018system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses | 1017system.cpu.l2cache.demand_mshr_misses::total 380 # number of demand (read+write) MSHR misses 1018system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses |
| 1019system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 1020system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses | 1019system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 1020system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses |
| 1021system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses 1022system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles 1023system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles 1026system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles 1027system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles 1028system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles 1029system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles 1030system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles 1031system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles 1032system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles 1033system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles 1034system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles 1035system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles 1036system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses | 1021system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses 1022system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles 1023system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles 1026system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles 1027system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles 1028system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles 1029system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles 1030system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles 1031system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles 1032system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles 1033system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles 1034system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles 1035system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles 1036system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses |
| 1037system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses | 1037system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses |
| 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses | 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses |
| 1039system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1040system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1041system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses | 1039system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1040system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 1041system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses |
| 1043system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses | 1043system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for demand accesses |
| 1044system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses | 1044system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses |
| 1045system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses 1046system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses | 1045system.cpu.l2cache.demand_mshr_miss_rate::total 0.865604 # mshr miss rate for demand accesses 1046system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for overall accesses |
| 1047system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses 1048system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1047system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses 1048system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 1049system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses 1050system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency 1051system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency 1052system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency 1053system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency 1054system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency 1055system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency 1056system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency 1057system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 1058system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 1059system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 1061system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 1062system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency 1063system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency | 1049system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses 1050system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency 1051system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency 1052system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency 1053system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency 1054system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency 1055system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency 1056system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency 1057system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency 1058system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency 1059system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency 1061system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency 1062system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency 1063system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency |
| 1064system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1064system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 1065system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 1066system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution 1067system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution | 1065system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution 1066system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution 1067system.cpu.toL2Bus.trans_dist::HardPFReq 64 # Transaction distribution |
| 1068system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1069system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution | 1068system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1069system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution |
| 1070system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) | 1070system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 591 # Packet count per connected master and slave (bytes) |
| 1071system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) | 1071system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) |
| 1072system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) 1073system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) | 1072system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) 1073system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) |
| 1074system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) | 1074system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) |
| 1075system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) 1076system.cpu.toL2Bus.snoops 67 # Total snoops (count) 1077system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram 1078system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram | 1075system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) 1076system.cpu.toL2Bus.snoops 64 # Total snoops (count) 1077system.cpu.toL2Bus.snoop_fanout::samples 503 # Request fanout histogram 1078system.cpu.toL2Bus.snoop_fanout::mean 3.127237 # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::stdev 0.333570 # Request fanout histogram |
| 1080system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1081system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1082system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1083system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram | 1080system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1081system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1082system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1083system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram |
| 1084system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1085system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1086system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram 1087system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram | 1084system.cpu.toL2Bus.snoop_fanout::3 439 87.28% 87.28% # Request fanout histogram 1085system.cpu.toL2Bus.snoop_fanout::4 64 12.72% 100.00% # Request fanout histogram |
| 1088system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 1086system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 1089system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1090system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1091system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram 1092system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 1093system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1094system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) 1095system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 1096system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) 1097system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1098system.membus.trans_dist::ReadReq 378 # Transaction distribution 1099system.membus.trans_dist::ReadResp 376 # Transaction distribution | 1087system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram 1088system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram 1089system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram 1090system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) 1091system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 1092system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) 1093system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) 1094system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) 1095system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) 1096system.membus.trans_dist::ReadReq 377 # Transaction distribution 1097system.membus.trans_dist::ReadResp 375 # Transaction distribution |
| 1100system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1101system.membus.trans_dist::ReadExResp 30 # Transaction distribution | 1098system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1099system.membus.trans_dist::ReadExResp 30 # Transaction distribution |
| 1102system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) 1103system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) 1104system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) 1105system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) | 1100system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 812 # Packet count per connected master and slave (bytes) 1101system.membus.pkt_count::total 812 # Packet count per connected master and slave (bytes) 1102system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25920 # Cumulative packet size per connected master and slave (bytes) 1103system.membus.pkt_size::total 25920 # Cumulative packet size per connected master and slave (bytes) |
| 1106system.membus.snoops 0 # Total snoops (count) | 1104system.membus.snoops 0 # Total snoops (count) |
| 1107system.membus.snoop_fanout::samples 408 # Request fanout histogram | 1105system.membus.snoop_fanout::samples 407 # Request fanout histogram |
| 1108system.membus.snoop_fanout::mean 0 # Request fanout histogram 1109system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1110system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 1106system.membus.snoop_fanout::mean 0 # Request fanout histogram 1107system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1108system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 1111system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram | 1109system.membus.snoop_fanout::0 407 100.00% 100.00% # Request fanout histogram |
| 1112system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1113system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1114system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1115system.membus.snoop_fanout::max_value 0 # Request fanout histogram | 1110system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1111system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1112system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1113system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| 1116system.membus.snoop_fanout::total 408 # Request fanout histogram 1117system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) 1118system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) 1119system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) 1120system.membus.respLayer1.utilization 23.0 # Layer utilization (%) | 1114system.membus.snoop_fanout::total 407 # Request fanout histogram 1115system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) 1116system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 1117system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) 1118system.membus.respLayer1.utilization 11.9 # Layer utilization (%) |
| 1121 1122---------- End Simulation Statistics ---------- | 1119 1120---------- End Simulation Statistics ---------- |