| stats.txt (10488:7c27480a5031) | stats.txt (10628:c9b7e0c69f88) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 11859500 # Number of ticks simulated 5final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16487000 # Number of ticks simulated 5final_tick 16487000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 34923 # Simulator instruction rate (inst/s) 8host_op_rate 40896 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 90188816 # Simulator tick rate (ticks/s) 10host_mem_usage 248256 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 33036 # Simulator instruction rate (inst/s) 8host_op_rate 38686 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 118603969 # Simulator tick rate (ticks/s) 10host_mem_usage 248576 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 46848 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 732 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 733 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6912 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 # Number of bytes read from this memory 19system.physmem.bytes_read::total 26048 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 17408 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 17408 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 407 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 1055862194 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 419239401 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 104809850 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 1579911445 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 1055862194 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 1055862194 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 1055862194 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 419239401 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 104809850 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 1579911445 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 408 # Number of read requests accepted |
| 37system.physmem.writeReqs 0 # Number of write requests accepted | 37system.physmem.writeReqs 0 # Number of write requests accepted |
| 38system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue | 38system.physmem.readBursts 408 # Number of DRAM read bursts, including those serviced by the write queue |
| 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 40system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM | 40system.physmem.bytesReadDRAM 26112 # Total number of bytes read from DRAM |
| 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 43system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side | 43system.physmem.bytesReadSys 26112 # Total read bytes from the system interface side |
| 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 48system.physmem.perBankRdBursts::0 143 # Per bank write bursts 49system.physmem.perBankRdBursts::1 90 # Per bank write bursts 50system.physmem.perBankRdBursts::2 40 # Per bank write bursts 51system.physmem.perBankRdBursts::3 73 # Per bank write bursts 52system.physmem.perBankRdBursts::4 58 # Per bank write bursts 53system.physmem.perBankRdBursts::5 88 # Per bank write bursts 54system.physmem.perBankRdBursts::6 52 # Per bank write bursts 55system.physmem.perBankRdBursts::7 18 # Per bank write bursts 56system.physmem.perBankRdBursts::8 12 # Per bank write bursts 57system.physmem.perBankRdBursts::9 28 # Per bank write bursts 58system.physmem.perBankRdBursts::10 34 # Per bank write bursts | 48system.physmem.perBankRdBursts::0 88 # Per bank write bursts 49system.physmem.perBankRdBursts::1 45 # Per bank write bursts 50system.physmem.perBankRdBursts::2 19 # Per bank write bursts 51system.physmem.perBankRdBursts::3 45 # Per bank write bursts 52system.physmem.perBankRdBursts::4 18 # Per bank write bursts 53system.physmem.perBankRdBursts::5 32 # Per bank write bursts 54system.physmem.perBankRdBursts::6 37 # Per bank write bursts 55system.physmem.perBankRdBursts::7 10 # Per bank write bursts 56system.physmem.perBankRdBursts::8 4 # Per bank write bursts 57system.physmem.perBankRdBursts::9 7 # Per bank write bursts 58system.physmem.perBankRdBursts::10 26 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts | 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts |
| 61system.physmem.perBankRdBursts::13 19 # Per bank write bursts | 61system.physmem.perBankRdBursts::13 7 # Per bank write bursts |
| 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts | 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts |
| 63system.physmem.perBankRdBursts::15 14 # Per bank write bursts | 63system.physmem.perBankRdBursts::15 6 # Per bank write bursts |
| 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 82system.physmem.totGap 11846500 # Total gap between requests | 82system.physmem.totGap 16473500 # Total gap between requests |
| 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) | 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 89system.physmem.readPktSize::6 733 # Read request sizes (log2) | 89system.physmem.readPktSize::6 408 # Read request sizes (log2) |
| 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) | 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 97system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 123 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 3 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 2 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 2 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 2 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 1 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 193system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 207system.physmem.totQLat 17284989 # Total ticks spent queuing 208system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst | 193system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 406.349206 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 267.472109 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 352.639181 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 10 15.87% 15.87% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 20 31.75% 47.62% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 9 14.29% 61.90% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 4 6.35% 68.25% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 2 3.17% 71.43% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 3 4.76% 76.19% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 3 4.76% 80.95% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 2 3.17% 84.13% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 207system.physmem.totQLat 3192729 # Total ticks spent queuing 208system.physmem.totMemAccLat 10842729 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 2040000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 7825.32 # Average queueing delay per DRAM burst |
| 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 212system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s | 212system.physmem.avgMemAccLat 26575.32 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 1583.79 # Average DRAM read bandwidth in MiByte/s |
| 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 215system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s | 215system.physmem.avgRdBWSys 1583.79 # Average system read bandwidth in MiByte/s |
| 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 218system.physmem.busUtil 30.90 # Data bus utilization in percentage 219system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads | 218system.physmem.busUtil 12.37 # Data bus utilization in percentage 219system.physmem.busUtilRead 12.37 # Data bus utilization in percentage for reads |
| 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 221system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing |
| 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 223system.physmem.readRowHits 662 # Number of row buffer hits during reads | 223system.physmem.readRowHits 342 # Number of row buffer hits during reads |
| 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 225system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads | 225system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads |
| 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 227system.physmem.avgGap 16161.66 # Average gap between requests 228system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined 229system.physmem.memoryStateTime::IDLE 6500 # Time in different power states 230system.physmem.memoryStateTime::REF 260000 # Time in different power states 231system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 232system.physmem.memoryStateTime::ACT 7800750 # Time in different power states 233system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 234system.physmem.actEnergy::0 249480 # Energy for activate commands per rank (pJ) 235system.physmem.actEnergy::1 90720 # Energy for activate commands per rank (pJ) 236system.physmem.preEnergy::0 136125 # Energy for precharge commands per rank (pJ) 237system.physmem.preEnergy::1 49500 # Energy for precharge commands per rank (pJ) 238system.physmem.readEnergy::0 3088800 # Energy for read commands per rank (pJ) 239system.physmem.readEnergy::1 1037400 # Energy for read commands per rank (pJ) 240system.physmem.writeEnergy::0 0 # Energy for write commands per rank (pJ) 241system.physmem.writeEnergy::1 0 # Energy for write commands per rank (pJ) 242system.physmem.refreshEnergy::0 508560 # Energy for refresh commands per rank (pJ) 243system.physmem.refreshEnergy::1 508560 # Energy for refresh commands per rank (pJ) 244system.physmem.actBackEnergy::0 5483970 # Energy for active background per rank (pJ) 245system.physmem.actBackEnergy::1 5436945 # Energy for active background per rank (pJ) 246system.physmem.preBackEnergy::0 21750 # Energy for precharge background per rank (pJ) 247system.physmem.preBackEnergy::1 63000 # Energy for precharge background per rank (pJ) 248system.physmem.totalEnergy::0 9488685 # Total energy per rank (pJ) 249system.physmem.totalEnergy::1 7186125 # Total energy per rank (pJ) 250system.physmem.averagePower::0 1178.169797 # Core power per rank (mW) 251system.physmem.averagePower::1 892.270681 # Core power per rank (mW) 252system.membus.trans_dist::ReadReq 704 # Transaction distribution 253system.membus.trans_dist::ReadResp 702 # Transaction distribution 254system.membus.trans_dist::ReadExReq 29 # Transaction distribution 255system.membus.trans_dist::ReadExResp 29 # Transaction distribution 256system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) 257system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) 258system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) 259system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) 260system.membus.snoops 0 # Total snoops (count) 261system.membus.snoop_fanout::samples 733 # Request fanout histogram 262system.membus.snoop_fanout::mean 0 # Request fanout histogram 263system.membus.snoop_fanout::stdev 0 # Request fanout histogram 264system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 265system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram 266system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 267system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 268system.membus.snoop_fanout::min_value 0 # Request fanout histogram 269system.membus.snoop_fanout::max_value 0 # Request fanout histogram 270system.membus.snoop_fanout::total 733 # Request fanout histogram 271system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) 272system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) 273system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) 274system.membus.respLayer1.utilization 55.9 # Layer utilization (%) 275system.cpu_clk_domain.clock 500 # Clock period in ticks 276system.cpu.branchPred.lookups 2560 # Number of BP lookups 277system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted 278system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect 279system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups 280system.cpu.branchPred.BTBHits 497 # Number of BTB hits | 227system.physmem.avgGap 40376.23 # Average gap between requests 228system.physmem.pageHitRate 83.82 # Row buffer hit rate, read and write combined 229system.physmem_0.actEnergy 317520 # Energy for activate commands per rank (pJ) 230system.physmem_0.preEnergy 173250 # Energy for precharge commands per rank (pJ) 231system.physmem_0.readEnergy 2207400 # Energy for read commands per rank (pJ) 232system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 233system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 234system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) 235system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) 236system.physmem_0.totalEnergy 14540625 # Total energy per rank (pJ) 237system.physmem_0.averagePower 918.403600 # Core power per rank (mW) 238system.physmem_0.memoryStateTime::IDLE 6500 # Time in different power states 239system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 240system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 241system.physmem_0.memoryStateTime::ACT 15319750 # Time in different power states 242system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 243system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) 244system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) 245system.physmem_1.readEnergy 881400 # Energy for read commands per rank (pJ) 246system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 247system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 248system.physmem_1.actBackEnergy 10626795 # Energy for active background per rank (pJ) 249system.physmem_1.preBackEnergy 177750 # Energy for precharge background per rank (pJ) 250system.physmem_1.totalEnergy 12936765 # Total energy per rank (pJ) 251system.physmem_1.averagePower 817.101847 # Core power per rank (mW) 252system.physmem_1.memoryStateTime::IDLE 860250 # Time in different power states 253system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 254system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.physmem_1.memoryStateTime::ACT 15071750 # Time in different power states 256system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.cpu.branchPred.lookups 2361 # Number of BP lookups 258system.cpu.branchPred.condPredicted 1411 # Number of conditional branches predicted 259system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect 260system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups 261system.cpu.branchPred.BTBHits 473 # Number of BTB hits |
| 281system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 262system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 282system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage 283system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. | 263system.cpu.branchPred.BTBHitPct 54.305396 # BTB Hit Percentage 264system.cpu.branchPred.usedRAS 287 # Number of times the RAS was used to get a target. |
| 284system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. | 265system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. |
| 266system.cpu_clk_domain.clock 500 # Clock period in ticks 267system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 268system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 269system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 270system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 271system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 272system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 273system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 274system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 285system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 286system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 287system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 288system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 289system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 290system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 291system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 292system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 298system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 299system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 300system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 301system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 302system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 303system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 304system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 305system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 275system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 276system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 277system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 278system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 279system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 280system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 281system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 282system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 288system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 289system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 290system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 291system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 292system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 293system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 294system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 295system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 296system.cpu.dtb.walker.walks 0 # Table walker walks requested 297system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 298system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 299system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 300system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 301system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 302system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 303system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 306system.cpu.dtb.inst_hits 0 # ITB inst hits 307system.cpu.dtb.inst_misses 0 # ITB inst misses 308system.cpu.dtb.read_hits 0 # DTB read hits 309system.cpu.dtb.read_misses 0 # DTB read misses 310system.cpu.dtb.write_hits 0 # DTB write hits 311system.cpu.dtb.write_misses 0 # DTB write misses 312system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 313system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 319system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 320system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 321system.cpu.dtb.read_accesses 0 # DTB read accesses 322system.cpu.dtb.write_accesses 0 # DTB write accesses 323system.cpu.dtb.inst_accesses 0 # ITB inst accesses 324system.cpu.dtb.hits 0 # DTB hits 325system.cpu.dtb.misses 0 # DTB misses 326system.cpu.dtb.accesses 0 # DTB accesses | 304system.cpu.dtb.inst_hits 0 # ITB inst hits 305system.cpu.dtb.inst_misses 0 # ITB inst misses 306system.cpu.dtb.read_hits 0 # DTB read hits 307system.cpu.dtb.read_misses 0 # DTB read misses 308system.cpu.dtb.write_hits 0 # DTB write hits 309system.cpu.dtb.write_misses 0 # DTB write misses 310system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 311system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 317system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 318system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 319system.cpu.dtb.read_accesses 0 # DTB read accesses 320system.cpu.dtb.write_accesses 0 # DTB write accesses 321system.cpu.dtb.inst_accesses 0 # ITB inst accesses 322system.cpu.dtb.hits 0 # DTB hits 323system.cpu.dtb.misses 0 # DTB misses 324system.cpu.dtb.accesses 0 # DTB accesses |
| 325system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested 326system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 327system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 328system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 329system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 330system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 331system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 332system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 327system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 328system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 329system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 330system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 331system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 332system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 333system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 334system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 340system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 341system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 342system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 343system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 344system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 345system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 346system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 347system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses | 333system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 334system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 335system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 336system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 337system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 338system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 339system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 340system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 346system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 347system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 348system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 349system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 350system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 351system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 352system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 353system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| 354system.cpu.itb.walker.walks 0 # Table walker walks requested 355system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst 356system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst 357system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst 358system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst 359system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst 360system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst 361system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
|
| 348system.cpu.itb.inst_hits 0 # ITB inst hits 349system.cpu.itb.inst_misses 0 # ITB inst misses 350system.cpu.itb.read_hits 0 # DTB read hits 351system.cpu.itb.read_misses 0 # DTB read misses 352system.cpu.itb.write_hits 0 # DTB write hits 353system.cpu.itb.write_misses 0 # DTB write misses 354system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 355system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 362system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 363system.cpu.itb.read_accesses 0 # DTB read accesses 364system.cpu.itb.write_accesses 0 # DTB write accesses 365system.cpu.itb.inst_accesses 0 # ITB inst accesses 366system.cpu.itb.hits 0 # DTB hits 367system.cpu.itb.misses 0 # DTB misses 368system.cpu.itb.accesses 0 # DTB accesses 369system.cpu.workload.num_syscalls 13 # Number of system calls | 362system.cpu.itb.inst_hits 0 # ITB inst hits 363system.cpu.itb.inst_misses 0 # ITB inst misses 364system.cpu.itb.read_hits 0 # DTB read hits 365system.cpu.itb.read_misses 0 # DTB read misses 366system.cpu.itb.write_hits 0 # DTB write hits 367system.cpu.itb.write_misses 0 # DTB write misses 368system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 369system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 6 unchanged lines hidden (view full) --- 376system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 377system.cpu.itb.read_accesses 0 # DTB read accesses 378system.cpu.itb.write_accesses 0 # DTB write accesses 379system.cpu.itb.inst_accesses 0 # ITB inst accesses 380system.cpu.itb.hits 0 # DTB hits 381system.cpu.itb.misses 0 # DTB misses 382system.cpu.itb.accesses 0 # DTB accesses 383system.cpu.workload.num_syscalls 13 # Number of system calls |
| 370system.cpu.numCycles 23720 # number of cpu cycles simulated | 384system.cpu.numCycles 32975 # number of cpu cycles simulated |
| 371system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 372system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 385system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 386system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 373system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss 374system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed 375system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered 376system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken 377system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked 378system.cpu.fetch.SquashCycles 1063 # Number of cycles fetch has spent squashing 379system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 380system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps 381system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR 382system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched 383system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed 384system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) 385system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) 386system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) | 387system.cpu.fetch.icacheStallCycles 6157 # Number of cycles fetch is stalled on an Icache miss 388system.cpu.fetch.Insts 11322 # Number of instructions fetch has processed 389system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered 390system.cpu.fetch.predictedBranches 760 # Number of branches that fetch has predicted taken 391system.cpu.fetch.Cycles 7387 # Number of cycles fetch has run and was not squashing or blocked 392system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing 393system.cpu.fetch.MiscStallCycles 111 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 394system.cpu.fetch.PendingTrapStallCycles 277 # Number of stall cycles due to pending traps 395system.cpu.fetch.IcacheWaitRetryStallCycles 339 # Number of stall cycles due to full MSHR 396system.cpu.fetch.CacheLines 3848 # Number of cache lines fetched 397system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed 398system.cpu.fetch.rateDist::samples 14798 # Number of instructions fetched each cycle (Total) 399system.cpu.fetch.rateDist::mean 0.892688 # Number of instructions fetched each cycle (Total) 400system.cpu.fetch.rateDist::stdev 1.216053 # Number of instructions fetched each cycle (Total) |
| 387system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 401system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 388system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) 389system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) 390system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) 391system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) | 402system.cpu.fetch.rateDist::0 8580 57.98% 57.98% # Number of instructions fetched each cycle (Total) 403system.cpu.fetch.rateDist::1 2466 16.66% 74.65% # Number of instructions fetched each cycle (Total) 404system.cpu.fetch.rateDist::2 512 3.46% 78.11% # Number of instructions fetched each cycle (Total) 405system.cpu.fetch.rateDist::3 3240 21.89% 100.00% # Number of instructions fetched each cycle (Total) |
| 392system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 393system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 394system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) | 406system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 407system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 408system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) |
| 395system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) 396system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle 397system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle 398system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle 399system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked 400system.cpu.decode.RunCycles 5106 # Number of cycles decode is running 401system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking 402system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing 403system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch 404system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction 405system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode 406system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode 407system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing 408system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle 409system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking 410system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst 411system.cpu.rename.RunCycles 4105 # Number of cycles rename is running 412system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking 413system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename 414system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename 415system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full 416system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 417system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full 418system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full 419system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed 420system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made 421system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups | 409system.cpu.fetch.rateDist::total 14798 # Number of instructions fetched each cycle (Total) 410system.cpu.fetch.branchRate 0.071600 # Number of branch fetches per cycle 411system.cpu.fetch.rate 0.343351 # Number of inst fetches per cycle 412system.cpu.decode.IdleCycles 5946 # Number of cycles decode is idle 413system.cpu.decode.BlockedCycles 3315 # Number of cycles decode is blocked 414system.cpu.decode.RunCycles 5035 # Number of cycles decode is running 415system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking 416system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing 417system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch 418system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 419system.cpu.decode.DecodedInsts 9887 # Number of instructions handled by decode 420system.cpu.decode.SquashedInsts 1624 # Number of squashed instructions handled by decode 421system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing 422system.cpu.rename.IdleCycles 7027 # Number of cycles rename is idle 423system.cpu.rename.BlockCycles 950 # Number of cycles rename is blocking 424system.cpu.rename.serializeStallCycles 1833 # count of cycles rename stalled for serializing inst 425system.cpu.rename.RunCycles 4080 # Number of cycles rename is running 426system.cpu.rename.UnblockCycles 541 # Number of cycles rename is unblocking 427system.cpu.rename.RenamedInsts 8892 # Number of instructions processed by rename 428system.cpu.rename.SquashedInsts 410 # Number of squashed instructions processed by rename 429system.cpu.rename.ROBFullEvents 16 # Number of times rename has blocked due to ROB full 430system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full 431system.cpu.rename.LQFullEvents 16 # Number of times rename has blocked due to LQ full 432system.cpu.rename.SQFullEvents 453 # Number of times rename has blocked due to SQ full 433system.cpu.rename.RenamedOperands 9276 # Number of destination operands rename has renamed 434system.cpu.rename.RenameLookups 40303 # Number of register rename lookups that rename has made 435system.cpu.rename.int_rename_lookups 9770 # Number of integer rename lookups |
| 422system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups 423system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 436system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups 437system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 424system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing | 438system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing |
| 425system.cpu.rename.serializingInsts 31 # count of serializing insts renamed | 439system.cpu.rename.serializingInsts 31 # count of serializing insts renamed |
| 426system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed 427system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer 428system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. 429system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. | 440system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed 441system.cpu.rename.skidInsts 320 # count of insts added to the skid buffer 442system.cpu.memDep0.insertedLoads 1789 # Number of loads inserted to the mem dependence unit. 443system.cpu.memDep0.insertedStores 1266 # Number of stores inserted to the mem dependence unit. |
| 430system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 431system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. | 444system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 445system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. |
| 432system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) 433system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ 434system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued 435system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued 436system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling 437system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph 438system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 439system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle 440system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle 441system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle | 446system.cpu.iq.iqInstsAdded 8351 # Number of instructions added to the IQ (excludes non-spec) 447system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ 448system.cpu.iq.iqInstsIssued 7157 # Number of instructions issued 449system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued 450system.cpu.iq.iqSquashedInstsExamined 2800 # Number of squashed instructions iterated over during squash; mainly for profiling 451system.cpu.iq.iqSquashedOperandsExamined 7772 # Number of squashed operands that are examined and possibly removed from graph 452system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 453system.cpu.iq.issued_per_cycle::samples 14798 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::mean 0.483646 # Number of insts issued each cycle 455system.cpu.iq.issued_per_cycle::stdev 0.864768 # Number of insts issued each cycle |
| 442system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 456system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 443system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle 444system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle 445system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle 446system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle 447system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle | 457system.cpu.iq.issued_per_cycle::0 10589 71.56% 71.56% # Number of insts issued each cycle 458system.cpu.iq.issued_per_cycle::1 1954 13.20% 84.76% # Number of insts issued each cycle 459system.cpu.iq.issued_per_cycle::2 1606 10.85% 95.61% # Number of insts issued each cycle 460system.cpu.iq.issued_per_cycle::3 605 4.09% 99.70% # Number of insts issued each cycle 461system.cpu.iq.issued_per_cycle::4 44 0.30% 100.00% # Number of insts issued each cycle |
| 448system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 449system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 450system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 451system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 452system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 453system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 454system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle | 462system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 463system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 464system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 465system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle 466system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 467system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 468system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle |
| 455system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle | 469system.cpu.iq.issued_per_cycle::total 14798 # Number of insts issued each cycle |
| 456system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 470system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 457system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available 458system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available 459system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available 460system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available 461system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available 462system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available 463system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available 464system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available 465system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available 468system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available 469system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available 470system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available 471system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available 472system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available 473system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available 474system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available 475system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available 476system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available 477system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available 478system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available 479system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 486system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available 487system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available | 471system.cpu.iq.fu_full::IntAlu 414 28.91% 28.91% # attempts to use FU when none available 472system.cpu.iq.fu_full::IntMult 0 0.00% 28.91% # attempts to use FU when none available 473system.cpu.iq.fu_full::IntDiv 0 0.00% 28.91% # attempts to use FU when none available 474system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.91% # attempts to use FU when none available 475system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.91% # attempts to use FU when none available 476system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.91% # attempts to use FU when none available 477system.cpu.iq.fu_full::FloatMult 0 0.00% 28.91% # attempts to use FU when none available 478system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.91% # attempts to use FU when none available 479system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 480system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.91% # attempts to use FU when none available 481system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.91% # attempts to use FU when none available 482system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.91% # attempts to use FU when none available 483system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.91% # attempts to use FU when none available 484system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.91% # attempts to use FU when none available 485system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.91% # attempts to use FU when none available 486system.cpu.iq.fu_full::SimdMult 0 0.00% 28.91% # attempts to use FU when none available 487system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.91% # attempts to use FU when none available 488system.cpu.iq.fu_full::SimdShift 0 0.00% 28.91% # attempts to use FU when none available 489system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.91% # attempts to use FU when none available 490system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.91% # attempts to use FU when none available 491system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.91% # attempts to use FU when none available 492system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.91% # attempts to use FU when none available 493system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.91% # attempts to use FU when none available 494system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.91% # attempts to use FU when none available 495system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.91% # attempts to use FU when none available 496system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.91% # attempts to use FU when none available 497system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.91% # attempts to use FU when none available 498system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.91% # attempts to use FU when none available 499system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.91% # attempts to use FU when none available 500system.cpu.iq.fu_full::MemRead 469 32.75% 61.66% # attempts to use FU when none available 501system.cpu.iq.fu_full::MemWrite 549 38.34% 100.00% # attempts to use FU when none available |
| 488system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 489system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 490system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 502system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 503system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 504system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 491system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued 492system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued 493system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued 494system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued 495system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued 496system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued 497system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued 498system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued 499system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued 502system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued 503system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued 504system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued 505system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued 506system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued 507system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued 508system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued 509system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued 510system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued 511system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued 512system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued 513system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued 520system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued 521system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued | 505system.cpu.iq.FU_type_0::IntAlu 4493 62.78% 62.78% # Type of FU issued 506system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued 507system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued 508system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued 509system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued 510system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued 511system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued 512system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued 513system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued 514system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued 515system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued 516system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued 517system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued 518system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued 519system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued 520system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued 521system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued 522system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued 523system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued 524system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued 525system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued 526system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued 527system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued 528system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued 529system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued 530system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued 531system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued 532system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued 533system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued 534system.cpu.iq.FU_type_0::MemRead 1580 22.08% 84.97% # Type of FU issued 535system.cpu.iq.FU_type_0::MemWrite 1076 15.03% 100.00% # Type of FU issued |
| 522system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 523system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 536system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 537system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 524system.cpu.iq.FU_type_0::total 7242 # Type of FU issued 525system.cpu.iq.rate 0.305312 # Inst issue rate 526system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested 527system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) 528system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads 529system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes 530system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses 531system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads | 538system.cpu.iq.FU_type_0::total 7157 # Type of FU issued 539system.cpu.iq.rate 0.217043 # Inst issue rate 540system.cpu.iq.fu_busy_cnt 1432 # FU busy when requested 541system.cpu.iq.fu_busy_rate 0.200084 # FU busy rate (busy events/executed inst) 542system.cpu.iq.int_inst_queue_reads 30686 # Number of integer instruction queue reads 543system.cpu.iq.int_inst_queue_writes 11179 # Number of integer instruction queue writes 544system.cpu.iq.int_inst_queue_wakeup_accesses 6571 # Number of integer instruction queue wakeup accesses 545system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads |
| 532system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes 533system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses | 546system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes 547system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses |
| 534system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses 535system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses 536system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores | 548system.cpu.iq.int_alu_accesses 8561 # Number of integer alu accesses 549system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses 550system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores |
| 537system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 551system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 538system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed 539system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed | 552system.cpu.iew.lsq.thread0.squashedLoads 762 # Number of loads squashed 553system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| 540system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations | 554system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations |
| 541system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed | 555system.cpu.iew.lsq.thread0.squashedStores 328 # Number of stores squashed |
| 542system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 543system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 556system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 557system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 544system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 545system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked | 558system.cpu.iew.lsq.thread0.rescheduledLoads 6 # Number of loads that were rescheduled 559system.cpu.iew.lsq.thread0.cacheBlocked 21 # Number of times an access to memory failed due to the cache being blocked |
| 546system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 560system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 547system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing 548system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking 549system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking 550system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ | 561system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing 562system.cpu.iew.iewBlockCycles 446 # Number of cycles IEW is blocking 563system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking 564system.cpu.iew.iewDispatchedInsts 8404 # Number of instructions dispatched to IQ |
| 551system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch | 565system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch |
| 552system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions 553system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions 554system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 555system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 556system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall | 566system.cpu.iew.iewDispLoadInsts 1789 # Number of dispatched load instructions 567system.cpu.iew.iewDispStoreInsts 1266 # Number of dispatched store instructions 568system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 569system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall 570system.cpu.iew.iewLSQFullEvents 19 # Number of times the LSQ has become full, causing a stall |
| 557system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations | 571system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations |
| 558system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 559system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 560system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute 561system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions 562system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed 563system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute | 572system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 573system.cpu.iew.predictedNotTakenIncorrect 290 # Number of branches that were predicted not taken incorrectly 574system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute 575system.cpu.iew.iewExecutedInsts 6761 # Number of executed instructions 576system.cpu.iew.iewExecLoadInsts 1400 # Number of load instructions executed 577system.cpu.iew.iewExecSquashedInsts 396 # Number of squashed instructions skipped in execute |
| 564system.cpu.iew.exec_swp 0 # number of swp insts executed 565system.cpu.iew.exec_nop 14 # number of nop insts executed | 578system.cpu.iew.exec_swp 0 # number of swp insts executed 579system.cpu.iew.exec_nop 14 # number of nop insts executed |
| 566system.cpu.iew.exec_refs 2449 # number of memory reference insts executed 567system.cpu.iew.exec_branches 1283 # Number of branches executed 568system.cpu.iew.exec_stores 1021 # Number of stores executed 569system.cpu.iew.exec_rate 0.287858 # Inst execution rate 570system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit 571system.cpu.iew.wb_count 6654 # cumulative count of insts written-back 572system.cpu.iew.wb_producers 3045 # num instructions producing a value 573system.cpu.iew.wb_consumers 5519 # num instructions consuming a value | 580system.cpu.iew.exec_refs 2417 # number of memory reference insts executed 581system.cpu.iew.exec_branches 1277 # Number of branches executed 582system.cpu.iew.exec_stores 1017 # Number of stores executed 583system.cpu.iew.exec_rate 0.205034 # Inst execution rate 584system.cpu.iew.wb_sent 6630 # cumulative count of insts sent to commit 585system.cpu.iew.wb_count 6587 # cumulative count of insts written-back 586system.cpu.iew.wb_producers 2990 # num instructions producing a value 587system.cpu.iew.wb_consumers 5391 # num instructions consuming a value |
| 574system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 588system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 575system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle 576system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back | 589system.cpu.iew.wb_rate 0.199757 # insts written-back per cycle 590system.cpu.iew.wb_fanout 0.554628 # average fanout of values written-back |
| 577system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 591system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 578system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit | 592system.cpu.commit.commitSquashedInsts 2570 # The number of squashed insts skipped by commit |
| 579system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards | 593system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards |
| 580system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted 581system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle 582system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle 583system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle | 594system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted 595system.cpu.commit.committed_per_cycle::samples 14256 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::mean 0.377175 # Number of insts commited each cycle 597system.cpu.commit.committed_per_cycle::stdev 1.026651 # Number of insts commited each cycle |
| 584system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 598system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 585system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle 586system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle 587system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle 588system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle 589system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle 590system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle 591system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle 592system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle 593system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle | 599system.cpu.commit.committed_per_cycle::0 11607 81.42% 81.42% # Number of insts commited each cycle 600system.cpu.commit.committed_per_cycle::1 1384 9.71% 91.13% # Number of insts commited each cycle 601system.cpu.commit.committed_per_cycle::2 607 4.26% 95.38% # Number of insts commited each cycle 602system.cpu.commit.committed_per_cycle::3 292 2.05% 97.43% # Number of insts commited each cycle 603system.cpu.commit.committed_per_cycle::4 168 1.18% 98.61% # Number of insts commited each cycle 604system.cpu.commit.committed_per_cycle::5 76 0.53% 99.14% # Number of insts commited each cycle 605system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle 606system.cpu.commit.committed_per_cycle::7 33 0.23% 99.70% # Number of insts commited each cycle 607system.cpu.commit.committed_per_cycle::8 43 0.30% 100.00% # Number of insts commited each cycle |
| 594system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 595system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 596system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 608system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 609system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 610system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 597system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle | 611system.cpu.commit.committed_per_cycle::total 14256 # Number of insts commited each cycle |
| 598system.cpu.commit.committedInsts 4591 # Number of instructions committed 599system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 600system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 601system.cpu.commit.refs 1965 # Number of memory references committed 602system.cpu.commit.loads 1027 # Number of loads committed 603system.cpu.commit.membars 12 # Number of memory barriers committed 604system.cpu.commit.branches 1007 # Number of branches committed 605system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 635system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 636system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 637system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 638system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 639system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 640system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 641system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 642system.cpu.commit.op_class_0::total 5377 # Class of committed instruction | 612system.cpu.commit.committedInsts 4591 # Number of instructions committed 613system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 614system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 615system.cpu.commit.refs 1965 # Number of memory references committed 616system.cpu.commit.loads 1027 # Number of loads committed 617system.cpu.commit.membars 12 # Number of memory barriers committed 618system.cpu.commit.branches 1007 # Number of branches committed 619system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 649system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 650system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 651system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 652system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 653system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 654system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 655system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 656system.cpu.commit.op_class_0::total 5377 # Class of committed instruction |
| 643system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached | 657system.cpu.commit.bw_lim_events 43 # number cycles where commit BW limit reached |
| 644system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 658system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 645system.cpu.rob.rob_reads 24066 # The number of ROB reads 646system.cpu.rob.rob_writes 16750 # The number of ROB writes 647system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself 648system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling | 659system.cpu.rob.rob_reads 22003 # The number of ROB reads 660system.cpu.rob.rob_writes 16441 # The number of ROB writes 661system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself 662system.cpu.idleCycles 18177 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 649system.cpu.committedInsts 4591 # Number of Instructions Simulated 650system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated | 663system.cpu.committedInsts 4591 # Number of Instructions Simulated 664system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated |
| 651system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction 652system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads 653system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle 654system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads 655system.cpu.int_regfile_reads 6787 # number of integer regfile reads 656system.cpu.int_regfile_writes 3839 # number of integer regfile writes | 665system.cpu.cpi 7.182531 # CPI: Cycles Per Instruction 666system.cpu.cpi_total 7.182531 # CPI: Total CPI of All Threads 667system.cpu.ipc 0.139227 # IPC: Instructions Per Cycle 668system.cpu.ipc_total 0.139227 # IPC: Total IPC of All Threads 669system.cpu.int_regfile_reads 6737 # number of integer regfile reads 670system.cpu.int_regfile_writes 3765 # number of integer regfile writes |
| 657system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 671system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 658system.cpu.cc_regfile_reads 24301 # number of cc regfile reads 659system.cpu.cc_regfile_writes 2919 # number of cc regfile writes 660system.cpu.misc_regfile_reads 2642 # number of misc regfile reads | 672system.cpu.cc_regfile_reads 24010 # number of cc regfile reads 673system.cpu.cc_regfile_writes 2910 # number of cc regfile writes 674system.cpu.misc_regfile_reads 2599 # number of misc regfile reads |
| 661system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 675system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 662system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution 663system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution 664system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution 665system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution 666system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution 667system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) 668system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) 669system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) 670system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) 671system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) 672system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 673system.cpu.toL2Bus.snoops 1026 # Total snoops (count) 674system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram 675system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram 676system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram 677system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 678system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 679system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 680system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 681system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 682system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 683system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram 684system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram 685system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 686system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 687system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 688system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram 689system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) 690system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 691system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) 692system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) 693system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) 694system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 695system.cpu.icache.tags.replacements 47 # number of replacements 696system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use 697system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. 698system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. 699system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. | 676system.cpu.dcache.tags.replacements 1 # number of replacements 677system.cpu.dcache.tags.tagsinuse 84.720980 # Cycle average of tags in use 678system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. 679system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 680system.cpu.dcache.tags.avg_refs 13.352113 # Average number of references to valid blocks. 681system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 682system.cpu.dcache.tags.occ_blocks::cpu.data 84.720980 # Average occupied blocks per requestor 683system.cpu.dcache.tags.occ_percent::cpu.data 0.165471 # Average percentage of cache occupancy 684system.cpu.dcache.tags.occ_percent::total 0.165471 # Average percentage of cache occupancy 685system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id 686system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 687system.cpu.dcache.tags.age_task_id_blocks_1024::1 74 # Occupied blocks per task id 688system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id 689system.cpu.dcache.tags.tag_accesses 4676 # Number of tag accesses 690system.cpu.dcache.tags.data_accesses 4676 # Number of data accesses 691system.cpu.dcache.ReadReq_hits::cpu.data 1154 # number of ReadReq hits 692system.cpu.dcache.ReadReq_hits::total 1154 # number of ReadReq hits 693system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits 694system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits 695system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits 696system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits 697system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 698system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 699system.cpu.dcache.demand_hits::cpu.data 1876 # number of demand (read+write) hits 700system.cpu.dcache.demand_hits::total 1876 # number of demand (read+write) hits 701system.cpu.dcache.overall_hits::cpu.data 1876 # number of overall hits 702system.cpu.dcache.overall_hits::total 1876 # number of overall hits 703system.cpu.dcache.ReadReq_misses::cpu.data 178 # number of ReadReq misses 704system.cpu.dcache.ReadReq_misses::total 178 # number of ReadReq misses 705system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses 706system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses 707system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 708system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 709system.cpu.dcache.demand_misses::cpu.data 369 # number of demand (read+write) misses 710system.cpu.dcache.demand_misses::total 369 # number of demand (read+write) misses 711system.cpu.dcache.overall_misses::cpu.data 369 # number of overall misses 712system.cpu.dcache.overall_misses::total 369 # number of overall misses 713system.cpu.dcache.ReadReq_miss_latency::cpu.data 8985992 # number of ReadReq miss cycles 714system.cpu.dcache.ReadReq_miss_latency::total 8985992 # number of ReadReq miss cycles 715system.cpu.dcache.WriteReq_miss_latency::cpu.data 6715000 # number of WriteReq miss cycles 716system.cpu.dcache.WriteReq_miss_latency::total 6715000 # number of WriteReq miss cycles 717system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 112000 # number of LoadLockedReq miss cycles 718system.cpu.dcache.LoadLockedReq_miss_latency::total 112000 # number of LoadLockedReq miss cycles 719system.cpu.dcache.demand_miss_latency::cpu.data 15700992 # number of demand (read+write) miss cycles 720system.cpu.dcache.demand_miss_latency::total 15700992 # number of demand (read+write) miss cycles 721system.cpu.dcache.overall_miss_latency::cpu.data 15700992 # number of overall miss cycles 722system.cpu.dcache.overall_miss_latency::total 15700992 # number of overall miss cycles 723system.cpu.dcache.ReadReq_accesses::cpu.data 1332 # number of ReadReq accesses(hits+misses) 724system.cpu.dcache.ReadReq_accesses::total 1332 # number of ReadReq accesses(hits+misses) 725system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 726system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 727system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) 728system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) 729system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 730system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 731system.cpu.dcache.demand_accesses::cpu.data 2245 # number of demand (read+write) accesses 732system.cpu.dcache.demand_accesses::total 2245 # number of demand (read+write) accesses 733system.cpu.dcache.overall_accesses::cpu.data 2245 # number of overall (read+write) accesses 734system.cpu.dcache.overall_accesses::total 2245 # number of overall (read+write) accesses 735system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.133634 # miss rate for ReadReq accesses 736system.cpu.dcache.ReadReq_miss_rate::total 0.133634 # miss rate for ReadReq accesses 737system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses 738system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses 739system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses 740system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses 741system.cpu.dcache.demand_miss_rate::cpu.data 0.164365 # miss rate for demand accesses 742system.cpu.dcache.demand_miss_rate::total 0.164365 # miss rate for demand accesses 743system.cpu.dcache.overall_miss_rate::cpu.data 0.164365 # miss rate for overall accesses 744system.cpu.dcache.overall_miss_rate::total 0.164365 # miss rate for overall accesses 745system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50483.101124 # average ReadReq miss latency 746system.cpu.dcache.ReadReq_avg_miss_latency::total 50483.101124 # average ReadReq miss latency 747system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35157.068063 # average WriteReq miss latency 748system.cpu.dcache.WriteReq_avg_miss_latency::total 35157.068063 # average WriteReq miss latency 749system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 56000 # average LoadLockedReq miss latency 750system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 56000 # average LoadLockedReq miss latency 751system.cpu.dcache.demand_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 752system.cpu.dcache.demand_avg_miss_latency::total 42550.113821 # average overall miss latency 753system.cpu.dcache.overall_avg_miss_latency::cpu.data 42550.113821 # average overall miss latency 754system.cpu.dcache.overall_avg_miss_latency::total 42550.113821 # average overall miss latency 755system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 756system.cpu.dcache.blocked_cycles::no_targets 646 # number of cycles access was blocked 757system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 758system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 759system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 760system.cpu.dcache.avg_blocked_cycles::no_targets 35.888889 # average number of cycles each access was blocked 761system.cpu.dcache.fast_writes 0 # number of fast writes performed 762system.cpu.dcache.cache_copies 0 # number of cache copies performed 763system.cpu.dcache.ReadReq_mshr_hits::cpu.data 76 # number of ReadReq MSHR hits 764system.cpu.dcache.ReadReq_mshr_hits::total 76 # number of ReadReq MSHR hits 765system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits 766system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits 767system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 768system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 769system.cpu.dcache.demand_mshr_hits::cpu.data 226 # number of demand (read+write) MSHR hits 770system.cpu.dcache.demand_mshr_hits::total 226 # number of demand (read+write) MSHR hits 771system.cpu.dcache.overall_mshr_hits::cpu.data 226 # number of overall MSHR hits 772system.cpu.dcache.overall_mshr_hits::total 226 # number of overall MSHR hits 773system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses 774system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses 775system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses 776system.cpu.dcache.WriteReq_mshr_misses::total 41 # number of WriteReq MSHR misses 777system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses 778system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses 779system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses 780system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses 781system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5294755 # number of ReadReq MSHR miss cycles 782system.cpu.dcache.ReadReq_mshr_miss_latency::total 5294755 # number of ReadReq MSHR miss cycles 783system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2189500 # number of WriteReq MSHR miss cycles 784system.cpu.dcache.WriteReq_mshr_miss_latency::total 2189500 # number of WriteReq MSHR miss cycles 785system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7484255 # number of demand (read+write) MSHR miss cycles 786system.cpu.dcache.demand_mshr_miss_latency::total 7484255 # number of demand (read+write) MSHR miss cycles 787system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7484255 # number of overall MSHR miss cycles 788system.cpu.dcache.overall_mshr_miss_latency::total 7484255 # number of overall MSHR miss cycles 789system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076577 # mshr miss rate for ReadReq accesses 790system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076577 # mshr miss rate for ReadReq accesses 791system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses 792system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses 793system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for demand accesses 794system.cpu.dcache.demand_mshr_miss_rate::total 0.063697 # mshr miss rate for demand accesses 795system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063697 # mshr miss rate for overall accesses 796system.cpu.dcache.overall_mshr_miss_rate::total 0.063697 # mshr miss rate for overall accesses 797system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51909.362745 # average ReadReq mshr miss latency 798system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51909.362745 # average ReadReq mshr miss latency 799system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53402.439024 # average WriteReq mshr miss latency 800system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53402.439024 # average WriteReq mshr miss latency 801system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 802system.cpu.dcache.demand_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency 803system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52337.447552 # average overall mshr miss latency 804system.cpu.dcache.overall_avg_mshr_miss_latency::total 52337.447552 # average overall mshr miss latency 805system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 806system.cpu.icache.tags.replacements 42 # number of replacements 807system.cpu.icache.tags.tagsinuse 138.060100 # Cycle average of tags in use 808system.cpu.icache.tags.total_refs 3485 # Total number of references to valid blocks. 809system.cpu.icache.tags.sampled_refs 296 # Sample count of references to valid blocks. 810system.cpu.icache.tags.avg_refs 11.773649 # Average number of references to valid blocks. |
| 700system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 811system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 701system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor 702system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy 703system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy 704system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 705system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 706system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 707system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id 708system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses 709system.cpu.icache.tags.data_accesses 8536 # Number of data accesses 710system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits 711system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits 712system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits 713system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits 714system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits 715system.cpu.icache.overall_hits::total 3784 # number of overall hits 716system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses 717system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses 718system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses 719system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses 720system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses 721system.cpu.icache.overall_misses::total 332 # number of overall misses 722system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles 723system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles 724system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles 725system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles 726system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles 727system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles 728system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses) 729system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses) 730system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses 731system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses 732system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses 733system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses 734system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses 735system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses 736system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses 737system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses 738system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses 739system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses 740system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency 741system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency 742system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 743system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency 744system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 745system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency 746system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked 747system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 748system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked 749system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 750system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked 751system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 812system.cpu.icache.tags.occ_blocks::cpu.inst 138.060100 # Average occupied blocks per requestor 813system.cpu.icache.tags.occ_percent::cpu.inst 0.269649 # Average percentage of cache occupancy 814system.cpu.icache.tags.occ_percent::total 0.269649 # Average percentage of cache occupancy 815system.cpu.icache.tags.occ_task_id_blocks::1024 254 # Occupied blocks per task id 816system.cpu.icache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 817system.cpu.icache.tags.age_task_id_blocks_1024::1 87 # Occupied blocks per task id 818system.cpu.icache.tags.occ_task_id_percent::1024 0.496094 # Percentage of cache occupancy per task id 819system.cpu.icache.tags.tag_accesses 7990 # Number of tag accesses 820system.cpu.icache.tags.data_accesses 7990 # Number of data accesses 821system.cpu.icache.ReadReq_hits::cpu.inst 3485 # number of ReadReq hits 822system.cpu.icache.ReadReq_hits::total 3485 # number of ReadReq hits 823system.cpu.icache.demand_hits::cpu.inst 3485 # number of demand (read+write) hits 824system.cpu.icache.demand_hits::total 3485 # number of demand (read+write) hits 825system.cpu.icache.overall_hits::cpu.inst 3485 # number of overall hits 826system.cpu.icache.overall_hits::total 3485 # number of overall hits 827system.cpu.icache.ReadReq_misses::cpu.inst 362 # number of ReadReq misses 828system.cpu.icache.ReadReq_misses::total 362 # number of ReadReq misses 829system.cpu.icache.demand_misses::cpu.inst 362 # number of demand (read+write) misses 830system.cpu.icache.demand_misses::total 362 # number of demand (read+write) misses 831system.cpu.icache.overall_misses::cpu.inst 362 # number of overall misses 832system.cpu.icache.overall_misses::total 362 # number of overall misses 833system.cpu.icache.ReadReq_miss_latency::cpu.inst 19725741 # number of ReadReq miss cycles 834system.cpu.icache.ReadReq_miss_latency::total 19725741 # number of ReadReq miss cycles 835system.cpu.icache.demand_miss_latency::cpu.inst 19725741 # number of demand (read+write) miss cycles 836system.cpu.icache.demand_miss_latency::total 19725741 # number of demand (read+write) miss cycles 837system.cpu.icache.overall_miss_latency::cpu.inst 19725741 # number of overall miss cycles 838system.cpu.icache.overall_miss_latency::total 19725741 # number of overall miss cycles 839system.cpu.icache.ReadReq_accesses::cpu.inst 3847 # number of ReadReq accesses(hits+misses) 840system.cpu.icache.ReadReq_accesses::total 3847 # number of ReadReq accesses(hits+misses) 841system.cpu.icache.demand_accesses::cpu.inst 3847 # number of demand (read+write) accesses 842system.cpu.icache.demand_accesses::total 3847 # number of demand (read+write) accesses 843system.cpu.icache.overall_accesses::cpu.inst 3847 # number of overall (read+write) accesses 844system.cpu.icache.overall_accesses::total 3847 # number of overall (read+write) accesses 845system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094099 # miss rate for ReadReq accesses 846system.cpu.icache.ReadReq_miss_rate::total 0.094099 # miss rate for ReadReq accesses 847system.cpu.icache.demand_miss_rate::cpu.inst 0.094099 # miss rate for demand accesses 848system.cpu.icache.demand_miss_rate::total 0.094099 # miss rate for demand accesses 849system.cpu.icache.overall_miss_rate::cpu.inst 0.094099 # miss rate for overall accesses 850system.cpu.icache.overall_miss_rate::total 0.094099 # miss rate for overall accesses 851system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54490.997238 # average ReadReq miss latency 852system.cpu.icache.ReadReq_avg_miss_latency::total 54490.997238 # average ReadReq miss latency 853system.cpu.icache.demand_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 854system.cpu.icache.demand_avg_miss_latency::total 54490.997238 # average overall miss latency 855system.cpu.icache.overall_avg_miss_latency::cpu.inst 54490.997238 # average overall miss latency 856system.cpu.icache.overall_avg_miss_latency::total 54490.997238 # average overall miss latency 857system.cpu.icache.blocked_cycles::no_mshrs 7642 # number of cycles access was blocked 858system.cpu.icache.blocked_cycles::no_targets 18 # number of cycles access was blocked 859system.cpu.icache.blocked::no_mshrs 94 # number of cycles access was blocked 860system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked 861system.cpu.icache.avg_blocked_cycles::no_mshrs 81.297872 # average number of cycles each access was blocked 862system.cpu.icache.avg_blocked_cycles::no_targets 18 # average number of cycles each access was blocked |
| 752system.cpu.icache.fast_writes 0 # number of fast writes performed 753system.cpu.icache.cache_copies 0 # number of cache copies performed | 863system.cpu.icache.fast_writes 0 # number of fast writes performed 864system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 754system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits 755system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 756system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits 757system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 758system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits 759system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits 760system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 761system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 762system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 763system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 764system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 765system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 766system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles 767system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles 768system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles 769system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles 770system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles 771system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles 772system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses 773system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses 774system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses 775system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses 776system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses 777system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses 778system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency 779system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency 780system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 781system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency 782system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 783system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency | 865system.cpu.icache.ReadReq_mshr_hits::cpu.inst 65 # number of ReadReq MSHR hits 866system.cpu.icache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits 867system.cpu.icache.demand_mshr_hits::cpu.inst 65 # number of demand (read+write) MSHR hits 868system.cpu.icache.demand_mshr_hits::total 65 # number of demand (read+write) MSHR hits 869system.cpu.icache.overall_mshr_hits::cpu.inst 65 # number of overall MSHR hits 870system.cpu.icache.overall_mshr_hits::total 65 # number of overall MSHR hits 871system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses 872system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses 873system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses 874system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses 875system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses 876system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses 877system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16894743 # number of ReadReq MSHR miss cycles 878system.cpu.icache.ReadReq_mshr_miss_latency::total 16894743 # number of ReadReq MSHR miss cycles 879system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16894743 # number of demand (read+write) MSHR miss cycles 880system.cpu.icache.demand_mshr_miss_latency::total 16894743 # number of demand (read+write) MSHR miss cycles 881system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16894743 # number of overall MSHR miss cycles 882system.cpu.icache.overall_mshr_miss_latency::total 16894743 # number of overall MSHR miss cycles 883system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for ReadReq accesses 884system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077203 # mshr miss rate for ReadReq accesses 885system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for demand accesses 886system.cpu.icache.demand_mshr_miss_rate::total 0.077203 # mshr miss rate for demand accesses 887system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077203 # mshr miss rate for overall accesses 888system.cpu.icache.overall_mshr_miss_rate::total 0.077203 # mshr miss rate for overall accesses 889system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 56884.656566 # average ReadReq mshr miss latency 890system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 56884.656566 # average ReadReq mshr miss latency 891system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 892system.cpu.icache.demand_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency 893system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 56884.656566 # average overall mshr miss latency 894system.cpu.icache.overall_avg_mshr_miss_latency::total 56884.656566 # average overall mshr miss latency |
| 784system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 895system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 785system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified 786system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr 787system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache 788system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue 789system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 790system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated 791system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued 792system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page 793system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time | 896system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued 897system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified 898system.cpu.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue 899system.cpu.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 900system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size 901system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing |
| 794system.cpu.l2cache.tags.replacements 0 # number of replacements | 902system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 795system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use 796system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks. 797system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks. 798system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks. | 903system.cpu.l2cache.tags.tagsinuse 195.136661 # Cycle average of tags in use 904system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. 905system.cpu.l2cache.tags.sampled_refs 365 # Sample count of references to valid blocks. 906system.cpu.l2cache.tags.avg_refs 0.115068 # Average number of references to valid blocks. |
| 799system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 907system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 800system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor 801system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor 802system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor 803system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy 804system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy 805system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy 806system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy 807system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id 808system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id 809system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id 810system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id 811system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 812system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 813system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id 814system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id 815system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses 816system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses 817system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits 818system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits 819system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits | 908system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.591914 # Average occupied blocks per requestor 909system.cpu.l2cache.tags.occ_blocks::cpu.data 45.333856 # Average occupied blocks per requestor 910system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.210892 # Average occupied blocks per requestor 911system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008581 # Average percentage of cache occupancy 912system.cpu.l2cache.tags.occ_percent::cpu.data 0.002767 # Average percentage of cache occupancy 913system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000562 # Average percentage of cache occupancy 914system.cpu.l2cache.tags.occ_percent::total 0.011910 # Average percentage of cache occupancy 915system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id 916system.cpu.l2cache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 917system.cpu.l2cache.tags.age_task_id_blocks_1022::0 13 # Occupied blocks per task id 918system.cpu.l2cache.tags.age_task_id_blocks_1022::1 3 # Occupied blocks per task id 919system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 920system.cpu.l2cache.tags.age_task_id_blocks_1024::1 162 # Occupied blocks per task id 921system.cpu.l2cache.tags.occ_task_id_percent::1022 0.000977 # Percentage of cache occupancy per task id 922system.cpu.l2cache.tags.occ_task_id_percent::1024 0.021301 # Percentage of cache occupancy per task id 923system.cpu.l2cache.tags.tag_accesses 7446 # Number of tag accesses 924system.cpu.l2cache.tags.data_accesses 7446 # Number of data accesses 925system.cpu.l2cache.ReadReq_hits::cpu.inst 23 # number of ReadReq hits 926system.cpu.l2cache.ReadReq_hits::cpu.data 19 # number of ReadReq hits 927system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits |
| 820system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 821system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits | 928system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 929system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits |
| 822system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits 823system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits 824system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits 825system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits 826system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits 827system.cpu.l2cache.overall_hits::total 280 # number of overall hits 828system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses 829system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses 830system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses 831system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses 832system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses 833system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses 834system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses 835system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses 836system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses 837system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses 838system.cpu.l2cache.overall_misses::total 168 # number of overall misses 839system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles 840system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles 841system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles 843system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles 844system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles 845system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles 846system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles 847system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles 848system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles 849system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles 850system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 851system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 852system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) 853system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses) 854system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses) 855system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 856system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 857system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses 858system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 859system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 860system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses 861system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses 862system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses 863system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses 864system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses 865system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses 866system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses 867system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses 868system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses 869system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses 870system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses 871system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses 872system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency 873system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency 874system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency 875system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency 876system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency 877system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 878system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 879system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency 880system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 881system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 882system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency 883system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked | 930system.cpu.l2cache.demand_hits::cpu.inst 23 # number of demand (read+write) hits 931system.cpu.l2cache.demand_hits::cpu.data 30 # number of demand (read+write) hits 932system.cpu.l2cache.demand_hits::total 53 # number of demand (read+write) hits 933system.cpu.l2cache.overall_hits::cpu.inst 23 # number of overall hits 934system.cpu.l2cache.overall_hits::cpu.data 30 # number of overall hits 935system.cpu.l2cache.overall_hits::total 53 # number of overall hits 936system.cpu.l2cache.ReadReq_misses::cpu.inst 274 # number of ReadReq misses 937system.cpu.l2cache.ReadReq_misses::cpu.data 83 # number of ReadReq misses 938system.cpu.l2cache.ReadReq_misses::total 357 # number of ReadReq misses 939system.cpu.l2cache.ReadExReq_misses::cpu.data 30 # number of ReadExReq misses 940system.cpu.l2cache.ReadExReq_misses::total 30 # number of ReadExReq misses 941system.cpu.l2cache.demand_misses::cpu.inst 274 # number of demand (read+write) misses 942system.cpu.l2cache.demand_misses::cpu.data 113 # number of demand (read+write) misses 943system.cpu.l2cache.demand_misses::total 387 # number of demand (read+write) misses 944system.cpu.l2cache.overall_misses::cpu.inst 274 # number of overall misses 945system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses 946system.cpu.l2cache.overall_misses::total 387 # number of overall misses 947system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16599750 # number of ReadReq miss cycles 948system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5077250 # number of ReadReq miss cycles 949system.cpu.l2cache.ReadReq_miss_latency::total 21677000 # number of ReadReq miss cycles 950system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2079500 # number of ReadExReq miss cycles 951system.cpu.l2cache.ReadExReq_miss_latency::total 2079500 # number of ReadExReq miss cycles 952system.cpu.l2cache.demand_miss_latency::cpu.inst 16599750 # number of demand (read+write) miss cycles 953system.cpu.l2cache.demand_miss_latency::cpu.data 7156750 # number of demand (read+write) miss cycles 954system.cpu.l2cache.demand_miss_latency::total 23756500 # number of demand (read+write) miss cycles 955system.cpu.l2cache.overall_miss_latency::cpu.inst 16599750 # number of overall miss cycles 956system.cpu.l2cache.overall_miss_latency::cpu.data 7156750 # number of overall miss cycles 957system.cpu.l2cache.overall_miss_latency::total 23756500 # number of overall miss cycles 958system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses) 959system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) 960system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 961system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) 962system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) 963system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses 964system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses 965system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses 966system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses 967system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses 968system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses 969system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.922559 # miss rate for ReadReq accesses 970system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.813725 # miss rate for ReadReq accesses 971system.cpu.l2cache.ReadReq_miss_rate::total 0.894737 # miss rate for ReadReq accesses 972system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.731707 # miss rate for ReadExReq accesses 973system.cpu.l2cache.ReadExReq_miss_rate::total 0.731707 # miss rate for ReadExReq accesses 974system.cpu.l2cache.demand_miss_rate::cpu.inst 0.922559 # miss rate for demand accesses 975system.cpu.l2cache.demand_miss_rate::cpu.data 0.790210 # miss rate for demand accesses 976system.cpu.l2cache.demand_miss_rate::total 0.879545 # miss rate for demand accesses 977system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922559 # miss rate for overall accesses 978system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses 979system.cpu.l2cache.overall_miss_rate::total 0.879545 # miss rate for overall accesses 980system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 60583.029197 # average ReadReq miss latency 981system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 61171.686747 # average ReadReq miss latency 982system.cpu.l2cache.ReadReq_avg_miss_latency::total 60719.887955 # average ReadReq miss latency 983system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 69316.666667 # average ReadExReq miss latency 984system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69316.666667 # average ReadExReq miss latency 985system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 986system.cpu.l2cache.demand_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 987system.cpu.l2cache.demand_avg_miss_latency::total 61386.304910 # average overall miss latency 988system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60583.029197 # average overall miss latency 989system.cpu.l2cache.overall_avg_miss_latency::cpu.data 63334.070796 # average overall miss latency 990system.cpu.l2cache.overall_avg_miss_latency::total 61386.304910 # average overall miss latency 991system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| 884system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 992system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 885system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked | 993system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| 886system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 994system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 887system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked | 995system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| 888system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 889system.cpu.l2cache.fast_writes 0 # number of fast writes performed 890system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 996system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 997system.cpu.l2cache.fast_writes 0 # number of fast writes performed 998system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 891system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 892system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 893system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 894system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 895system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 896system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 897system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 898system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 899system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 900system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses 901system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 902system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses 903system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses 904system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses 905system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses 906system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses 907system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses 908system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses 909system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses 910system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses 911system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses 912system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses 913system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses 914system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles 915system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles 916system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles 917system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles 918system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles 919system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles 920system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles 921system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles 922system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles 923system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles 924system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles 925system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles 926system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles 927system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles 928system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses 929system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses 930system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses | 999system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits 1000system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 1001system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits 1002system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits 1003system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 1004system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits 1005system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits 1006system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 1007system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits 1008system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 273 # number of ReadReq MSHR misses 1009system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses 1010system.cpu.l2cache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses 1011system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 48 # number of HardPFReq MSHR misses 1012system.cpu.l2cache.HardPFReq_mshr_misses::total 48 # number of HardPFReq MSHR misses 1013system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 30 # number of ReadExReq MSHR misses 1014system.cpu.l2cache.ReadExReq_mshr_misses::total 30 # number of ReadExReq MSHR misses 1015system.cpu.l2cache.demand_mshr_misses::cpu.inst 273 # number of demand (read+write) MSHR misses 1016system.cpu.l2cache.demand_mshr_misses::cpu.data 108 # number of demand (read+write) MSHR misses 1017system.cpu.l2cache.demand_mshr_misses::total 381 # number of demand (read+write) MSHR misses 1018system.cpu.l2cache.overall_mshr_misses::cpu.inst 273 # number of overall MSHR misses 1019system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses 1020system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses 1021system.cpu.l2cache.overall_mshr_misses::total 429 # number of overall MSHR misses 1022system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 14211250 # number of ReadReq MSHR miss cycles 1023system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4185750 # number of ReadReq MSHR miss cycles 1024system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18397000 # number of ReadReq MSHR miss cycles 1025system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of HardPFReq MSHR miss cycles 1026system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1810701 # number of HardPFReq MSHR miss cycles 1027system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1833500 # number of ReadExReq MSHR miss cycles 1028system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1833500 # number of ReadExReq MSHR miss cycles 1029system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14211250 # number of demand (read+write) MSHR miss cycles 1030system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6019250 # number of demand (read+write) MSHR miss cycles 1031system.cpu.l2cache.demand_mshr_miss_latency::total 20230500 # number of demand (read+write) MSHR miss cycles 1032system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14211250 # number of overall MSHR miss cycles 1033system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6019250 # number of overall MSHR miss cycles 1034system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1810701 # number of overall MSHR miss cycles 1035system.cpu.l2cache.overall_mshr_miss_latency::total 22041201 # number of overall MSHR miss cycles 1036system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for ReadReq accesses 1037system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses 1038system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879699 # mshr miss rate for ReadReq accesses |
| 931system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 932system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses | 1039system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 1040system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses |
| 933system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses 934system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses 935system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses 936system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses 937system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses 938system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses 939system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses | 1041system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.731707 # mshr miss rate for ReadExReq accesses 1042system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.731707 # mshr miss rate for ReadExReq accesses 1043system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for demand accesses 1044system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for demand accesses 1045system.cpu.l2cache.demand_mshr_miss_rate::total 0.865909 # mshr miss rate for demand accesses 1046system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.919192 # mshr miss rate for overall accesses 1047system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses |
| 940system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses | 1048system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses |
| 941system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses 942system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency 943system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency 944system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency 945system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency 946system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency 947system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency 948system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency 949system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 950system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 951system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency 952system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 953system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 954system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency 955system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency | 1049system.cpu.l2cache.overall_mshr_miss_rate::total 0.975000 # mshr miss rate for overall accesses 1050system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 52055.860806 # average ReadReq mshr miss latency 1051system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 53663.461538 # average ReadReq mshr miss latency 1052system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 52413.105413 # average ReadReq mshr miss latency 1053system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average HardPFReq mshr miss latency 1054system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 37722.937500 # average HardPFReq mshr miss latency 1055system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61116.666667 # average ReadExReq mshr miss latency 1056system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61116.666667 # average ReadExReq mshr miss latency 1057system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 1058system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 1059system.cpu.l2cache.demand_avg_mshr_miss_latency::total 53098.425197 # average overall mshr miss latency 1060system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 52055.860806 # average overall mshr miss latency 1061system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55733.796296 # average overall mshr miss latency 1062system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 37722.937500 # average overall mshr miss latency 1063system.cpu.l2cache.overall_avg_mshr_miss_latency::total 51378.090909 # average overall mshr miss latency |
| 956system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 1064system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 957system.cpu.dcache.tags.replacements 1 # number of replacements 958system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use 959system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. 960system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 961system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. 962system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 963system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor 964system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy 965system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy 966system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 967system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 968system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 969system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 970system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses 971system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses 972system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits 973system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits 974system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits 975system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits 976system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 977system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits 978system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 979system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits 980system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits 981system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits 982system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits 983system.cpu.dcache.overall_hits::total 1873 # number of overall hits 984system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses 985system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses 986system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses 987system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses 988system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 989system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses 990system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses 991system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses 992system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses 993system.cpu.dcache.overall_misses::total 392 # number of overall misses 994system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles 995system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles 996system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles 997system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles 998system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles 999system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles 1000system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles 1001system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles 1002system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles 1003system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles 1004system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) 1005system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) 1006system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 1007system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) 1008system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 1009system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) 1010system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 1011system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) 1012system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses 1013system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses 1014system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses 1015system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses 1016system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses 1017system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses 1018system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses 1019system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses 1020system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 1021system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 1022system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses 1023system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses 1024system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses 1025system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses 1026system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency 1027system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency 1028system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency 1029system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency 1030system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency 1031system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency 1032system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1033system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency 1034system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1035system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency 1036system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked 1037system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked 1038system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 1039system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 1040system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked 1041system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked 1042system.cpu.dcache.fast_writes 0 # number of fast writes performed 1043system.cpu.dcache.cache_copies 0 # number of cache copies performed 1044system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits 1045system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 1046system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits 1047system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits 1048system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1049system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits 1050system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits 1051system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 1052system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits 1053system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 1054system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 1055system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 1056system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses 1057system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses 1058system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 1059system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 1060system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 1061system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 1062system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles 1063system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles 1064system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles 1065system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles 1066system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles 1067system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles 1068system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles 1069system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles 1070system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses 1071system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses 1072system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses 1073system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses 1074system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses 1075system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses 1076system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses 1077system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses 1078system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency 1079system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency 1080system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency 1081system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency 1082system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1083system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency 1084system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1085system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency 1086system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | 1065system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 1066system.cpu.toL2Bus.trans_dist::ReadResp 397 # Transaction distribution 1067system.cpu.toL2Bus.trans_dist::HardPFReq 67 # Transaction distribution 1068system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 1069system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 1070system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 593 # Packet count per connected master and slave (bytes) 1071system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 285 # Packet count per connected master and slave (bytes) 1072system.cpu.toL2Bus.pkt_count::total 878 # Packet count per connected master and slave (bytes) 1073system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18944 # Cumulative packet size per connected master and slave (bytes) 1074system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 1075system.cpu.toL2Bus.pkt_size::total 28032 # Cumulative packet size per connected master and slave (bytes) 1076system.cpu.toL2Bus.snoops 67 # Total snoops (count) 1077system.cpu.toL2Bus.snoop_fanout::samples 507 # Request fanout histogram 1078system.cpu.toL2Bus.snoop_fanout::mean 5.132150 # Request fanout histogram 1079system.cpu.toL2Bus.snoop_fanout::stdev 0.338988 # Request fanout histogram 1080system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1081system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 1082system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 1083system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 1084system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 1085system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 1086system.cpu.toL2Bus.snoop_fanout::5 440 86.79% 86.79% # Request fanout histogram 1087system.cpu.toL2Bus.snoop_fanout::6 67 13.21% 100.00% # Request fanout histogram 1088system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1089system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 1090system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 1091system.cpu.toL2Bus.snoop_fanout::total 507 # Request fanout histogram 1092system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) 1093system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) 1094system.cpu.toL2Bus.respLayer0.occupancy 493249 # Layer occupancy (ticks) 1095system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 1096system.cpu.toL2Bus.respLayer1.occupancy 222745 # Layer occupancy (ticks) 1097system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 1098system.membus.trans_dist::ReadReq 378 # Transaction distribution 1099system.membus.trans_dist::ReadResp 376 # Transaction distribution 1100system.membus.trans_dist::ReadExReq 30 # Transaction distribution 1101system.membus.trans_dist::ReadExResp 30 # Transaction distribution 1102system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 814 # Packet count per connected master and slave (bytes) 1103system.membus.pkt_count::total 814 # Packet count per connected master and slave (bytes) 1104system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25984 # Cumulative packet size per connected master and slave (bytes) 1105system.membus.pkt_size::total 25984 # Cumulative packet size per connected master and slave (bytes) 1106system.membus.snoops 0 # Total snoops (count) 1107system.membus.snoop_fanout::samples 408 # Request fanout histogram 1108system.membus.snoop_fanout::mean 0 # Request fanout histogram 1109system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1110system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1111system.membus.snoop_fanout::0 408 100.00% 100.00% # Request fanout histogram 1112system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1113system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1114system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1115system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1116system.membus.snoop_fanout::total 408 # Request fanout histogram 1117system.membus.reqLayer0.occupancy 506687 # Layer occupancy (ticks) 1118system.membus.reqLayer0.utilization 3.1 # Layer utilization (%) 1119system.membus.respLayer1.occupancy 3785965 # Layer occupancy (ticks) 1120system.membus.respLayer1.utilization 23.0 # Layer utilization (%) |
| 1087 1088---------- End Simulation Statistics ---------- | 1121 1122---------- End Simulation Statistics ---------- |