| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000016 # Number of seconds simulated 4sim_ticks 16223000 # Number of ticks simulated 5final_tick 16223000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000012 # Number of seconds simulated 4sim_ticks 11859500 # Number of ticks simulated 5final_tick 11859500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 35590 # Simulator instruction rate (inst/s) 8host_op_rate 41676 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 125719954 # Simulator tick rate (ticks/s) 10host_mem_usage 252016 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 50616 # Simulator instruction rate (inst/s) 8host_op_rate 59274 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 130716325 # Simulator tick rate (ticks/s) 10host_mem_usage 300356 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5377 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.bytes_read::cpu.inst 17600 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25408 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17600 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 17600 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 275 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 397 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1084879492 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 481291993 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1566171485 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1084879492 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1084879492 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1084879492 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 481291993 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1566171485 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 397 # Number of read requests accepted | 16system.physmem.bytes_read::cpu.inst 3776 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 5888 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.l2cache.prefetcher 37184 # Number of bytes read from this memory 19system.physmem.bytes_read::total 46848 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 3776 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 3776 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 59 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 92 # Number of read requests responded to by this memory 24system.physmem.num_reads::cpu.l2cache.prefetcher 581 # Number of read requests responded to by this memory 25system.physmem.num_reads::total 732 # Number of read requests responded to by this memory 26system.physmem.bw_read::cpu.inst 318394536 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::cpu.data 496479615 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_read::cpu.l2cache.prefetcher 3135376702 # Total read bandwidth from this memory (bytes/s) 29system.physmem.bw_read::total 3950250854 # Total read bandwidth from this memory (bytes/s) 30system.physmem.bw_inst_read::cpu.inst 318394536 # Instruction read bandwidth from this memory (bytes/s) 31system.physmem.bw_inst_read::total 318394536 # Instruction read bandwidth from this memory (bytes/s) 32system.physmem.bw_total::cpu.inst 318394536 # Total bandwidth to/from this memory (bytes/s) 33system.physmem.bw_total::cpu.data 496479615 # Total bandwidth to/from this memory (bytes/s) 34system.physmem.bw_total::cpu.l2cache.prefetcher 3135376702 # Total bandwidth to/from this memory (bytes/s) 35system.physmem.bw_total::total 3950250854 # Total bandwidth to/from this memory (bytes/s) 36system.physmem.readReqs 733 # Number of read requests accepted |
| 33system.physmem.writeReqs 0 # Number of write requests accepted | 37system.physmem.writeReqs 0 # Number of write requests accepted |
| 34system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue | 38system.physmem.readBursts 733 # Number of DRAM read bursts, including those serviced by the write queue |
| 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue | 39system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue |
| 36system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM | 40system.physmem.bytesReadDRAM 46912 # Total number of bytes read from DRAM |
| 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM | 41system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 42system.physmem.bytesWritten 0 # Total number of bytes written to DRAM |
| 39system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side | 43system.physmem.bytesReadSys 46912 # Total read bytes from the system interface side |
| 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 44system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 45system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 46system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 47system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 44system.physmem.perBankRdBursts::0 90 # Per bank write bursts 45system.physmem.perBankRdBursts::1 46 # Per bank write bursts 46system.physmem.perBankRdBursts::2 20 # Per bank write bursts 47system.physmem.perBankRdBursts::3 43 # Per bank write bursts 48system.physmem.perBankRdBursts::4 18 # Per bank write bursts 49system.physmem.perBankRdBursts::5 32 # Per bank write bursts 50system.physmem.perBankRdBursts::6 35 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 4 # Per bank write bursts 53system.physmem.perBankRdBursts::9 8 # Per bank write bursts 54system.physmem.perBankRdBursts::10 28 # Per bank write bursts 55system.physmem.perBankRdBursts::11 42 # Per bank write bursts 56system.physmem.perBankRdBursts::12 9 # Per bank write bursts 57system.physmem.perBankRdBursts::13 6 # Per bank write bursts | 48system.physmem.perBankRdBursts::0 143 # Per bank write bursts 49system.physmem.perBankRdBursts::1 90 # Per bank write bursts 50system.physmem.perBankRdBursts::2 40 # Per bank write bursts 51system.physmem.perBankRdBursts::3 73 # Per bank write bursts 52system.physmem.perBankRdBursts::4 58 # Per bank write bursts 53system.physmem.perBankRdBursts::5 88 # Per bank write bursts 54system.physmem.perBankRdBursts::6 52 # Per bank write bursts 55system.physmem.perBankRdBursts::7 18 # Per bank write bursts 56system.physmem.perBankRdBursts::8 12 # Per bank write bursts 57system.physmem.perBankRdBursts::9 28 # Per bank write bursts 58system.physmem.perBankRdBursts::10 34 # Per bank write bursts 59system.physmem.perBankRdBursts::11 47 # Per bank write bursts 60system.physmem.perBankRdBursts::12 17 # Per bank write bursts 61system.physmem.perBankRdBursts::13 19 # Per bank write bursts |
| 58system.physmem.perBankRdBursts::14 0 # Per bank write bursts | 62system.physmem.perBankRdBursts::14 0 # Per bank write bursts |
| 59system.physmem.perBankRdBursts::15 6 # Per bank write bursts | 63system.physmem.perBankRdBursts::15 14 # Per bank write bursts |
| 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 64system.physmem.perBankWrBursts::0 0 # Per bank write bursts 65system.physmem.perBankWrBursts::1 0 # Per bank write bursts 66system.physmem.perBankWrBursts::2 0 # Per bank write bursts 67system.physmem.perBankWrBursts::3 0 # Per bank write bursts 68system.physmem.perBankWrBursts::4 0 # Per bank write bursts 69system.physmem.perBankWrBursts::5 0 # Per bank write bursts 70system.physmem.perBankWrBursts::6 0 # Per bank write bursts 71system.physmem.perBankWrBursts::7 0 # Per bank write bursts 72system.physmem.perBankWrBursts::8 0 # Per bank write bursts 73system.physmem.perBankWrBursts::9 0 # Per bank write bursts 74system.physmem.perBankWrBursts::10 0 # Per bank write bursts 75system.physmem.perBankWrBursts::11 0 # Per bank write bursts 76system.physmem.perBankWrBursts::12 0 # Per bank write bursts 77system.physmem.perBankWrBursts::13 0 # Per bank write bursts 78system.physmem.perBankWrBursts::14 0 # Per bank write bursts 79system.physmem.perBankWrBursts::15 0 # Per bank write bursts 80system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 81system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 16156000 # Total gap between requests | 82system.physmem.totGap 11846500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) | 83system.physmem.readPktSize::0 0 # Read request sizes (log2) 84system.physmem.readPktSize::1 0 # Read request sizes (log2) 85system.physmem.readPktSize::2 0 # Read request sizes (log2) 86system.physmem.readPktSize::3 0 # Read request sizes (log2) 87system.physmem.readPktSize::4 0 # Read request sizes (log2) 88system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| 85system.physmem.readPktSize::6 397 # Read request sizes (log2) | 89system.physmem.readPktSize::6 733 # Read request sizes (log2) |
| 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 90system.physmem.writePktSize::0 0 # Write request sizes (log2) 91system.physmem.writePktSize::1 0 # Write request sizes (log2) 92system.physmem.writePktSize::2 0 # Write request sizes (log2) 93system.physmem.writePktSize::3 0 # Write request sizes (log2) 94system.physmem.writePktSize::4 0 # Write request sizes (log2) 95system.physmem.writePktSize::5 0 # Write request sizes (log2) 96system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 210 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 119 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::0 96 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::2 83 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::3 79 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::4 68 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::5 60 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::6 51 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::7 53 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::8 48 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::9 26 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::10 17 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::11 18 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::12 6 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::13 8 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::15 2 # What read queue length does an incoming req see |
| 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 113system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see --- 64 unchanged lines hidden (view full) --- 185system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 190system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 191system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 192system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 396.190476 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 265.364013 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 334.900990 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 12 19.05% 19.05% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 16 25.40% 44.44% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 12.70% 57.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 9 14.29% 71.43% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 4.76% 84.13% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation 202system.physmem.totQLat 2970000 # Total ticks spent queuing 203system.physmem.totMemAccLat 10413750 # Total ticks spent from burst creation until serviced by the DRAM 204system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers 205system.physmem.avgQLat 7481.11 # Average queueing delay per DRAM burst | 193system.physmem.bytesPerActivate::samples 60 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::mean 712.533333 # Bytes accessed per row activation 195system.physmem.bytesPerActivate::gmean 570.872295 # Bytes accessed per row activation 196system.physmem.bytesPerActivate::stdev 336.283550 # Bytes accessed per row activation 197system.physmem.bytesPerActivate::0-127 4 6.67% 6.67% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::128-255 5 8.33% 15.00% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::256-383 4 6.67% 21.67% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::384-511 1 1.67% 23.33% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::512-639 4 6.67% 30.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::640-767 10 16.67% 46.67% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::768-895 4 6.67% 53.33% # Bytes accessed per row activation 204system.physmem.bytesPerActivate::896-1023 5 8.33% 61.67% # Bytes accessed per row activation 205system.physmem.bytesPerActivate::1024-1151 23 38.33% 100.00% # Bytes accessed per row activation 206system.physmem.bytesPerActivate::total 60 # Bytes accessed per row activation 207system.physmem.totQLat 17284989 # Total ticks spent queuing 208system.physmem.totMemAccLat 31028739 # Total ticks spent from burst creation until serviced by the DRAM 209system.physmem.totBusLat 3665000 # Total ticks spent in databus transfers 210system.physmem.avgQLat 23581.16 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 211system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 26231.11 # Average memory access latency per DRAM burst 208system.physmem.avgRdBW 1566.17 # Average DRAM read bandwidth in MiByte/s | 212system.physmem.avgMemAccLat 42331.16 # Average memory access latency per DRAM burst 213system.physmem.avgRdBW 3955.65 # Average DRAM read bandwidth in MiByte/s |
| 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 214system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 210system.physmem.avgRdBWSys 1566.17 # Average system read bandwidth in MiByte/s | 215system.physmem.avgRdBWSys 3955.65 # Average system read bandwidth in MiByte/s |
| 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 216system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 217system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 213system.physmem.busUtil 12.24 # Data bus utilization in percentage 214system.physmem.busUtilRead 12.24 # Data bus utilization in percentage for reads | 218system.physmem.busUtil 30.90 # Data bus utilization in percentage 219system.physmem.busUtilRead 30.90 # Data bus utilization in percentage for reads |
| 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 220system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 216system.physmem.avgRdQLen 1.84 # Average read queue length when enqueuing | 221system.physmem.avgRdQLen 5.25 # Average read queue length when enqueuing |
| 217system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 222system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 218system.physmem.readRowHits 331 # Number of row buffer hits during reads | 223system.physmem.readRowHits 662 # Number of row buffer hits during reads |
| 219system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 224system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 220system.physmem.readRowHitRate 83.38 # Row buffer hit rate for reads | 225system.physmem.readRowHitRate 90.31 # Row buffer hit rate for reads |
| 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 226system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 222system.physmem.avgGap 40695.21 # Average gap between requests 223system.physmem.pageHitRate 83.38 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states | 227system.physmem.avgGap 16161.66 # Average gap between requests 228system.physmem.pageHitRate 90.31 # Row buffer hit rate, read and write combined 229system.physmem.memoryStateTime::IDLE 6500 # Time in different power states 230system.physmem.memoryStateTime::REF 260000 # Time in different power states |
| 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states | 231system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states | 232system.physmem.memoryStateTime::ACT 7800750 # Time in different power states |
| 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 233system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 229system.membus.throughput 1566171485 # Throughput (bytes/s) 230system.membus.trans_dist::ReadReq 355 # Transaction distribution 231system.membus.trans_dist::ReadResp 355 # Transaction distribution 232system.membus.trans_dist::ReadExReq 42 # Transaction distribution 233system.membus.trans_dist::ReadExResp 42 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 25408 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 240system.membus.reqLayer0.occupancy 494500 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 3.0 # Layer utilization (%) 242system.membus.respLayer1.occupancy 3699500 # Layer occupancy (ticks) 243system.membus.respLayer1.utilization 22.8 # Layer utilization (%) | 234system.membus.trans_dist::ReadReq 704 # Transaction distribution 235system.membus.trans_dist::ReadResp 702 # Transaction distribution 236system.membus.trans_dist::ReadExReq 29 # Transaction distribution 237system.membus.trans_dist::ReadExResp 29 # Transaction distribution 238system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1464 # Packet count per connected master and slave (bytes) 239system.membus.pkt_count::total 1464 # Packet count per connected master and slave (bytes) 240system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 46784 # Cumulative packet size per connected master and slave (bytes) 241system.membus.pkt_size::total 46784 # Cumulative packet size per connected master and slave (bytes) 242system.membus.snoops 0 # Total snoops (count) 243system.membus.snoop_fanout::samples 733 # Request fanout histogram 244system.membus.snoop_fanout::mean 0 # Request fanout histogram 245system.membus.snoop_fanout::stdev 0 # Request fanout histogram 246system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 247system.membus.snoop_fanout::0 733 100.00% 100.00% # Request fanout histogram 248system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 249system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 250system.membus.snoop_fanout::min_value 0 # Request fanout histogram 251system.membus.snoop_fanout::max_value 0 # Request fanout histogram 252system.membus.snoop_fanout::total 733 # Request fanout histogram 253system.membus.reqLayer0.occupancy 803724 # Layer occupancy (ticks) 254system.membus.reqLayer0.utilization 6.8 # Layer utilization (%) 255system.membus.respLayer1.occupancy 6629985 # Layer occupancy (ticks) 256system.membus.respLayer1.utilization 55.9 # Layer utilization (%) |
| 244system.cpu_clk_domain.clock 500 # Clock period in ticks | 257system.cpu_clk_domain.clock 500 # Clock period in ticks |
| 245system.cpu.branchPred.lookups 2638 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1635 # Number of conditional branches predicted 247system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect 248system.cpu.branchPred.BTBLookups 2101 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 783 # Number of BTB hits | 258system.cpu.branchPred.lookups 2560 # Number of BP lookups 259system.cpu.branchPred.condPredicted 1531 # Number of conditional branches predicted 260system.cpu.branchPred.condIncorrect 510 # Number of conditional branches incorrect 261system.cpu.branchPred.BTBLookups 939 # Number of BTB lookups 262system.cpu.branchPred.BTBHits 497 # Number of BTB hits |
| 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 263system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 251system.cpu.branchPred.BTBHitPct 37.267968 # BTB Hit Percentage 252system.cpu.branchPred.usedRAS 354 # Number of times the RAS was used to get a target. 253system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. | 264system.cpu.branchPred.BTBHitPct 52.928647 # BTB Hit Percentage 265system.cpu.branchPred.usedRAS 297 # Number of times the RAS was used to get a target. 266system.cpu.branchPred.RASInCorrect 56 # Number of incorrect RAS predictions. |
| 254system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 255system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 256system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 257system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 258system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 259system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 260system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 261system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 331system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 332system.cpu.itb.read_accesses 0 # DTB read accesses 333system.cpu.itb.write_accesses 0 # DTB write accesses 334system.cpu.itb.inst_accesses 0 # ITB inst accesses 335system.cpu.itb.hits 0 # DTB hits 336system.cpu.itb.misses 0 # DTB misses 337system.cpu.itb.accesses 0 # DTB accesses 338system.cpu.workload.num_syscalls 13 # Number of system calls | 267system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 268system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 269system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 270system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 271system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 272system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 273system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 274system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 69 unchanged lines hidden (view full) --- 344system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions 345system.cpu.itb.read_accesses 0 # DTB read accesses 346system.cpu.itb.write_accesses 0 # DTB write accesses 347system.cpu.itb.inst_accesses 0 # ITB inst accesses 348system.cpu.itb.hits 0 # DTB hits 349system.cpu.itb.misses 0 # DTB misses 350system.cpu.itb.accesses 0 # DTB accesses 351system.cpu.workload.num_syscalls 13 # Number of system calls |
| 339system.cpu.numCycles 32447 # number of cpu cycles simulated | 352system.cpu.numCycles 23720 # number of cpu cycles simulated |
| 340system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 341system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 353system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 354system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 342system.cpu.fetch.icacheStallCycles 7786 # Number of cycles fetch is stalled on an Icache miss 343system.cpu.fetch.Insts 12484 # Number of instructions fetch has processed 344system.cpu.fetch.Branches 2638 # Number of branches that fetch encountered 345system.cpu.fetch.predictedBranches 1137 # Number of branches that fetch has predicted taken 346system.cpu.fetch.Cycles 4850 # Number of cycles fetch has run and was not squashing or blocked 347system.cpu.fetch.SquashCycles 1010 # Number of cycles fetch has spent squashing 348system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 349system.cpu.fetch.PendingTrapStallCycles 259 # Number of stall cycles due to pending traps 350system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR 351system.cpu.fetch.CacheLines 2068 # Number of cache lines fetched 352system.cpu.fetch.IcacheSquashes 320 # Number of outstanding Icache misses that were squashed 353system.cpu.fetch.rateDist::samples 13433 # Number of instructions fetched each cycle (Total) 354system.cpu.fetch.rateDist::mean 1.098935 # Number of instructions fetched each cycle (Total) 355system.cpu.fetch.rateDist::stdev 2.478489 # Number of instructions fetched each cycle (Total) | 355system.cpu.fetch.icacheStallCycles 4394 # Number of cycles fetch is stalled on an Icache miss 356system.cpu.fetch.Insts 12370 # Number of instructions fetch has processed 357system.cpu.fetch.Branches 2560 # Number of branches that fetch encountered 358system.cpu.fetch.predictedBranches 794 # Number of branches that fetch has predicted taken 359system.cpu.fetch.Cycles 11397 # Number of cycles fetch has run and was not squashing or blocked 360system.cpu.fetch.SquashCycles 1062 # Number of cycles fetch has spent squashing 361system.cpu.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 362system.cpu.fetch.PendingTrapStallCycles 322 # Number of stall cycles due to pending traps 363system.cpu.fetch.IcacheWaitRetryStallCycles 84 # Number of stall cycles due to full MSHR 364system.cpu.fetch.CacheLines 4117 # Number of cache lines fetched 365system.cpu.fetch.IcacheSquashes 139 # Number of outstanding Icache misses that were squashed 366system.cpu.fetch.rateDist::samples 16747 # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::mean 0.858243 # Number of instructions fetched each cycle (Total) 368system.cpu.fetch.rateDist::stdev 1.204203 # Number of instructions fetched each cycle (Total) |
| 356system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 369system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 357system.cpu.fetch.rateDist::0 10743 79.97% 79.97% # Number of instructions fetched each cycle (Total) 358system.cpu.fetch.rateDist::1 265 1.97% 81.95% # Number of instructions fetched each cycle (Total) 359system.cpu.fetch.rateDist::2 241 1.79% 83.74% # Number of instructions fetched each cycle (Total) 360system.cpu.fetch.rateDist::3 235 1.75% 85.49% # Number of instructions fetched each cycle (Total) 361system.cpu.fetch.rateDist::4 238 1.77% 87.26% # Number of instructions fetched each cycle (Total) 362system.cpu.fetch.rateDist::5 291 2.17% 89.43% # Number of instructions fetched each cycle (Total) 363system.cpu.fetch.rateDist::6 141 1.05% 90.48% # Number of instructions fetched each cycle (Total) 364system.cpu.fetch.rateDist::7 175 1.30% 91.78% # Number of instructions fetched each cycle (Total) 365system.cpu.fetch.rateDist::8 1104 8.22% 100.00% # Number of instructions fetched each cycle (Total) | 370system.cpu.fetch.rateDist::0 9977 59.57% 59.57% # Number of instructions fetched each cycle (Total) 371system.cpu.fetch.rateDist::1 2687 16.04% 75.62% # Number of instructions fetched each cycle (Total) 372system.cpu.fetch.rateDist::2 563 3.36% 78.98% # Number of instructions fetched each cycle (Total) 373system.cpu.fetch.rateDist::3 3520 21.02% 100.00% # Number of instructions fetched each cycle (Total) |
| 366system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 367system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) | 374system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 375system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| 368system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 369system.cpu.fetch.rateDist::total 13433 # Number of instructions fetched each cycle (Total) 370system.cpu.fetch.branchRate 0.081302 # Number of branch fetches per cycle 371system.cpu.fetch.rate 0.384751 # Number of inst fetches per cycle 372system.cpu.decode.IdleCycles 6529 # Number of cycles decode is idle 373system.cpu.decode.BlockedCycles 4272 # Number of cycles decode is blocked 374system.cpu.decode.RunCycles 2145 # Number of cycles decode is running 375system.cpu.decode.UnblockCycles 138 # Number of cycles decode is unblocking 376system.cpu.decode.SquashCycles 349 # Number of cycles decode is squashing 377system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch 378system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction 379system.cpu.decode.DecodedInsts 12118 # Number of instructions handled by decode 380system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode 381system.cpu.rename.SquashCycles 349 # Number of cycles rename is squashing 382system.cpu.rename.IdleCycles 6736 # Number of cycles rename is idle 383system.cpu.rename.BlockCycles 846 # Number of cycles rename is blocking 384system.cpu.rename.serializeStallCycles 2304 # count of cycles rename stalled for serializing inst 385system.cpu.rename.RunCycles 2064 # Number of cycles rename is running 386system.cpu.rename.UnblockCycles 1134 # Number of cycles rename is unblocking 387system.cpu.rename.RenamedInsts 11483 # Number of instructions processed by rename 388system.cpu.rename.IQFullEvents 163 # Number of times rename has blocked due to IQ full 389system.cpu.rename.LQFullEvents 117 # Number of times rename has blocked due to LQ full 390system.cpu.rename.SQFullEvents 963 # Number of times rename has blocked due to SQ full 391system.cpu.rename.RenamedOperands 11820 # Number of destination operands rename has renamed 392system.cpu.rename.RenameLookups 52846 # Number of register rename lookups that rename has made 393system.cpu.rename.int_rename_lookups 12757 # Number of integer rename lookups 394system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups | 376system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) 377system.cpu.fetch.rateDist::total 16747 # Number of instructions fetched each cycle (Total) 378system.cpu.fetch.branchRate 0.107926 # Number of branch fetches per cycle 379system.cpu.fetch.rate 0.521501 # Number of inst fetches per cycle 380system.cpu.decode.IdleCycles 4535 # Number of cycles decode is idle 381system.cpu.decode.BlockedCycles 6577 # Number of cycles decode is blocked 382system.cpu.decode.RunCycles 5106 # Number of cycles decode is running 383system.cpu.decode.UnblockCycles 160 # Number of cycles decode is unblocking 384system.cpu.decode.SquashCycles 369 # Number of cycles decode is squashing 385system.cpu.decode.BranchResolved 338 # Number of times decode resolved a branch 386system.cpu.decode.BranchMispred 165 # Number of times decode detected a branch misprediction 387system.cpu.decode.DecodedInsts 10143 # Number of instructions handled by decode 388system.cpu.decode.SquashedInsts 1684 # Number of squashed instructions handled by decode 389system.cpu.rename.SquashCycles 369 # Number of cycles rename is squashing 390system.cpu.rename.IdleCycles 5681 # Number of cycles rename is idle 391system.cpu.rename.BlockCycles 3207 # Number of cycles rename is blocking 392system.cpu.rename.serializeStallCycles 2422 # count of cycles rename stalled for serializing inst 393system.cpu.rename.RunCycles 4105 # Number of cycles rename is running 394system.cpu.rename.UnblockCycles 963 # Number of cycles rename is unblocking 395system.cpu.rename.RenamedInsts 9048 # Number of instructions processed by rename 396system.cpu.rename.SquashedInsts 426 # Number of squashed instructions processed by rename 397system.cpu.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full 398system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full 399system.cpu.rename.LQFullEvents 101 # Number of times rename has blocked due to LQ full 400system.cpu.rename.SQFullEvents 748 # Number of times rename has blocked due to SQ full 401system.cpu.rename.RenamedOperands 9432 # Number of destination operands rename has renamed 402system.cpu.rename.RenameLookups 41033 # Number of register rename lookups that rename has made 403system.cpu.rename.int_rename_lookups 9977 # Number of integer rename lookups 404system.cpu.rename.fp_rename_lookups 18 # Number of floating rename lookups |
| 395system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed | 405system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed |
| 396system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing 397system.cpu.rename.serializingInsts 43 # count of serializing insts renamed 398system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed 399system.cpu.rename.skidInsts 443 # count of insts added to the skid buffer 400system.cpu.memDep0.insertedLoads 2313 # Number of loads inserted to the mem dependence unit. 401system.cpu.memDep0.insertedStores 1639 # Number of stores inserted to the mem dependence unit. 402system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. 403system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. 404system.cpu.iq.iqInstsAdded 10354 # Number of instructions added to the IQ (excludes non-spec) 405system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ 406system.cpu.iq.iqInstsIssued 8358 # Number of instructions issued 407system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued 408system.cpu.iq.iqSquashedInstsExamined 4760 # Number of squashed instructions iterated over during squash; mainly for profiling 409system.cpu.iq.iqSquashedOperandsExamined 12835 # Number of squashed operands that are examined and possibly removed from graph 410system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed 411system.cpu.iq.issued_per_cycle::samples 13433 # Number of insts issued each cycle 412system.cpu.iq.issued_per_cycle::mean 0.622199 # Number of insts issued each cycle 413system.cpu.iq.issued_per_cycle::stdev 1.376807 # Number of insts issued each cycle | 406system.cpu.rename.UndoneMaps 3938 # Number of HB maps that are undone due to squashing 407system.cpu.rename.serializingInsts 31 # count of serializing insts renamed 408system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed 409system.cpu.rename.skidInsts 472 # count of insts added to the skid buffer 410system.cpu.memDep0.insertedLoads 1824 # Number of loads inserted to the mem dependence unit. 411system.cpu.memDep0.insertedStores 1295 # Number of stores inserted to the mem dependence unit. 412system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 413system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. 414system.cpu.iq.iqInstsAdded 8517 # Number of instructions added to the IQ (excludes non-spec) 415system.cpu.iq.iqNonSpecInstsAdded 40 # Number of non-speculative instructions added to the IQ 416system.cpu.iq.iqInstsIssued 7242 # Number of instructions issued 417system.cpu.iq.iqSquashedInstsIssued 203 # Number of squashed instructions issued 418system.cpu.iq.iqSquashedInstsExamined 2981 # Number of squashed instructions iterated over during squash; mainly for profiling 419system.cpu.iq.iqSquashedOperandsExamined 8241 # Number of squashed operands that are examined and possibly removed from graph 420system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 421system.cpu.iq.issued_per_cycle::samples 16747 # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::mean 0.432436 # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::stdev 0.833231 # Number of insts issued each cycle |
| 414system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 424system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 415system.cpu.iq.issued_per_cycle::0 10179 75.78% 75.78% # Number of insts issued each cycle 416system.cpu.iq.issued_per_cycle::1 1183 8.81% 84.58% # Number of insts issued each cycle 417system.cpu.iq.issued_per_cycle::2 748 5.57% 90.15% # Number of insts issued each cycle 418system.cpu.iq.issued_per_cycle::3 453 3.37% 93.52% # Number of insts issued each cycle 419system.cpu.iq.issued_per_cycle::4 362 2.69% 96.22% # Number of insts issued each cycle 420system.cpu.iq.issued_per_cycle::5 286 2.13% 98.35% # Number of insts issued each cycle 421system.cpu.iq.issued_per_cycle::6 135 1.00% 99.35% # Number of insts issued each cycle 422system.cpu.iq.issued_per_cycle::7 64 0.48% 99.83% # Number of insts issued each cycle 423system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle | 425system.cpu.iq.issued_per_cycle::0 12501 74.65% 74.65% # Number of insts issued each cycle 426system.cpu.iq.issued_per_cycle::1 1960 11.70% 86.35% # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::2 1628 9.72% 96.07% # Number of insts issued each cycle 428system.cpu.iq.issued_per_cycle::3 606 3.62% 99.69% # Number of insts issued each cycle 429system.cpu.iq.issued_per_cycle::4 52 0.31% 100.00% # Number of insts issued each cycle 430system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle 431system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle 432system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle 433system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle |
| 424system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 425system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle | 434system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 435system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| 426system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 427system.cpu.iq.issued_per_cycle::total 13433 # Number of insts issued each cycle | 436system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle 437system.cpu.iq.issued_per_cycle::total 16747 # Number of insts issued each cycle |
| 428system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 438system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 429system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available 430system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available 431system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available 432system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available 433system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available 434system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available 435system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available 436system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available 437system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 438system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available 439system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available 440system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available 441system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available 442system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available 443system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available 444system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available 445system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available 446system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available 447system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available 458system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available 459system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available | 439system.cpu.iq.fu_full::IntAlu 437 29.61% 29.61% # attempts to use FU when none available 440system.cpu.iq.fu_full::IntMult 0 0.00% 29.61% # attempts to use FU when none available 441system.cpu.iq.fu_full::IntDiv 0 0.00% 29.61% # attempts to use FU when none available 442system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.61% # attempts to use FU when none available 443system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.61% # attempts to use FU when none available 444system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.61% # attempts to use FU when none available 445system.cpu.iq.fu_full::FloatMult 0 0.00% 29.61% # attempts to use FU when none available 446system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.61% # attempts to use FU when none available 447system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 448system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.61% # attempts to use FU when none available 449system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.61% # attempts to use FU when none available 450system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.61% # attempts to use FU when none available 451system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.61% # attempts to use FU when none available 452system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.61% # attempts to use FU when none available 453system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.61% # attempts to use FU when none available 454system.cpu.iq.fu_full::SimdMult 0 0.00% 29.61% # attempts to use FU when none available 455system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.61% # attempts to use FU when none available 456system.cpu.iq.fu_full::SimdShift 0 0.00% 29.61% # attempts to use FU when none available 457system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.61% # attempts to use FU when none available 458system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.61% # attempts to use FU when none available 459system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.61% # attempts to use FU when none available 460system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.61% # attempts to use FU when none available 461system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.61% # attempts to use FU when none available 462system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.61% # attempts to use FU when none available 463system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.61% # attempts to use FU when none available 464system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.61% # attempts to use FU when none available 465system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.61% # attempts to use FU when none available 466system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.61% # attempts to use FU when none available 467system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.61% # attempts to use FU when none available 468system.cpu.iq.fu_full::MemRead 482 32.66% 62.26% # attempts to use FU when none available 469system.cpu.iq.fu_full::MemWrite 557 37.74% 100.00% # attempts to use FU when none available |
| 460system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 461system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 462system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 470system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 471system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 472system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 463system.cpu.iq.FU_type_0::IntAlu 5041 60.31% 60.31% # Type of FU issued 464system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.39% # Type of FU issued 465system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.39% # Type of FU issued 466system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.39% # Type of FU issued 467system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.39% # Type of FU issued 468system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.39% # Type of FU issued 469system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.39% # Type of FU issued 470system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.39% # Type of FU issued 471system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.39% # Type of FU issued 472system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.39% # Type of FU issued 473system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.39% # Type of FU issued 474system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.39% # Type of FU issued 475system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.39% # Type of FU issued 476system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.39% # Type of FU issued 477system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.39% # Type of FU issued 478system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.39% # Type of FU issued 479system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.39% # Type of FU issued 480system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.39% # Type of FU issued 481system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.39% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.39% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.39% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.39% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.39% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.39% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.39% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued 492system.cpu.iq.FU_type_0::MemRead 2009 24.04% 84.46% # Type of FU issued 493system.cpu.iq.FU_type_0::MemWrite 1299 15.54% 100.00% # Type of FU issued | 473system.cpu.iq.FU_type_0::IntAlu 4533 62.59% 62.59% # Type of FU issued 474system.cpu.iq.FU_type_0::IntMult 6 0.08% 62.68% # Type of FU issued 475system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.68% # Type of FU issued 476system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.68% # Type of FU issued 477system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.68% # Type of FU issued 478system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.68% # Type of FU issued 479system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.68% # Type of FU issued 480system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.68% # Type of FU issued 481system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.68% # Type of FU issued 482system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.68% # Type of FU issued 483system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.68% # Type of FU issued 484system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.68% # Type of FU issued 485system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.68% # Type of FU issued 486system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.68% # Type of FU issued 487system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.68% # Type of FU issued 488system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.68% # Type of FU issued 489system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.68% # Type of FU issued 490system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.68% # Type of FU issued 491system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.68% # Type of FU issued 492system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.68% # Type of FU issued 493system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.68% # Type of FU issued 494system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.68% # Type of FU issued 495system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.68% # Type of FU issued 496system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.68% # Type of FU issued 497system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.68% # Type of FU issued 498system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.72% # Type of FU issued 499system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued 500system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued 501system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued 502system.cpu.iq.FU_type_0::MemRead 1613 22.27% 84.99% # Type of FU issued 503system.cpu.iq.FU_type_0::MemWrite 1087 15.01% 100.00% # Type of FU issued |
| 494system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 495system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 504system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 505system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 496system.cpu.iq.FU_type_0::total 8358 # Type of FU issued 497system.cpu.iq.rate 0.257589 # Inst issue rate 498system.cpu.iq.fu_busy_cnt 169 # FU busy when requested 499system.cpu.iq.fu_busy_rate 0.020220 # FU busy rate (busy events/executed inst) 500system.cpu.iq.int_inst_queue_reads 30275 # Number of integer instruction queue reads 501system.cpu.iq.int_inst_queue_writes 15052 # Number of integer instruction queue writes 502system.cpu.iq.int_inst_queue_wakeup_accesses 7570 # Number of integer instruction queue wakeup accesses 503system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads 504system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes 505system.cpu.iq.fp_inst_queue_wakeup_accesses 31 # Number of floating instruction queue wakeup accesses 506system.cpu.iq.int_alu_accesses 8484 # Number of integer alu accesses 507system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses 508system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores | 506system.cpu.iq.FU_type_0::total 7242 # Type of FU issued 507system.cpu.iq.rate 0.305312 # Inst issue rate 508system.cpu.iq.fu_busy_cnt 1476 # FU busy when requested 509system.cpu.iq.fu_busy_rate 0.203811 # FU busy rate (busy events/executed inst) 510system.cpu.iq.int_inst_queue_reads 32865 # Number of integer instruction queue reads 511system.cpu.iq.int_inst_queue_writes 11527 # Number of integer instruction queue writes 512system.cpu.iq.int_inst_queue_wakeup_accesses 6638 # Number of integer instruction queue wakeup accesses 513system.cpu.iq.fp_inst_queue_reads 45 # Number of floating instruction queue reads 514system.cpu.iq.fp_inst_queue_writes 18 # Number of floating instruction queue writes 515system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses 516system.cpu.iq.int_alu_accesses 8689 # Number of integer alu accesses 517system.cpu.iq.fp_alu_accesses 29 # Number of floating point alu accesses 518system.cpu.iew.lsq.thread0.forwLoads 15 # Number of loads that had data forwarded from stores |
| 509system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 519system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 510system.cpu.iew.lsq.thread0.squashedLoads 1286 # Number of loads squashed 511system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed 512system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations 513system.cpu.iew.lsq.thread0.squashedStores 701 # Number of stores squashed | 520system.cpu.iew.lsq.thread0.squashedLoads 797 # Number of loads squashed 521system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed 522system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 523system.cpu.iew.lsq.thread0.squashedStores 357 # Number of stores squashed |
| 514system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 515system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding | 524system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 525system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| 516system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled 517system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked | 526system.cpu.iew.lsq.thread0.rescheduledLoads 7 # Number of loads that were rescheduled 527system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked |
| 518system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 528system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 519system.cpu.iew.iewSquashCycles 349 # Number of cycles IEW is squashing 520system.cpu.iew.iewBlockCycles 800 # Number of cycles IEW is blocking 521system.cpu.iew.iewUnblockCycles 25 # Number of cycles IEW is unblocking 522system.cpu.iew.iewDispatchedInsts 10411 # Number of instructions dispatched to IQ 523system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch 524system.cpu.iew.iewDispLoadInsts 2313 # Number of dispatched load instructions 525system.cpu.iew.iewDispStoreInsts 1639 # Number of dispatched store instructions 526system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions 527system.cpu.iew.iewIQFullEvents 13 # Number of times the IQ has become full, causing a stall 528system.cpu.iew.iewLSQFullEvents 10 # Number of times the LSQ has become full, causing a stall 529system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations 530system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly 531system.cpu.iew.predictedNotTakenIncorrect 252 # Number of branches that were predicted not taken incorrectly 532system.cpu.iew.branchMispredicts 364 # Number of branch mispredicts detected at execute 533system.cpu.iew.iewExecutedInsts 8063 # Number of executed instructions 534system.cpu.iew.iewExecLoadInsts 1908 # Number of load instructions executed 535system.cpu.iew.iewExecSquashedInsts 295 # Number of squashed instructions skipped in execute | 529system.cpu.iew.iewSquashCycles 369 # Number of cycles IEW is squashing 530system.cpu.iew.iewBlockCycles 705 # Number of cycles IEW is blocking 531system.cpu.iew.iewUnblockCycles 159 # Number of cycles IEW is unblocking 532system.cpu.iew.iewDispatchedInsts 8571 # Number of instructions dispatched to IQ 533system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch 534system.cpu.iew.iewDispLoadInsts 1824 # Number of dispatched load instructions 535system.cpu.iew.iewDispStoreInsts 1295 # Number of dispatched store instructions 536system.cpu.iew.iewDispNonSpecInsts 28 # Number of dispatched non-speculative instructions 537system.cpu.iew.iewIQFullEvents 6 # Number of times the IQ has become full, causing a stall 538system.cpu.iew.iewLSQFullEvents 151 # Number of times the LSQ has become full, causing a stall 539system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 540system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly 541system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly 542system.cpu.iew.branchMispredicts 362 # Number of branch mispredicts detected at execute 543system.cpu.iew.iewExecutedInsts 6828 # Number of executed instructions 544system.cpu.iew.iewExecLoadInsts 1428 # Number of load instructions executed 545system.cpu.iew.iewExecSquashedInsts 414 # Number of squashed instructions skipped in execute |
| 536system.cpu.iew.exec_swp 0 # number of swp insts executed | 546system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 537system.cpu.iew.exec_nop 11 # number of nop insts executed 538system.cpu.iew.exec_refs 3148 # number of memory reference insts executed 539system.cpu.iew.exec_branches 1457 # Number of branches executed 540system.cpu.iew.exec_stores 1240 # Number of stores executed 541system.cpu.iew.exec_rate 0.248498 # Inst execution rate 542system.cpu.iew.wb_sent 7735 # cumulative count of insts sent to commit 543system.cpu.iew.wb_count 7601 # cumulative count of insts written-back 544system.cpu.iew.wb_producers 3572 # num instructions producing a value 545system.cpu.iew.wb_consumers 6998 # num instructions consuming a value | 547system.cpu.iew.exec_nop 14 # number of nop insts executed 548system.cpu.iew.exec_refs 2449 # number of memory reference insts executed 549system.cpu.iew.exec_branches 1283 # Number of branches executed 550system.cpu.iew.exec_stores 1021 # Number of stores executed 551system.cpu.iew.exec_rate 0.287858 # Inst execution rate 552system.cpu.iew.wb_sent 6699 # cumulative count of insts sent to commit 553system.cpu.iew.wb_count 6654 # cumulative count of insts written-back 554system.cpu.iew.wb_producers 3045 # num instructions producing a value 555system.cpu.iew.wb_consumers 5519 # num instructions consuming a value |
| 546system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 556system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 547system.cpu.iew.wb_rate 0.234259 # insts written-back per cycle 548system.cpu.iew.wb_fanout 0.510432 # average fanout of values written-back | 557system.cpu.iew.wb_rate 0.280523 # insts written-back per cycle 558system.cpu.iew.wb_fanout 0.551730 # average fanout of values written-back |
| 549system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 559system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 550system.cpu.commit.commitSquashedInsts 5037 # The number of squashed insts skipped by commit | 560system.cpu.commit.commitSquashedInsts 2714 # The number of squashed insts skipped by commit |
| 551system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards | 561system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards |
| 552system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted 553system.cpu.commit.committed_per_cycle::samples 12552 # Number of insts commited each cycle 554system.cpu.commit.committed_per_cycle::mean 0.428378 # Number of insts commited each cycle 555system.cpu.commit.committed_per_cycle::stdev 1.273949 # Number of insts commited each cycle | 562system.cpu.commit.branchMispredicts 348 # The number of times a branch was mispredicted 563system.cpu.commit.committed_per_cycle::samples 16184 # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::mean 0.332242 # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::stdev 0.986798 # Number of insts commited each cycle |
| 556system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 566system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 557system.cpu.commit.committed_per_cycle::0 10495 83.61% 83.61% # Number of insts commited each cycle 558system.cpu.commit.committed_per_cycle::1 893 7.11% 90.73% # Number of insts commited each cycle 559system.cpu.commit.committed_per_cycle::2 426 3.39% 94.12% # Number of insts commited each cycle 560system.cpu.commit.committed_per_cycle::3 211 1.68% 95.80% # Number of insts commited each cycle 561system.cpu.commit.committed_per_cycle::4 111 0.88% 96.69% # Number of insts commited each cycle 562system.cpu.commit.committed_per_cycle::5 212 1.69% 98.37% # Number of insts commited each cycle 563system.cpu.commit.committed_per_cycle::6 50 0.40% 98.77% # Number of insts commited each cycle 564system.cpu.commit.committed_per_cycle::7 37 0.29% 99.07% # Number of insts commited each cycle 565system.cpu.commit.committed_per_cycle::8 117 0.93% 100.00% # Number of insts commited each cycle | 567system.cpu.commit.committed_per_cycle::0 13581 83.92% 83.92% # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::1 1345 8.31% 92.23% # Number of insts commited each cycle 569system.cpu.commit.committed_per_cycle::2 599 3.70% 95.93% # Number of insts commited each cycle 570system.cpu.commit.committed_per_cycle::3 281 1.74% 97.66% # Number of insts commited each cycle 571system.cpu.commit.committed_per_cycle::4 168 1.04% 98.70% # Number of insts commited each cycle 572system.cpu.commit.committed_per_cycle::5 78 0.48% 99.18% # Number of insts commited each cycle 573system.cpu.commit.committed_per_cycle::6 47 0.29% 99.47% # Number of insts commited each cycle 574system.cpu.commit.committed_per_cycle::7 33 0.20% 99.68% # Number of insts commited each cycle 575system.cpu.commit.committed_per_cycle::8 52 0.32% 100.00% # Number of insts commited each cycle |
| 566system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 567system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 568system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 576system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 577system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 578system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 569system.cpu.commit.committed_per_cycle::total 12552 # Number of insts commited each cycle | 579system.cpu.commit.committed_per_cycle::total 16184 # Number of insts commited each cycle |
| 570system.cpu.commit.committedInsts 4591 # Number of instructions committed 571system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 572system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 573system.cpu.commit.refs 1965 # Number of memory references committed 574system.cpu.commit.loads 1027 # Number of loads committed 575system.cpu.commit.membars 12 # Number of memory barriers committed 576system.cpu.commit.branches 1007 # Number of branches committed 577system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 607system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 608system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 609system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 610system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 611system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 612system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 613system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 614system.cpu.commit.op_class_0::total 5377 # Class of committed instruction | 580system.cpu.commit.committedInsts 4591 # Number of instructions committed 581system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed 582system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 583system.cpu.commit.refs 1965 # Number of memory references committed 584system.cpu.commit.loads 1027 # Number of loads committed 585system.cpu.commit.membars 12 # Number of memory barriers committed 586system.cpu.commit.branches 1007 # Number of branches committed 587system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 617system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction 618system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction 619system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% # Class of committed instruction 620system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Class of committed instruction 621system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction 622system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 623system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 624system.cpu.commit.op_class_0::total 5377 # Class of committed instruction |
| 615system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached | 625system.cpu.commit.bw_lim_events 52 # number cycles where commit BW limit reached |
| 616system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 626system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 617system.cpu.rob.rob_reads 22692 # The number of ROB reads 618system.cpu.rob.rob_writes 21719 # The number of ROB writes 619system.cpu.timesIdled 209 # Number of times that the entire CPU went into an idle state and unscheduled itself 620system.cpu.idleCycles 19014 # Total number of cycles that the CPU has spent unscheduled due to idling | 627system.cpu.rob.rob_reads 24066 # The number of ROB reads 628system.cpu.rob.rob_writes 16749 # The number of ROB writes 629system.cpu.timesIdled 138 # Number of times that the entire CPU went into an idle state and unscheduled itself 630system.cpu.idleCycles 6973 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 621system.cpu.committedInsts 4591 # Number of Instructions Simulated 622system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated | 631system.cpu.committedInsts 4591 # Number of Instructions Simulated 632system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated |
| 623system.cpu.cpi 7.067523 # CPI: Cycles Per Instruction 624system.cpu.cpi_total 7.067523 # CPI: Total CPI of All Threads 625system.cpu.ipc 0.141492 # IPC: Instructions Per Cycle 626system.cpu.ipc_total 0.141492 # IPC: Total IPC of All Threads 627system.cpu.int_regfile_reads 7944 # number of integer regfile reads 628system.cpu.int_regfile_writes 4420 # number of integer regfile writes 629system.cpu.fp_regfile_reads 31 # number of floating regfile reads 630system.cpu.cc_regfile_reads 28734 # number of cc regfile reads 631system.cpu.cc_regfile_writes 3302 # number of cc regfile writes 632system.cpu.misc_regfile_reads 3189 # number of misc regfile reads | 633system.cpu.cpi 5.166630 # CPI: Cycles Per Instruction 634system.cpu.cpi_total 5.166630 # CPI: Total CPI of All Threads 635system.cpu.ipc 0.193550 # IPC: Instructions Per Cycle 636system.cpu.ipc_total 0.193550 # IPC: Total IPC of All Threads 637system.cpu.int_regfile_reads 6786 # number of integer regfile reads 638system.cpu.int_regfile_writes 3839 # number of integer regfile writes 639system.cpu.fp_regfile_reads 16 # number of floating regfile reads 640system.cpu.cc_regfile_reads 24301 # number of cc regfile reads 641system.cpu.cc_regfile_writes 2919 # number of cc regfile writes 642system.cpu.misc_regfile_reads 2642 # number of misc regfile reads |
| 633system.cpu.misc_regfile_writes 24 # number of misc regfile writes | 643system.cpu.misc_regfile_writes 24 # number of misc regfile writes |
| 634system.cpu.toL2Bus.throughput 1735807187 # Throughput (bytes/s) 635system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution 636system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution 637system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution 638system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution 639system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) 640system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) 641system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) 642system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) 643system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) 644system.cpu.toL2Bus.tot_pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) 645system.cpu.toL2Bus.data_through_bus 28160 # Total data (bytes) 646system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 647system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 648system.cpu.toL2Bus.reqLayer0.utilization 1.4 # Layer utilization (%) 649system.cpu.toL2Bus.respLayer0.occupancy 488250 # Layer occupancy (ticks) 650system.cpu.toL2Bus.respLayer0.utilization 3.0 # Layer utilization (%) 651system.cpu.toL2Bus.respLayer1.occupancy 228495 # Layer occupancy (ticks) 652system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) 653system.cpu.icache.tags.replacements 1 # number of replacements 654system.cpu.icache.tags.tagsinuse 150.758993 # Cycle average of tags in use 655system.cpu.icache.tags.total_refs 1666 # Total number of references to valid blocks. 656system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. 657system.cpu.icache.tags.avg_refs 5.666667 # Average number of references to valid blocks. | 644system.cpu.toL2Bus.trans_dist::ReadReq 408 # Transaction distribution 645system.cpu.toL2Bus.trans_dist::ReadResp 407 # Transaction distribution 646system.cpu.toL2Bus.trans_dist::HardPFReq 1026 # Transaction distribution 647system.cpu.toL2Bus.trans_dist::ReadExReq 40 # Transaction distribution 648system.cpu.toL2Bus.trans_dist::ReadExResp 40 # Transaction distribution 649system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 608 # Packet count per connected master and slave (bytes) 650system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 287 # Packet count per connected master and slave (bytes) 651system.cpu.toL2Bus.pkt_count::total 895 # Packet count per connected master and slave (bytes) 652system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19456 # Cumulative packet size per connected master and slave (bytes) 653system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9152 # Cumulative packet size per connected master and slave (bytes) 654system.cpu.toL2Bus.pkt_size::total 28608 # Cumulative packet size per connected master and slave (bytes) 655system.cpu.toL2Bus.snoops 1026 # Total snoops (count) 656system.cpu.toL2Bus.snoop_fanout::samples 1474 # Request fanout histogram 657system.cpu.toL2Bus.snoop_fanout::mean 5.696065 # Request fanout histogram 658system.cpu.toL2Bus.snoop_fanout::stdev 0.460111 # Request fanout histogram 659system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 660system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 661system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram 662system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram 663system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram 664system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram 665system.cpu.toL2Bus.snoop_fanout::5 448 30.39% 30.39% # Request fanout histogram 666system.cpu.toL2Bus.snoop_fanout::6 1026 69.61% 100.00% # Request fanout histogram 667system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 668system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram 669system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram 670system.cpu.toL2Bus.snoop_fanout::total 1474 # Request fanout histogram 671system.cpu.toL2Bus.reqLayer0.occupancy 224000 # Layer occupancy (ticks) 672system.cpu.toL2Bus.reqLayer0.utilization 1.9 # Layer utilization (%) 673system.cpu.toL2Bus.respLayer0.occupancy 461250 # Layer occupancy (ticks) 674system.cpu.toL2Bus.respLayer0.utilization 3.9 # Layer utilization (%) 675system.cpu.toL2Bus.respLayer1.occupancy 223747 # Layer occupancy (ticks) 676system.cpu.toL2Bus.respLayer1.utilization 1.9 # Layer utilization (%) 677system.cpu.icache.tags.replacements 47 # number of replacements 678system.cpu.icache.tags.tagsinuse 138.950029 # Cycle average of tags in use 679system.cpu.icache.tags.total_refs 3784 # Total number of references to valid blocks. 680system.cpu.icache.tags.sampled_refs 304 # Sample count of references to valid blocks. 681system.cpu.icache.tags.avg_refs 12.447368 # Average number of references to valid blocks. |
| 658system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 682system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 659system.cpu.icache.tags.occ_blocks::cpu.inst 150.758993 # Average occupied blocks per requestor 660system.cpu.icache.tags.occ_percent::cpu.inst 0.073613 # Average percentage of cache occupancy 661system.cpu.icache.tags.occ_percent::total 0.073613 # Average percentage of cache occupancy 662system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id 663system.cpu.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id 664system.cpu.icache.tags.age_task_id_blocks_1024::1 120 # Occupied blocks per task id 665system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id 666system.cpu.icache.tags.tag_accesses 4430 # Number of tag accesses 667system.cpu.icache.tags.data_accesses 4430 # Number of data accesses 668system.cpu.icache.ReadReq_hits::cpu.inst 1666 # number of ReadReq hits 669system.cpu.icache.ReadReq_hits::total 1666 # number of ReadReq hits 670system.cpu.icache.demand_hits::cpu.inst 1666 # number of demand (read+write) hits 671system.cpu.icache.demand_hits::total 1666 # number of demand (read+write) hits 672system.cpu.icache.overall_hits::cpu.inst 1666 # number of overall hits 673system.cpu.icache.overall_hits::total 1666 # number of overall hits 674system.cpu.icache.ReadReq_misses::cpu.inst 402 # number of ReadReq misses 675system.cpu.icache.ReadReq_misses::total 402 # number of ReadReq misses 676system.cpu.icache.demand_misses::cpu.inst 402 # number of demand (read+write) misses 677system.cpu.icache.demand_misses::total 402 # number of demand (read+write) misses 678system.cpu.icache.overall_misses::cpu.inst 402 # number of overall misses 679system.cpu.icache.overall_misses::total 402 # number of overall misses 680system.cpu.icache.ReadReq_miss_latency::cpu.inst 25574000 # number of ReadReq miss cycles 681system.cpu.icache.ReadReq_miss_latency::total 25574000 # number of ReadReq miss cycles 682system.cpu.icache.demand_miss_latency::cpu.inst 25574000 # number of demand (read+write) miss cycles 683system.cpu.icache.demand_miss_latency::total 25574000 # number of demand (read+write) miss cycles 684system.cpu.icache.overall_miss_latency::cpu.inst 25574000 # number of overall miss cycles 685system.cpu.icache.overall_miss_latency::total 25574000 # number of overall miss cycles 686system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 687system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 688system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 689system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 690system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 691system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 692system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.194391 # miss rate for ReadReq accesses 693system.cpu.icache.ReadReq_miss_rate::total 0.194391 # miss rate for ReadReq accesses 694system.cpu.icache.demand_miss_rate::cpu.inst 0.194391 # miss rate for demand accesses 695system.cpu.icache.demand_miss_rate::total 0.194391 # miss rate for demand accesses 696system.cpu.icache.overall_miss_rate::cpu.inst 0.194391 # miss rate for overall accesses 697system.cpu.icache.overall_miss_rate::total 0.194391 # miss rate for overall accesses 698system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 63616.915423 # average ReadReq miss latency 699system.cpu.icache.ReadReq_avg_miss_latency::total 63616.915423 # average ReadReq miss latency 700system.cpu.icache.demand_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 701system.cpu.icache.demand_avg_miss_latency::total 63616.915423 # average overall miss latency 702system.cpu.icache.overall_avg_miss_latency::cpu.inst 63616.915423 # average overall miss latency 703system.cpu.icache.overall_avg_miss_latency::total 63616.915423 # average overall miss latency 704system.cpu.icache.blocked_cycles::no_mshrs 298 # number of cycles access was blocked | 683system.cpu.icache.tags.occ_blocks::cpu.inst 138.950029 # Average occupied blocks per requestor 684system.cpu.icache.tags.occ_percent::cpu.inst 0.271387 # Average percentage of cache occupancy 685system.cpu.icache.tags.occ_percent::total 0.271387 # Average percentage of cache occupancy 686system.cpu.icache.tags.occ_task_id_blocks::1024 257 # Occupied blocks per task id 687system.cpu.icache.tags.age_task_id_blocks_1024::0 228 # Occupied blocks per task id 688system.cpu.icache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 689system.cpu.icache.tags.occ_task_id_percent::1024 0.501953 # Percentage of cache occupancy per task id 690system.cpu.icache.tags.tag_accesses 8536 # Number of tag accesses 691system.cpu.icache.tags.data_accesses 8536 # Number of data accesses 692system.cpu.icache.ReadReq_hits::cpu.inst 3784 # number of ReadReq hits 693system.cpu.icache.ReadReq_hits::total 3784 # number of ReadReq hits 694system.cpu.icache.demand_hits::cpu.inst 3784 # number of demand (read+write) hits 695system.cpu.icache.demand_hits::total 3784 # number of demand (read+write) hits 696system.cpu.icache.overall_hits::cpu.inst 3784 # number of overall hits 697system.cpu.icache.overall_hits::total 3784 # number of overall hits 698system.cpu.icache.ReadReq_misses::cpu.inst 332 # number of ReadReq misses 699system.cpu.icache.ReadReq_misses::total 332 # number of ReadReq misses 700system.cpu.icache.demand_misses::cpu.inst 332 # number of demand (read+write) misses 701system.cpu.icache.demand_misses::total 332 # number of demand (read+write) misses 702system.cpu.icache.overall_misses::cpu.inst 332 # number of overall misses 703system.cpu.icache.overall_misses::total 332 # number of overall misses 704system.cpu.icache.ReadReq_miss_latency::cpu.inst 7426247 # number of ReadReq miss cycles 705system.cpu.icache.ReadReq_miss_latency::total 7426247 # number of ReadReq miss cycles 706system.cpu.icache.demand_miss_latency::cpu.inst 7426247 # number of demand (read+write) miss cycles 707system.cpu.icache.demand_miss_latency::total 7426247 # number of demand (read+write) miss cycles 708system.cpu.icache.overall_miss_latency::cpu.inst 7426247 # number of overall miss cycles 709system.cpu.icache.overall_miss_latency::total 7426247 # number of overall miss cycles 710system.cpu.icache.ReadReq_accesses::cpu.inst 4116 # number of ReadReq accesses(hits+misses) 711system.cpu.icache.ReadReq_accesses::total 4116 # number of ReadReq accesses(hits+misses) 712system.cpu.icache.demand_accesses::cpu.inst 4116 # number of demand (read+write) accesses 713system.cpu.icache.demand_accesses::total 4116 # number of demand (read+write) accesses 714system.cpu.icache.overall_accesses::cpu.inst 4116 # number of overall (read+write) accesses 715system.cpu.icache.overall_accesses::total 4116 # number of overall (read+write) accesses 716system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.080661 # miss rate for ReadReq accesses 717system.cpu.icache.ReadReq_miss_rate::total 0.080661 # miss rate for ReadReq accesses 718system.cpu.icache.demand_miss_rate::cpu.inst 0.080661 # miss rate for demand accesses 719system.cpu.icache.demand_miss_rate::total 0.080661 # miss rate for demand accesses 720system.cpu.icache.overall_miss_rate::cpu.inst 0.080661 # miss rate for overall accesses 721system.cpu.icache.overall_miss_rate::total 0.080661 # miss rate for overall accesses 722system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 22368.213855 # average ReadReq miss latency 723system.cpu.icache.ReadReq_avg_miss_latency::total 22368.213855 # average ReadReq miss latency 724system.cpu.icache.demand_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 725system.cpu.icache.demand_avg_miss_latency::total 22368.213855 # average overall miss latency 726system.cpu.icache.overall_avg_miss_latency::cpu.inst 22368.213855 # average overall miss latency 727system.cpu.icache.overall_avg_miss_latency::total 22368.213855 # average overall miss latency 728system.cpu.icache.blocked_cycles::no_mshrs 1112 # number of cycles access was blocked |
| 705system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 729system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 706system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked | 730system.cpu.icache.blocked::no_mshrs 66 # number of cycles access was blocked |
| 707system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 731system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 708system.cpu.icache.avg_blocked_cycles::no_mshrs 59.600000 # average number of cycles each access was blocked | 732system.cpu.icache.avg_blocked_cycles::no_mshrs 16.848485 # average number of cycles each access was blocked |
| 709system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 710system.cpu.icache.fast_writes 0 # number of fast writes performed 711system.cpu.icache.cache_copies 0 # number of cache copies performed | 733system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 734system.cpu.icache.fast_writes 0 # number of fast writes performed 735system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 712system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits 713system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits 714system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits 715system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits 716system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits 717system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits 718system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses 719system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses 720system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses 721system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses 722system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses 723system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses 724system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 19742750 # number of ReadReq MSHR miss cycles 725system.cpu.icache.ReadReq_mshr_miss_latency::total 19742750 # number of ReadReq MSHR miss cycles 726system.cpu.icache.demand_mshr_miss_latency::cpu.inst 19742750 # number of demand (read+write) MSHR miss cycles 727system.cpu.icache.demand_mshr_miss_latency::total 19742750 # number of demand (read+write) MSHR miss cycles 728system.cpu.icache.overall_mshr_miss_latency::cpu.inst 19742750 # number of overall MSHR miss cycles 729system.cpu.icache.overall_mshr_miss_latency::total 19742750 # number of overall MSHR miss cycles 730system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for ReadReq accesses 731system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142166 # mshr miss rate for ReadReq accesses 732system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for demand accesses 733system.cpu.icache.demand_mshr_miss_rate::total 0.142166 # mshr miss rate for demand accesses 734system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142166 # mshr miss rate for overall accesses 735system.cpu.icache.overall_mshr_miss_rate::total 0.142166 # mshr miss rate for overall accesses 736system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67152.210884 # average ReadReq mshr miss latency 737system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67152.210884 # average ReadReq mshr miss latency 738system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 739system.cpu.icache.demand_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency 740system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67152.210884 # average overall mshr miss latency 741system.cpu.icache.overall_avg_mshr_miss_latency::total 67152.210884 # average overall mshr miss latency | 736system.cpu.icache.ReadReq_mshr_hits::cpu.inst 28 # number of ReadReq MSHR hits 737system.cpu.icache.ReadReq_mshr_hits::total 28 # number of ReadReq MSHR hits 738system.cpu.icache.demand_mshr_hits::cpu.inst 28 # number of demand (read+write) MSHR hits 739system.cpu.icache.demand_mshr_hits::total 28 # number of demand (read+write) MSHR hits 740system.cpu.icache.overall_mshr_hits::cpu.inst 28 # number of overall MSHR hits 741system.cpu.icache.overall_mshr_hits::total 28 # number of overall MSHR hits 742system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses 743system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses 744system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses 745system.cpu.icache.demand_mshr_misses::total 304 # number of demand (read+write) MSHR misses 746system.cpu.icache.overall_mshr_misses::cpu.inst 304 # number of overall MSHR misses 747system.cpu.icache.overall_mshr_misses::total 304 # number of overall MSHR misses 748system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6489997 # number of ReadReq MSHR miss cycles 749system.cpu.icache.ReadReq_mshr_miss_latency::total 6489997 # number of ReadReq MSHR miss cycles 750system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6489997 # number of demand (read+write) MSHR miss cycles 751system.cpu.icache.demand_mshr_miss_latency::total 6489997 # number of demand (read+write) MSHR miss cycles 752system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6489997 # number of overall MSHR miss cycles 753system.cpu.icache.overall_mshr_miss_latency::total 6489997 # number of overall MSHR miss cycles 754system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for ReadReq accesses 755system.cpu.icache.ReadReq_mshr_miss_rate::total 0.073858 # mshr miss rate for ReadReq accesses 756system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for demand accesses 757system.cpu.icache.demand_mshr_miss_rate::total 0.073858 # mshr miss rate for demand accesses 758system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.073858 # mshr miss rate for overall accesses 759system.cpu.icache.overall_mshr_miss_rate::total 0.073858 # mshr miss rate for overall accesses 760system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21348.674342 # average ReadReq mshr miss latency 761system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 21348.674342 # average ReadReq mshr miss latency 762system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 763system.cpu.icache.demand_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency 764system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21348.674342 # average overall mshr miss latency 765system.cpu.icache.overall_avg_mshr_miss_latency::total 21348.674342 # average overall mshr miss latency |
| 742system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 766system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 767system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_identified 2346 # number of hwpf identified 768system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 489 # number of hwpf that were already in mshr 769system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 1139 # number of hwpf that were already in the cache 770system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 86 # number of hwpf that were already in the prefetch queue 771system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left 772system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 29 # number of hwpf removed because MSHR allocated 773system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_issued 603 # number of hwpf issued 774system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_span_page 198 # number of hwpf spanning a virtual page 775system.cpu.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
|
| 743system.cpu.l2cache.tags.replacements 0 # number of replacements | 776system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 744system.cpu.l2cache.tags.tagsinuse 188.170247 # Cycle average of tags in use 745system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. 746system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. 747system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. | 777system.cpu.l2cache.tags.tagsinuse 370.948422 # Cycle average of tags in use 778system.cpu.l2cache.tags.total_refs 270 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 691 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.390738 # Average number of references to valid blocks. |
| 748system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 749system.cpu.l2cache.tags.occ_blocks::cpu.inst 141.371533 # Average occupied blocks per requestor 750system.cpu.l2cache.tags.occ_blocks::cpu.data 46.798714 # Average occupied blocks per requestor 751system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004314 # Average percentage of cache occupancy 752system.cpu.l2cache.tags.occ_percent::cpu.data 0.001428 # Average percentage of cache occupancy 753system.cpu.l2cache.tags.occ_percent::total 0.005743 # Average percentage of cache occupancy 754system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id 755system.cpu.l2cache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id 756system.cpu.l2cache.tags.age_task_id_blocks_1024::1 157 # Occupied blocks per task id 757system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id 758system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses 759system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses 760system.cpu.l2cache.ReadReq_hits::cpu.inst 19 # number of ReadReq hits 761system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits 762system.cpu.l2cache.ReadReq_hits::total 39 # number of ReadReq hits 763system.cpu.l2cache.demand_hits::cpu.inst 19 # number of demand (read+write) hits 764system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits 765system.cpu.l2cache.demand_hits::total 39 # number of demand (read+write) hits 766system.cpu.l2cache.overall_hits::cpu.inst 19 # number of overall hits 767system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits 768system.cpu.l2cache.overall_hits::total 39 # number of overall hits 769system.cpu.l2cache.ReadReq_misses::cpu.inst 275 # number of ReadReq misses 770system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses 771system.cpu.l2cache.ReadReq_misses::total 360 # number of ReadReq misses 772system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses 773system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses 774system.cpu.l2cache.demand_misses::cpu.inst 275 # number of demand (read+write) misses 775system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses 776system.cpu.l2cache.demand_misses::total 402 # number of demand (read+write) misses 777system.cpu.l2cache.overall_misses::cpu.inst 275 # number of overall misses 778system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses 779system.cpu.l2cache.overall_misses::total 402 # number of overall misses 780system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 19251250 # number of ReadReq miss cycles 781system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6010750 # number of ReadReq miss cycles 782system.cpu.l2cache.ReadReq_miss_latency::total 25262000 # number of ReadReq miss cycles 783system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3101750 # number of ReadExReq miss cycles 784system.cpu.l2cache.ReadExReq_miss_latency::total 3101750 # number of ReadExReq miss cycles 785system.cpu.l2cache.demand_miss_latency::cpu.inst 19251250 # number of demand (read+write) miss cycles 786system.cpu.l2cache.demand_miss_latency::cpu.data 9112500 # number of demand (read+write) miss cycles 787system.cpu.l2cache.demand_miss_latency::total 28363750 # number of demand (read+write) miss cycles 788system.cpu.l2cache.overall_miss_latency::cpu.inst 19251250 # number of overall miss cycles 789system.cpu.l2cache.overall_miss_latency::cpu.data 9112500 # number of overall miss cycles 790system.cpu.l2cache.overall_miss_latency::total 28363750 # number of overall miss cycles 791system.cpu.l2cache.ReadReq_accesses::cpu.inst 294 # number of ReadReq accesses(hits+misses) 792system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) 793system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) 794system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) 795system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) 796system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses 797system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses 798system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses 799system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses 800system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses 801system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses 802system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.935374 # miss rate for ReadReq accesses 803system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.809524 # miss rate for ReadReq accesses 804system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses 805system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 806system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 807system.cpu.l2cache.demand_miss_rate::cpu.inst 0.935374 # miss rate for demand accesses 808system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses 809system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses 810system.cpu.l2cache.overall_miss_rate::cpu.inst 0.935374 # miss rate for overall accesses 811system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses 812system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses 813system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70004.545455 # average ReadReq miss latency 814system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 70714.705882 # average ReadReq miss latency 815system.cpu.l2cache.ReadReq_avg_miss_latency::total 70172.222222 # average ReadReq miss latency 816system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 73851.190476 # average ReadExReq miss latency 817system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73851.190476 # average ReadExReq miss latency 818system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 819system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency 820system.cpu.l2cache.demand_avg_miss_latency::total 70556.592040 # average overall miss latency 821system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70004.545455 # average overall miss latency 822system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71751.968504 # average overall miss latency 823system.cpu.l2cache.overall_avg_miss_latency::total 70556.592040 # average overall miss latency 824system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked | 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 30.449811 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 36.598805 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 303.899806 # Average occupied blocks per requestor 785system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001859 # Average percentage of cache occupancy 786system.cpu.l2cache.tags.occ_percent::cpu.data 0.002234 # Average percentage of cache occupancy 787system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.018549 # Average percentage of cache occupancy 788system.cpu.l2cache.tags.occ_percent::total 0.022641 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_task_id_blocks::1022 570 # Occupied blocks per task id 790system.cpu.l2cache.tags.occ_task_id_blocks::1024 121 # Occupied blocks per task id 791system.cpu.l2cache.tags.age_task_id_blocks_1022::0 471 # Occupied blocks per task id 792system.cpu.l2cache.tags.age_task_id_blocks_1022::1 99 # Occupied blocks per task id 793system.cpu.l2cache.tags.age_task_id_blocks_1024::0 92 # Occupied blocks per task id 794system.cpu.l2cache.tags.age_task_id_blocks_1024::1 29 # Occupied blocks per task id 795system.cpu.l2cache.tags.occ_task_id_percent::1022 0.034790 # Percentage of cache occupancy per task id 796system.cpu.l2cache.tags.occ_task_id_percent::1024 0.007385 # Percentage of cache occupancy per task id 797system.cpu.l2cache.tags.tag_accesses 7899 # Number of tag accesses 798system.cpu.l2cache.tags.data_accesses 7899 # Number of data accesses 799system.cpu.l2cache.ReadReq_hits::cpu.inst 234 # number of ReadReq hits 800system.cpu.l2cache.ReadReq_hits::cpu.data 35 # number of ReadReq hits 801system.cpu.l2cache.ReadReq_hits::total 269 # number of ReadReq hits 802system.cpu.l2cache.ReadExReq_hits::cpu.data 11 # number of ReadExReq hits 803system.cpu.l2cache.ReadExReq_hits::total 11 # number of ReadExReq hits 804system.cpu.l2cache.demand_hits::cpu.inst 234 # number of demand (read+write) hits 805system.cpu.l2cache.demand_hits::cpu.data 46 # number of demand (read+write) hits 806system.cpu.l2cache.demand_hits::total 280 # number of demand (read+write) hits 807system.cpu.l2cache.overall_hits::cpu.inst 234 # number of overall hits 808system.cpu.l2cache.overall_hits::cpu.data 46 # number of overall hits 809system.cpu.l2cache.overall_hits::total 280 # number of overall hits 810system.cpu.l2cache.ReadReq_misses::cpu.inst 70 # number of ReadReq misses 811system.cpu.l2cache.ReadReq_misses::cpu.data 69 # number of ReadReq misses 812system.cpu.l2cache.ReadReq_misses::total 139 # number of ReadReq misses 813system.cpu.l2cache.ReadExReq_misses::cpu.data 29 # number of ReadExReq misses 814system.cpu.l2cache.ReadExReq_misses::total 29 # number of ReadExReq misses 815system.cpu.l2cache.demand_misses::cpu.inst 70 # number of demand (read+write) misses 816system.cpu.l2cache.demand_misses::cpu.data 98 # number of demand (read+write) misses 817system.cpu.l2cache.demand_misses::total 168 # number of demand (read+write) misses 818system.cpu.l2cache.overall_misses::cpu.inst 70 # number of overall misses 819system.cpu.l2cache.overall_misses::cpu.data 98 # number of overall misses 820system.cpu.l2cache.overall_misses::total 168 # number of overall misses 821system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 4724750 # number of ReadReq miss cycles 822system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5170750 # number of ReadReq miss cycles 823system.cpu.l2cache.ReadReq_miss_latency::total 9895500 # number of ReadReq miss cycles 824system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2577500 # number of ReadExReq miss cycles 825system.cpu.l2cache.ReadExReq_miss_latency::total 2577500 # number of ReadExReq miss cycles 826system.cpu.l2cache.demand_miss_latency::cpu.inst 4724750 # number of demand (read+write) miss cycles 827system.cpu.l2cache.demand_miss_latency::cpu.data 7748250 # number of demand (read+write) miss cycles 828system.cpu.l2cache.demand_miss_latency::total 12473000 # number of demand (read+write) miss cycles 829system.cpu.l2cache.overall_miss_latency::cpu.inst 4724750 # number of overall miss cycles 830system.cpu.l2cache.overall_miss_latency::cpu.data 7748250 # number of overall miss cycles 831system.cpu.l2cache.overall_miss_latency::total 12473000 # number of overall miss cycles 832system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) 833system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) 834system.cpu.l2cache.ReadReq_accesses::total 408 # number of ReadReq accesses(hits+misses) 835system.cpu.l2cache.ReadExReq_accesses::cpu.data 40 # number of ReadExReq accesses(hits+misses) 836system.cpu.l2cache.ReadExReq_accesses::total 40 # number of ReadExReq accesses(hits+misses) 837system.cpu.l2cache.demand_accesses::cpu.inst 304 # number of demand (read+write) accesses 838system.cpu.l2cache.demand_accesses::cpu.data 144 # number of demand (read+write) accesses 839system.cpu.l2cache.demand_accesses::total 448 # number of demand (read+write) accesses 840system.cpu.l2cache.overall_accesses::cpu.inst 304 # number of overall (read+write) accesses 841system.cpu.l2cache.overall_accesses::cpu.data 144 # number of overall (read+write) accesses 842system.cpu.l2cache.overall_accesses::total 448 # number of overall (read+write) accesses 843system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.230263 # miss rate for ReadReq accesses 844system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.663462 # miss rate for ReadReq accesses 845system.cpu.l2cache.ReadReq_miss_rate::total 0.340686 # miss rate for ReadReq accesses 846system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.725000 # miss rate for ReadExReq accesses 847system.cpu.l2cache.ReadExReq_miss_rate::total 0.725000 # miss rate for ReadExReq accesses 848system.cpu.l2cache.demand_miss_rate::cpu.inst 0.230263 # miss rate for demand accesses 849system.cpu.l2cache.demand_miss_rate::cpu.data 0.680556 # miss rate for demand accesses 850system.cpu.l2cache.demand_miss_rate::total 0.375000 # miss rate for demand accesses 851system.cpu.l2cache.overall_miss_rate::cpu.inst 0.230263 # miss rate for overall accesses 852system.cpu.l2cache.overall_miss_rate::cpu.data 0.680556 # miss rate for overall accesses 853system.cpu.l2cache.overall_miss_rate::total 0.375000 # miss rate for overall accesses 854system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67496.428571 # average ReadReq miss latency 855system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74938.405797 # average ReadReq miss latency 856system.cpu.l2cache.ReadReq_avg_miss_latency::total 71190.647482 # average ReadReq miss latency 857system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 88879.310345 # average ReadExReq miss latency 858system.cpu.l2cache.ReadExReq_avg_miss_latency::total 88879.310345 # average ReadExReq miss latency 859system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 860system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 861system.cpu.l2cache.demand_avg_miss_latency::total 74244.047619 # average overall miss latency 862system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67496.428571 # average overall miss latency 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79063.775510 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 74244.047619 # average overall miss latency 865system.cpu.l2cache.blocked_cycles::no_mshrs 388 # number of cycles access was blocked |
| 825system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked | 866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| 826system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked | 867system.cpu.l2cache.blocked::no_mshrs 17 # number of cycles access was blocked |
| 827system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 828system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked | 869system.cpu.l2cache.avg_blocked_cycles::no_mshrs 22.823529 # average number of cycles each access was blocked |
| 829system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 830system.cpu.l2cache.fast_writes 0 # number of fast writes performed 831system.cpu.l2cache.cache_copies 0 # number of cache copies performed | 870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 871system.cpu.l2cache.fast_writes 0 # number of fast writes performed 872system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| 832system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits 833system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits 834system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits 835system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits 836system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits 837system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits 838system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 275 # number of ReadReq MSHR misses 839system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses 840system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses 841system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses 842system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses 843system.cpu.l2cache.demand_mshr_misses::cpu.inst 275 # number of demand (read+write) MSHR misses 844system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses 845system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses 846system.cpu.l2cache.overall_mshr_misses::cpu.inst 275 # number of overall MSHR misses 847system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses 848system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses 849system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15797750 # number of ReadReq MSHR miss cycles 850system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4736000 # number of ReadReq MSHR miss cycles 851system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20533750 # number of ReadReq MSHR miss cycles 852system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2589250 # number of ReadExReq MSHR miss cycles 853system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2589250 # number of ReadExReq MSHR miss cycles 854system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15797750 # number of demand (read+write) MSHR miss cycles 855system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7325250 # number of demand (read+write) MSHR miss cycles 856system.cpu.l2cache.demand_mshr_miss_latency::total 23123000 # number of demand (read+write) MSHR miss cycles 857system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15797750 # number of overall MSHR miss cycles 858system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7325250 # number of overall MSHR miss cycles 859system.cpu.l2cache.overall_mshr_miss_latency::total 23123000 # number of overall MSHR miss cycles 860system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for ReadReq accesses 861system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.761905 # mshr miss rate for ReadReq accesses 862system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses 863system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 864system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 865system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for demand accesses 866system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses 867system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses 868system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935374 # mshr miss rate for overall accesses 869system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses 870system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses 871system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57446.363636 # average ReadReq mshr miss latency 872system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59200 # average ReadReq mshr miss latency 873system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57841.549296 # average ReadReq mshr miss latency 874system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61648.809524 # average ReadExReq mshr miss latency 875system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61648.809524 # average ReadExReq mshr miss latency 876system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 877system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency 878system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency 879system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57446.363636 # average overall mshr miss latency 880system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 60043.032787 # average overall mshr miss latency 881system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58244.332494 # average overall mshr miss latency | 873system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 11 # number of ReadReq MSHR hits 874system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits 875system.cpu.l2cache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits 876system.cpu.l2cache.demand_mshr_hits::cpu.inst 11 # number of demand (read+write) MSHR hits 877system.cpu.l2cache.demand_mshr_hits::cpu.data 6 # number of demand (read+write) MSHR hits 878system.cpu.l2cache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits 879system.cpu.l2cache.overall_mshr_hits::cpu.inst 11 # number of overall MSHR hits 880system.cpu.l2cache.overall_mshr_hits::cpu.data 6 # number of overall MSHR hits 881system.cpu.l2cache.overall_mshr_hits::total 17 # number of overall MSHR hits 882system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 59 # number of ReadReq MSHR misses 883system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses 884system.cpu.l2cache.ReadReq_mshr_misses::total 122 # number of ReadReq MSHR misses 885system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher 603 # number of HardPFReq MSHR misses 886system.cpu.l2cache.HardPFReq_mshr_misses::total 603 # number of HardPFReq MSHR misses 887system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 29 # number of ReadExReq MSHR misses 888system.cpu.l2cache.ReadExReq_mshr_misses::total 29 # number of ReadExReq MSHR misses 889system.cpu.l2cache.demand_mshr_misses::cpu.inst 59 # number of demand (read+write) MSHR misses 890system.cpu.l2cache.demand_mshr_misses::cpu.data 92 # number of demand (read+write) MSHR misses 891system.cpu.l2cache.demand_mshr_misses::total 151 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.overall_mshr_misses::cpu.inst 59 # number of overall MSHR misses 893system.cpu.l2cache.overall_mshr_misses::cpu.data 92 # number of overall MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 603 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::total 754 # number of overall MSHR misses 896system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 3978500 # number of ReadReq MSHR miss cycles 897system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4478500 # number of ReadReq MSHR miss cycles 898system.cpu.l2cache.ReadReq_mshr_miss_latency::total 8457000 # number of ReadReq MSHR miss cycles 899system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of HardPFReq MSHR miss cycles 900system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 49457864 # number of HardPFReq MSHR miss cycles 901system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2337500 # number of ReadExReq MSHR miss cycles 902system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2337500 # number of ReadExReq MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 3978500 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6816000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::total 10794500 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 3978500 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6816000 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 49457864 # number of overall MSHR miss cycles 909system.cpu.l2cache.overall_mshr_miss_latency::total 60252364 # number of overall MSHR miss cycles 910system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for ReadReq accesses 911system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.605769 # mshr miss rate for ReadReq accesses 912system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.299020 # mshr miss rate for ReadReq accesses 913system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses 914system.cpu.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses 915system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.725000 # mshr miss rate for ReadExReq accesses 916system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.725000 # mshr miss rate for ReadExReq accesses 917system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for demand accesses 918system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for demand accesses 919system.cpu.l2cache.demand_mshr_miss_rate::total 0.337054 # mshr miss rate for demand accesses 920system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194079 # mshr miss rate for overall accesses 921system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.638889 # mshr miss rate for overall accesses 922system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses 923system.cpu.l2cache.overall_mshr_miss_rate::total 1.683036 # mshr miss rate for overall accesses 924system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 67432.203390 # average ReadReq mshr miss latency 925system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 71087.301587 # average ReadReq mshr miss latency 926system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 69319.672131 # average ReadReq mshr miss latency 927system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average HardPFReq mshr miss latency 928system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 82019.674959 # average HardPFReq mshr miss latency 929system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80603.448276 # average ReadExReq mshr miss latency 930system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 80603.448276 # average ReadExReq mshr miss latency 931system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 932system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 933system.cpu.l2cache.demand_avg_mshr_miss_latency::total 71486.754967 # average overall mshr miss latency 934system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67432.203390 # average overall mshr miss latency 935system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74086.956522 # average overall mshr miss latency 936system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 82019.674959 # average overall mshr miss latency 937system.cpu.l2cache.overall_avg_mshr_miss_latency::total 79910.297082 # average overall mshr miss latency |
| 882system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 938system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 883system.cpu.dcache.tags.replacements 0 # number of replacements 884system.cpu.dcache.tags.tagsinuse 87.133302 # Cycle average of tags in use 885system.cpu.dcache.tags.total_refs 2168 # Total number of references to valid blocks. 886system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. 887system.cpu.dcache.tags.avg_refs 14.849315 # Average number of references to valid blocks. | 939system.cpu.dcache.tags.replacements 1 # number of replacements 940system.cpu.dcache.tags.tagsinuse 82.309019 # Cycle average of tags in use 941system.cpu.dcache.tags.total_refs 1894 # Total number of references to valid blocks. 942system.cpu.dcache.tags.sampled_refs 143 # Sample count of references to valid blocks. 943system.cpu.dcache.tags.avg_refs 13.244755 # Average number of references to valid blocks. |
| 888system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 944system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 889system.cpu.dcache.tags.occ_blocks::cpu.data 87.133302 # Average occupied blocks per requestor 890system.cpu.dcache.tags.occ_percent::cpu.data 0.021273 # Average percentage of cache occupancy 891system.cpu.dcache.tags.occ_percent::total 0.021273 # Average percentage of cache occupancy 892system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id 893system.cpu.dcache.tags.age_task_id_blocks_1024::0 67 # Occupied blocks per task id 894system.cpu.dcache.tags.age_task_id_blocks_1024::1 79 # Occupied blocks per task id 895system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id 896system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 897system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 898system.cpu.dcache.ReadReq_hits::cpu.data 1551 # number of ReadReq hits 899system.cpu.dcache.ReadReq_hits::total 1551 # number of ReadReq hits 900system.cpu.dcache.WriteReq_hits::cpu.data 595 # number of WriteReq hits 901system.cpu.dcache.WriteReq_hits::total 595 # number of WriteReq hits 902system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits 903system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits | 945system.cpu.dcache.tags.occ_blocks::cpu.data 82.309019 # Average occupied blocks per requestor 946system.cpu.dcache.tags.occ_percent::cpu.data 0.160760 # Average percentage of cache occupancy 947system.cpu.dcache.tags.occ_percent::total 0.160760 # Average percentage of cache occupancy 948system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 949system.cpu.dcache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 950system.cpu.dcache.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id 951system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 # Percentage of cache occupancy per task id 952system.cpu.dcache.tags.tag_accesses 4719 # Number of tag accesses 953system.cpu.dcache.tags.data_accesses 4719 # Number of data accesses 954system.cpu.dcache.ReadReq_hits::cpu.data 1158 # number of ReadReq hits 955system.cpu.dcache.ReadReq_hits::total 1158 # number of ReadReq hits 956system.cpu.dcache.WriteReq_hits::cpu.data 715 # number of WriteReq hits 957system.cpu.dcache.WriteReq_hits::total 715 # number of WriteReq hits 958system.cpu.dcache.LoadLockedReq_hits::cpu.data 10 # number of LoadLockedReq hits 959system.cpu.dcache.LoadLockedReq_hits::total 10 # number of LoadLockedReq hits |
| 904system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 905system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits | 960system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits 961system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| 906system.cpu.dcache.demand_hits::cpu.data 2146 # number of demand (read+write) hits 907system.cpu.dcache.demand_hits::total 2146 # number of demand (read+write) hits 908system.cpu.dcache.overall_hits::cpu.data 2146 # number of overall hits 909system.cpu.dcache.overall_hits::total 2146 # number of overall hits 910system.cpu.dcache.ReadReq_misses::cpu.data 203 # number of ReadReq misses 911system.cpu.dcache.ReadReq_misses::total 203 # number of ReadReq misses 912system.cpu.dcache.WriteReq_misses::cpu.data 318 # number of WriteReq misses 913system.cpu.dcache.WriteReq_misses::total 318 # number of WriteReq misses | 962system.cpu.dcache.demand_hits::cpu.data 1873 # number of demand (read+write) hits 963system.cpu.dcache.demand_hits::total 1873 # number of demand (read+write) hits 964system.cpu.dcache.overall_hits::cpu.data 1873 # number of overall hits 965system.cpu.dcache.overall_hits::total 1873 # number of overall hits 966system.cpu.dcache.ReadReq_misses::cpu.data 194 # number of ReadReq misses 967system.cpu.dcache.ReadReq_misses::total 194 # number of ReadReq misses 968system.cpu.dcache.WriteReq_misses::cpu.data 198 # number of WriteReq misses 969system.cpu.dcache.WriteReq_misses::total 198 # number of WriteReq misses |
| 914system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 915system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses | 970system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses 971system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| 916system.cpu.dcache.demand_misses::cpu.data 521 # number of demand (read+write) misses 917system.cpu.dcache.demand_misses::total 521 # number of demand (read+write) misses 918system.cpu.dcache.overall_misses::cpu.data 521 # number of overall misses 919system.cpu.dcache.overall_misses::total 521 # number of overall misses 920system.cpu.dcache.ReadReq_miss_latency::cpu.data 11351493 # number of ReadReq miss cycles 921system.cpu.dcache.ReadReq_miss_latency::total 11351493 # number of ReadReq miss cycles 922system.cpu.dcache.WriteReq_miss_latency::cpu.data 20745500 # number of WriteReq miss cycles 923system.cpu.dcache.WriteReq_miss_latency::total 20745500 # number of WriteReq miss cycles 924system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 130500 # number of LoadLockedReq miss cycles 925system.cpu.dcache.LoadLockedReq_miss_latency::total 130500 # number of LoadLockedReq miss cycles 926system.cpu.dcache.demand_miss_latency::cpu.data 32096993 # number of demand (read+write) miss cycles 927system.cpu.dcache.demand_miss_latency::total 32096993 # number of demand (read+write) miss cycles 928system.cpu.dcache.overall_miss_latency::cpu.data 32096993 # number of overall miss cycles 929system.cpu.dcache.overall_miss_latency::total 32096993 # number of overall miss cycles 930system.cpu.dcache.ReadReq_accesses::cpu.data 1754 # number of ReadReq accesses(hits+misses) 931system.cpu.dcache.ReadReq_accesses::total 1754 # number of ReadReq accesses(hits+misses) | 972system.cpu.dcache.demand_misses::cpu.data 392 # number of demand (read+write) misses 973system.cpu.dcache.demand_misses::total 392 # number of demand (read+write) misses 974system.cpu.dcache.overall_misses::cpu.data 392 # number of overall misses 975system.cpu.dcache.overall_misses::total 392 # number of overall misses 976system.cpu.dcache.ReadReq_miss_latency::cpu.data 10805495 # number of ReadReq miss cycles 977system.cpu.dcache.ReadReq_miss_latency::total 10805495 # number of ReadReq miss cycles 978system.cpu.dcache.WriteReq_miss_latency::cpu.data 8861750 # number of WriteReq miss cycles 979system.cpu.dcache.WriteReq_miss_latency::total 8861750 # number of WriteReq miss cycles 980system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 152500 # number of LoadLockedReq miss cycles 981system.cpu.dcache.LoadLockedReq_miss_latency::total 152500 # number of LoadLockedReq miss cycles 982system.cpu.dcache.demand_miss_latency::cpu.data 19667245 # number of demand (read+write) miss cycles 983system.cpu.dcache.demand_miss_latency::total 19667245 # number of demand (read+write) miss cycles 984system.cpu.dcache.overall_miss_latency::cpu.data 19667245 # number of overall miss cycles 985system.cpu.dcache.overall_miss_latency::total 19667245 # number of overall miss cycles 986system.cpu.dcache.ReadReq_accesses::cpu.data 1352 # number of ReadReq accesses(hits+misses) 987system.cpu.dcache.ReadReq_accesses::total 1352 # number of ReadReq accesses(hits+misses) |
| 932system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 933system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) | 988system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) 989system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) |
| 934system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) 935system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) | 990system.cpu.dcache.LoadLockedReq_accesses::cpu.data 12 # number of LoadLockedReq accesses(hits+misses) 991system.cpu.dcache.LoadLockedReq_accesses::total 12 # number of LoadLockedReq accesses(hits+misses) |
| 936system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 937system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) | 992system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) 993system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| 938system.cpu.dcache.demand_accesses::cpu.data 2667 # number of demand (read+write) accesses 939system.cpu.dcache.demand_accesses::total 2667 # number of demand (read+write) accesses 940system.cpu.dcache.overall_accesses::cpu.data 2667 # number of overall (read+write) accesses 941system.cpu.dcache.overall_accesses::total 2667 # number of overall (read+write) accesses 942system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.115735 # miss rate for ReadReq accesses 943system.cpu.dcache.ReadReq_miss_rate::total 0.115735 # miss rate for ReadReq accesses 944system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.348302 # miss rate for WriteReq accesses 945system.cpu.dcache.WriteReq_miss_rate::total 0.348302 # miss rate for WriteReq accesses 946system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses 947system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses 948system.cpu.dcache.demand_miss_rate::cpu.data 0.195351 # miss rate for demand accesses 949system.cpu.dcache.demand_miss_rate::total 0.195351 # miss rate for demand accesses 950system.cpu.dcache.overall_miss_rate::cpu.data 0.195351 # miss rate for overall accesses 951system.cpu.dcache.overall_miss_rate::total 0.195351 # miss rate for overall accesses 952system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55918.684729 # average ReadReq miss latency 953system.cpu.dcache.ReadReq_avg_miss_latency::total 55918.684729 # average ReadReq miss latency 954system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65237.421384 # average WriteReq miss latency 955system.cpu.dcache.WriteReq_avg_miss_latency::total 65237.421384 # average WriteReq miss latency 956system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 65250 # average LoadLockedReq miss latency 957system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 65250 # average LoadLockedReq miss latency 958system.cpu.dcache.demand_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 959system.cpu.dcache.demand_avg_miss_latency::total 61606.512476 # average overall miss latency 960system.cpu.dcache.overall_avg_miss_latency::cpu.data 61606.512476 # average overall miss latency 961system.cpu.dcache.overall_avg_miss_latency::total 61606.512476 # average overall miss latency 962system.cpu.dcache.blocked_cycles::no_mshrs 105 # number of cycles access was blocked 963system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 964system.cpu.dcache.blocked::no_mshrs 4 # number of cycles access was blocked 965system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 966system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.250000 # average number of cycles each access was blocked 967system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 994system.cpu.dcache.demand_accesses::cpu.data 2265 # number of demand (read+write) accesses 995system.cpu.dcache.demand_accesses::total 2265 # number of demand (read+write) accesses 996system.cpu.dcache.overall_accesses::cpu.data 2265 # number of overall (read+write) accesses 997system.cpu.dcache.overall_accesses::total 2265 # number of overall (read+write) accesses 998system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.143491 # miss rate for ReadReq accesses 999system.cpu.dcache.ReadReq_miss_rate::total 0.143491 # miss rate for ReadReq accesses 1000system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.216867 # miss rate for WriteReq accesses 1001system.cpu.dcache.WriteReq_miss_rate::total 0.216867 # miss rate for WriteReq accesses 1002system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.166667 # miss rate for LoadLockedReq accesses 1003system.cpu.dcache.LoadLockedReq_miss_rate::total 0.166667 # miss rate for LoadLockedReq accesses 1004system.cpu.dcache.demand_miss_rate::cpu.data 0.173068 # miss rate for demand accesses 1005system.cpu.dcache.demand_miss_rate::total 0.173068 # miss rate for demand accesses 1006system.cpu.dcache.overall_miss_rate::cpu.data 0.173068 # miss rate for overall accesses 1007system.cpu.dcache.overall_miss_rate::total 0.173068 # miss rate for overall accesses 1008system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55698.427835 # average ReadReq miss latency 1009system.cpu.dcache.ReadReq_avg_miss_latency::total 55698.427835 # average ReadReq miss latency 1010system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44756.313131 # average WriteReq miss latency 1011system.cpu.dcache.WriteReq_avg_miss_latency::total 44756.313131 # average WriteReq miss latency 1012system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 76250 # average LoadLockedReq miss latency 1013system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 76250 # average LoadLockedReq miss latency 1014system.cpu.dcache.demand_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1015system.cpu.dcache.demand_avg_miss_latency::total 50171.543367 # average overall miss latency 1016system.cpu.dcache.overall_avg_miss_latency::cpu.data 50171.543367 # average overall miss latency 1017system.cpu.dcache.overall_avg_miss_latency::total 50171.543367 # average overall miss latency 1018system.cpu.dcache.blocked_cycles::no_mshrs 10 # number of cycles access was blocked 1019system.cpu.dcache.blocked_cycles::no_targets 617 # number of cycles access was blocked 1020system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked 1021system.cpu.dcache.blocked::no_targets 18 # number of cycles access was blocked 1022system.cpu.dcache.avg_blocked_cycles::no_mshrs 10 # average number of cycles each access was blocked 1023system.cpu.dcache.avg_blocked_cycles::no_targets 34.277778 # average number of cycles each access was blocked |
| 968system.cpu.dcache.fast_writes 0 # number of fast writes performed 969system.cpu.dcache.cache_copies 0 # number of cache copies performed | 1024system.cpu.dcache.fast_writes 0 # number of fast writes performed 1025system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 970system.cpu.dcache.ReadReq_mshr_hits::cpu.data 98 # number of ReadReq MSHR hits 971system.cpu.dcache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits 972system.cpu.dcache.WriteReq_mshr_hits::cpu.data 276 # number of WriteReq MSHR hits 973system.cpu.dcache.WriteReq_mshr_hits::total 276 # number of WriteReq MSHR hits | 1026system.cpu.dcache.ReadReq_mshr_hits::cpu.data 90 # number of ReadReq MSHR hits 1027system.cpu.dcache.ReadReq_mshr_hits::total 90 # number of ReadReq MSHR hits 1028system.cpu.dcache.WriteReq_mshr_hits::cpu.data 158 # number of WriteReq MSHR hits 1029system.cpu.dcache.WriteReq_mshr_hits::total 158 # number of WriteReq MSHR hits |
| 974system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 975system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits | 1030system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits 1031system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| 976system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 977system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 978system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 979system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits 980system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses 981system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses 982system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses 983system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses 984system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses 985system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses 986system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 987system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses 988system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6245255 # number of ReadReq MSHR miss cycles 989system.cpu.dcache.ReadReq_mshr_miss_latency::total 6245255 # number of ReadReq MSHR miss cycles 990system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3144750 # number of WriteReq MSHR miss cycles 991system.cpu.dcache.WriteReq_mshr_miss_latency::total 3144750 # number of WriteReq MSHR miss cycles 992system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9390005 # number of demand (read+write) MSHR miss cycles 993system.cpu.dcache.demand_mshr_miss_latency::total 9390005 # number of demand (read+write) MSHR miss cycles 994system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9390005 # number of overall MSHR miss cycles 995system.cpu.dcache.overall_mshr_miss_latency::total 9390005 # number of overall MSHR miss cycles 996system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059863 # mshr miss rate for ReadReq accesses 997system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059863 # mshr miss rate for ReadReq accesses 998system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses 999system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses 1000system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for demand accesses 1001system.cpu.dcache.demand_mshr_miss_rate::total 0.055118 # mshr miss rate for demand accesses 1002system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055118 # mshr miss rate for overall accesses 1003system.cpu.dcache.overall_mshr_miss_rate::total 0.055118 # mshr miss rate for overall accesses 1004system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59478.619048 # average ReadReq mshr miss latency 1005system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59478.619048 # average ReadReq mshr miss latency 1006system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 74875 # average WriteReq mshr miss latency 1007system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 74875 # average WriteReq mshr miss latency 1008system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1009system.cpu.dcache.demand_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency 1010system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 63877.585034 # average overall mshr miss latency 1011system.cpu.dcache.overall_avg_mshr_miss_latency::total 63877.585034 # average overall mshr miss latency | 1032system.cpu.dcache.demand_mshr_hits::cpu.data 248 # number of demand (read+write) MSHR hits 1033system.cpu.dcache.demand_mshr_hits::total 248 # number of demand (read+write) MSHR hits 1034system.cpu.dcache.overall_mshr_hits::cpu.data 248 # number of overall MSHR hits 1035system.cpu.dcache.overall_mshr_hits::total 248 # number of overall MSHR hits 1036system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses 1037system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses 1038system.cpu.dcache.WriteReq_mshr_misses::cpu.data 40 # number of WriteReq MSHR misses 1039system.cpu.dcache.WriteReq_mshr_misses::total 40 # number of WriteReq MSHR misses 1040system.cpu.dcache.demand_mshr_misses::cpu.data 144 # number of demand (read+write) MSHR misses 1041system.cpu.dcache.demand_mshr_misses::total 144 # number of demand (read+write) MSHR misses 1042system.cpu.dcache.overall_mshr_misses::cpu.data 144 # number of overall MSHR misses 1043system.cpu.dcache.overall_mshr_misses::total 144 # number of overall MSHR misses 1044system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5492753 # number of ReadReq MSHR miss cycles 1045system.cpu.dcache.ReadReq_mshr_miss_latency::total 5492753 # number of ReadReq MSHR miss cycles 1046system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2689000 # number of WriteReq MSHR miss cycles 1047system.cpu.dcache.WriteReq_mshr_miss_latency::total 2689000 # number of WriteReq MSHR miss cycles 1048system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8181753 # number of demand (read+write) MSHR miss cycles 1049system.cpu.dcache.demand_mshr_miss_latency::total 8181753 # number of demand (read+write) MSHR miss cycles 1050system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8181753 # number of overall MSHR miss cycles 1051system.cpu.dcache.overall_mshr_miss_latency::total 8181753 # number of overall MSHR miss cycles 1052system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076923 # mshr miss rate for ReadReq accesses 1053system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076923 # mshr miss rate for ReadReq accesses 1054system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.043812 # mshr miss rate for WriteReq accesses 1055system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.043812 # mshr miss rate for WriteReq accesses 1056system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for demand accesses 1057system.cpu.dcache.demand_mshr_miss_rate::total 0.063576 # mshr miss rate for demand accesses 1058system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063576 # mshr miss rate for overall accesses 1059system.cpu.dcache.overall_mshr_miss_rate::total 0.063576 # mshr miss rate for overall accesses 1060system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52814.932692 # average ReadReq mshr miss latency 1061system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52814.932692 # average ReadReq mshr miss latency 1062system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 67225 # average WriteReq mshr miss latency 1063system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 67225 # average WriteReq mshr miss latency 1064system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1065system.cpu.dcache.demand_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency 1066system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56817.729167 # average overall mshr miss latency 1067system.cpu.dcache.overall_avg_mshr_miss_latency::total 56817.729167 # average overall mshr miss latency |
| 1012system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1013 1014---------- End Simulation Statistics ---------- | 1068system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 1069 1070---------- End Simulation Statistics ---------- |