| stats.txt (10036:80e84beef3bb) | stats.txt (10038:7eccd14e2610) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 16981000 # Number of ticks simulated 5final_tick 16981000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 34743 # Simulator instruction rate (inst/s) 8host_op_rate 43351 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 128481440 # Simulator tick rate (ticks/s) 10host_mem_usage 246872 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 45620 # Simulator instruction rate (inst/s) 8host_op_rate 56920 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 168691831 # Simulator tick rate (ticks/s) 10host_mem_usage 267756 # Number of bytes of host memory used 11host_seconds 0.10 # Real time elapsed on the host |
| 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory --- 202 unchanged lines hidden (view full) --- 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. | 12sim_insts 4591 # Number of instructions simulated 13sim_ops 5729 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 17280 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory 18system.physmem.bytes_read::total 25088 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 17280 # Number of instructions bytes read from this memory --- 202 unchanged lines hidden (view full) --- 222system.cpu.branchPred.condPredicted 1780 # Number of conditional branches predicted 223system.cpu.branchPred.condIncorrect 482 # Number of conditional branches incorrect 224system.cpu.branchPred.BTBLookups 1967 # Number of BTB lookups 225system.cpu.branchPred.BTBHits 697 # Number of BTB hits 226system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 227system.cpu.branchPred.BTBHitPct 35.434672 # BTB Hit Percentage 228system.cpu.branchPred.usedRAS 293 # Number of times the RAS was used to get a target. 229system.cpu.branchPred.RASInCorrect 71 # Number of incorrect RAS predictions. |
| 230system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 231system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 232system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 233system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 234system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 235system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 236system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 238system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 239system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 240system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 241system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 242system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 243system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 246system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 247system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 248system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits 249system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses 250system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 230system.cpu.dtb.inst_hits 0 # ITB inst hits 231system.cpu.dtb.inst_misses 0 # ITB inst misses 232system.cpu.dtb.read_hits 0 # DTB read hits 233system.cpu.dtb.read_misses 0 # DTB read misses 234system.cpu.dtb.write_hits 0 # DTB write hits 235system.cpu.dtb.write_misses 0 # DTB write misses 236system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 237system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 243system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 244system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 245system.cpu.dtb.read_accesses 0 # DTB read accesses 246system.cpu.dtb.write_accesses 0 # DTB write accesses 247system.cpu.dtb.inst_accesses 0 # ITB inst accesses 248system.cpu.dtb.hits 0 # DTB hits 249system.cpu.dtb.misses 0 # DTB misses 250system.cpu.dtb.accesses 0 # DTB accesses | 251system.cpu.dtb.inst_hits 0 # ITB inst hits 252system.cpu.dtb.inst_misses 0 # ITB inst misses 253system.cpu.dtb.read_hits 0 # DTB read hits 254system.cpu.dtb.read_misses 0 # DTB read misses 255system.cpu.dtb.write_hits 0 # DTB write hits 256system.cpu.dtb.write_misses 0 # DTB write misses 257system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 5 unchanged lines hidden (view full) --- 264system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions 265system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions 266system.cpu.dtb.read_accesses 0 # DTB read accesses 267system.cpu.dtb.write_accesses 0 # DTB write accesses 268system.cpu.dtb.inst_accesses 0 # ITB inst accesses 269system.cpu.dtb.hits 0 # DTB hits 270system.cpu.dtb.misses 0 # DTB misses 271system.cpu.dtb.accesses 0 # DTB accesses |
| 272system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits 273system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses 274system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits 275system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses 276system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits 277system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses 278system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed 279system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA 280system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID 281system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID 282system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB 283system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions 284system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch 285system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions 286system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions 287system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses 288system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses 289system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses 290system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits 291system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses 292system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
|
| 251system.cpu.itb.inst_hits 0 # ITB inst hits 252system.cpu.itb.inst_misses 0 # ITB inst misses 253system.cpu.itb.read_hits 0 # DTB read hits 254system.cpu.itb.read_misses 0 # DTB read misses 255system.cpu.itb.write_hits 0 # DTB write hits 256system.cpu.itb.write_misses 0 # DTB write misses 257system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 258system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 57 unchanged lines hidden (view full) --- 316system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 317system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 318system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 319system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 320system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 321system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 322system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 323system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed | 293system.cpu.itb.inst_hits 0 # ITB inst hits 294system.cpu.itb.inst_misses 0 # ITB inst misses 295system.cpu.itb.read_hits 0 # DTB read hits 296system.cpu.itb.read_misses 0 # DTB read misses 297system.cpu.itb.write_hits 0 # DTB write hits 298system.cpu.itb.write_misses 0 # DTB write misses 299system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed 300system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA --- 57 unchanged lines hidden (view full) --- 358system.cpu.rename.serializeStallCycles 2278 # count of cycles rename stalled for serializing inst 359system.cpu.rename.RunCycles 2227 # Number of cycles rename is running 360system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking 361system.cpu.rename.RenamedInsts 12456 # Number of instructions processed by rename 362system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 363system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full 364system.cpu.rename.LSQFullEvents 171 # Number of times rename has blocked due to LSQ full 365system.cpu.rename.RenamedOperands 12490 # Number of destination operands rename has renamed |
| 324system.cpu.rename.RenameLookups 56507 # Number of register rename lookups that rename has made | 366system.cpu.rename.RenameLookups 56756 # Number of register rename lookups that rename has made |
| 325system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 326system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 327system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 328system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 329system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 330system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 331system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 332system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 333system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 334system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 335system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 336system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 337system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 338system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 339system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 340system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling | 367system.cpu.rename.int_rename_lookups 51556 # Number of integer rename lookups 368system.cpu.rename.fp_rename_lookups 32 # Number of floating rename lookups 369system.cpu.rename.CommittedMaps 5673 # Number of HB maps that are committed 370system.cpu.rename.UndoneMaps 6817 # Number of HB maps that are undone due to squashing 371system.cpu.rename.serializingInsts 41 # count of serializing insts renamed 372system.cpu.rename.tempSerializingInsts 38 # count of temporary serializing insts renamed 373system.cpu.rename.skidInsts 665 # count of insts added to the skid buffer 374system.cpu.memDep0.insertedLoads 2790 # Number of loads inserted to the mem dependence unit. 375system.cpu.memDep0.insertedStores 1564 # Number of stores inserted to the mem dependence unit. 376system.cpu.memDep0.conflictingLoads 37 # Number of conflicting loads. 377system.cpu.memDep0.conflictingStores 14 # Number of conflicting stores. 378system.cpu.iq.iqInstsAdded 11171 # Number of instructions added to the IQ (excludes non-spec) 379system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ 380system.cpu.iq.iqInstsIssued 8921 # Number of instructions issued 381system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued 382system.cpu.iq.iqSquashedInstsExamined 5124 # Number of squashed instructions iterated over during squash; mainly for profiling |
| 341system.cpu.iq.iqSquashedOperandsExamined 14193 # Number of squashed operands that are examined and possibly removed from graph | 383system.cpu.iq.iqSquashedOperandsExamined 14241 # Number of squashed operands that are examined and possibly removed from graph |
| 342system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 343system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 345system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle --- 170 unchanged lines hidden (view full) --- 520system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 521system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 522system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 523system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 524system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 525system.cpu.int_regfile_reads 39210 # number of integer regfile reads 526system.cpu.int_regfile_writes 7985 # number of integer regfile writes 527system.cpu.fp_regfile_reads 16 # number of floating regfile reads | 384system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed 385system.cpu.iq.issued_per_cycle::samples 13238 # Number of insts issued each cycle 386system.cpu.iq.issued_per_cycle::mean 0.673893 # Number of insts issued each cycle 387system.cpu.iq.issued_per_cycle::stdev 1.378375 # Number of insts issued each cycle 388system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 389system.cpu.iq.issued_per_cycle::0 9658 72.96% 72.96% # Number of insts issued each cycle 390system.cpu.iq.issued_per_cycle::1 1314 9.93% 82.88% # Number of insts issued each cycle 391system.cpu.iq.issued_per_cycle::2 816 6.16% 89.05% # Number of insts issued each cycle --- 170 unchanged lines hidden (view full) --- 562system.cpu.committedInsts_total 4591 # Number of Instructions Simulated 563system.cpu.cpi 7.397735 # CPI: Cycles Per Instruction 564system.cpu.cpi_total 7.397735 # CPI: Total CPI of All Threads 565system.cpu.ipc 0.135177 # IPC: Instructions Per Cycle 566system.cpu.ipc_total 0.135177 # IPC: Total IPC of All Threads 567system.cpu.int_regfile_reads 39210 # number of integer regfile reads 568system.cpu.int_regfile_writes 7985 # number of integer regfile writes 569system.cpu.fp_regfile_reads 16 # number of floating regfile reads |
| 528system.cpu.misc_regfile_reads 2977 # number of misc regfile reads | 570system.cpu.misc_regfile_reads 3239 # number of misc regfile reads |
| 529system.cpu.misc_regfile_writes 24 # number of misc regfile writes 530system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 531system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 534system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 535system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 536system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) --- 374 unchanged lines hidden --- | 571system.cpu.misc_regfile_writes 24 # number of misc regfile writes 572system.cpu.toL2Bus.throughput 1643248336 # Throughput (bytes/s) 573system.cpu.toL2Bus.trans_dist::ReadReq 396 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 395 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 41 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 41 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 580 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) --- 374 unchanged lines hidden --- |