7,11c7,11
< host_inst_rate 29431 # Simulator instruction rate (inst/s)
< host_op_rate 36712 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 65901409 # Simulator tick rate (ticks/s)
< host_mem_usage 229344 # Number of bytes of host memory used
< host_seconds 0.16 # Real time elapsed on the host
---
> host_inst_rate 49511 # Simulator instruction rate (inst/s)
> host_op_rate 61757 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 110854808 # Simulator tick rate (ticks/s)
> host_mem_usage 229756 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 25664 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 401 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
> system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
367a375
> system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
368a377
> system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
369a379
> system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
370a381
> system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
371a383
> system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
372a385
> system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
399a413
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
400a415
> system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
401a417
> system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
402a419
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
403a421
> system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
404a423
> system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
459a479
> system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
460a481
> system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
461a483
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
462a485
> system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
463a487
> system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
464a489
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
465a491
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
466a493
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
467a495
> system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
468a497
> system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
503a533
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
504a535
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
505a537
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
506a539
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
507a541
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
508a543
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
509a545
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
510a547
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
566a604
> system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
567a606
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
569a609
> system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
571a612
> system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
573a615
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
574a617
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
576a620
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
578a623
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
616a662
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
617a664
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
619a667
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
621a670
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
623a673
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
624a675
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
626a678
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
628a681
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
< host_inst_rate 29431 # Simulator instruction rate (inst/s)
< host_op_rate 36712 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 65901409 # Simulator tick rate (ticks/s)
< host_mem_usage 229344 # Number of bytes of host memory used
< host_seconds 0.16 # Real time elapsed on the host
---
> host_inst_rate 49511 # Simulator instruction rate (inst/s)
> host_op_rate 61757 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 110854808 # Simulator tick rate (ticks/s)
> host_mem_usage 229756 # Number of bytes of host memory used
> host_seconds 0.09 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 25664 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 17664 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 401 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2490804096 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1714368904 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2490804096 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory
> system.physmem.bytes_read::total 25664 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 401 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1714368904 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 776435192 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2490804096 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1714368904 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1714368904 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 776435192 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2490804096 # Total bandwidth to/from this memory (bytes/s)
367a375
> system.cpu.icache.ReadReq_miss_rate::total 0.180207 # miss rate for ReadReq accesses
368a377
> system.cpu.icache.demand_miss_rate::total 0.180207 # miss rate for demand accesses
369a379
> system.cpu.icache.overall_miss_rate::total 0.180207 # miss rate for overall accesses
370a381
> system.cpu.icache.ReadReq_avg_miss_latency::total 34474.043716 # average ReadReq miss latency
371a383
> system.cpu.icache.demand_avg_miss_latency::total 34474.043716 # average overall miss latency
372a385
> system.cpu.icache.overall_avg_miss_latency::total 34474.043716 # average overall miss latency
399a413
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145741 # mshr miss rate for ReadReq accesses
400a415
> system.cpu.icache.demand_mshr_miss_rate::total 0.145741 # mshr miss rate for demand accesses
401a417
> system.cpu.icache.overall_mshr_miss_rate::total 0.145741 # mshr miss rate for overall accesses
402a419
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 33221.283784 # average ReadReq mshr miss latency
403a421
> system.cpu.icache.demand_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
404a423
> system.cpu.icache.overall_avg_mshr_miss_latency::total 33221.283784 # average overall mshr miss latency
459a479
> system.cpu.dcache.ReadReq_miss_rate::total 0.086470 # miss rate for ReadReq accesses
460a481
> system.cpu.dcache.WriteReq_miss_rate::total 0.332968 # miss rate for WriteReq accesses
461a483
> system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses
462a485
> system.cpu.dcache.demand_miss_rate::total 0.164641 # miss rate for demand accesses
463a487
> system.cpu.dcache.overall_miss_rate::total 0.164641 # miss rate for overall accesses
464a489
> system.cpu.dcache.ReadReq_avg_miss_latency::total 32597.058824 # average ReadReq miss latency
465a491
> system.cpu.dcache.WriteReq_avg_miss_latency::total 35671.052632 # average WriteReq miss latency
466a493
> system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 38250 # average LoadLockedReq miss latency
467a495
> system.cpu.dcache.demand_avg_miss_latency::total 34568.565401 # average overall miss latency
468a497
> system.cpu.dcache.overall_avg_miss_latency::total 34568.565401 # average overall miss latency
503a533
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054425 # mshr miss rate for ReadReq accesses
504a535
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses
505a537
> system.cpu.dcache.demand_mshr_miss_rate::total 0.051754 # mshr miss rate for demand accesses
506a539
> system.cpu.dcache.overall_mshr_miss_rate::total 0.051754 # mshr miss rate for overall accesses
507a541
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 29831.775701 # average ReadReq mshr miss latency
508a543
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 35750 # average WriteReq mshr miss latency
509a545
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
510a547
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 31500 # average overall mshr miss latency
566a604
> system.cpu.l2cache.ReadReq_miss_rate::total 0.900744 # miss rate for ReadReq accesses
567a606
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
569a609
> system.cpu.l2cache.demand_miss_rate::total 0.910112 # miss rate for demand accesses
571a612
> system.cpu.l2cache.overall_miss_rate::total 0.910112 # miss rate for overall accesses
573a615
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34365.013774 # average ReadReq miss latency
574a617
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34440.476190 # average ReadExReq miss latency
576a620
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.839506 # average overall miss latency
578a623
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.839506 # average overall miss latency
616a662
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.890819 # mshr miss rate for ReadReq accesses
617a664
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
619a667
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.901124 # mshr miss rate for demand accesses
621a670
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.901124 # mshr miss rate for overall accesses
623a673
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31204.735376 # average ReadReq mshr miss latency
624a675
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31309.523810 # average ReadExReq mshr miss latency
626a678
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency
628a681
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31215.710723 # average overall mshr miss latency