7,11c7,11
< host_inst_rate 10367 # Simulator instruction rate (inst/s)
< host_op_rate 12141 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 45828431 # Simulator tick rate (ticks/s)
< host_mem_usage 248616 # Number of bytes of host memory used
< host_seconds 0.44 # Real time elapsed on the host
---
> host_inst_rate 93691 # Simulator instruction rate (inst/s)
> host_op_rate 109699 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 414022055 # Simulator tick rate (ticks/s)
> host_mem_usage 265936 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
208,209c208,209
< system.physmem.totQLat 6124000 # Total ticks spent queuing
< system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6135000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM
211c211
< system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst
213c213
< system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst
235c235
< system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ)
237c237
< system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ)
242c242
< system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank
247,248c247,248
< system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states
254c254
< system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ)
256c256
< system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ)
270,273c270,273
< system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 449 # Number of BTB hits
---
> system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 446 # Number of BTB hits
275c275
< system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage
408,409c408,409
< system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed
411,414c411,414
< system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416,421c416,421
< system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total)
423,426c423,426
< system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total)
430c430
< system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total)
432,433c432,433
< system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle
---
> system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle
435c435
< system.cpu.decode.RunCycles 5174 # Number of cycles decode is running
---
> system.cpu.decode.RunCycles 5171 # Number of cycles decode is running
437,438c437,438
< system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch
---
> system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch
440c440
< system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode
442,443c442,443
< system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle
---
> system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle
446c446
< system.cpu.rename.RunCycles 4185 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 4182 # Number of cycles rename is running
448,449c448,449
< system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename
454,455c454,455
< system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made
---
> system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made
459c459
< system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing
463,464c463,464
< system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit.
469,470c469,470
< system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued
---
> system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued
472c472
< system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph
474,476c474,476
< system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle
478,479c478,479
< system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle
481c481
< system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle
490c490
< system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle
492,523c492,523
< system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available
530,562c530,562
< system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued
567,568c567,568
< system.cpu.iq.FU_type_0::total 7222 # Type of FU issued
< system.cpu.iq.rate 0.177860 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 7227 # Type of FU issued
> system.cpu.iq.rate 0.177983 # Inst issue rate
570,571c570,571
< system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads
573c573
< system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses
577c577
< system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses
581c581
< system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
584c584
< system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed
590c590
< system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing
595,596c595,596
< system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions
602,606c602,606
< system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
609,610c609,610
< system.cpu.iew.exec_refs 2442 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1297 # Number of branches executed
---
> system.cpu.iew.exec_refs 2443 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1299 # Number of branches executed
612,618c612,618
< system.cpu.iew.exec_rate 0.167836 # Inst execution rate
< system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6631 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2981 # num instructions producing a value
< system.cpu.iew.wb_consumers 5426 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back
---
> system.cpu.iew.exec_rate 0.168033 # Inst execution rate
> system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6639 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2983 # num instructions producing a value
> system.cpu.iew.wb_consumers 5430 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back
621,624c621,624
< system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle
626,627c626,627
< system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle
630c630
< system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle
638c638
< system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle
689,692c689,692
< system.cpu.rob.rob_reads 23226 # The number of ROB reads
< system.cpu.rob.rob_writes 16730 # The number of ROB writes
< system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 23224 # The number of ROB reads
> system.cpu.rob.rob_writes 16731 # The number of ROB writes
> system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling
699,700c699,700
< system.cpu.int_regfile_reads 6765 # number of integer regfile reads
< system.cpu.int_regfile_writes 3787 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 6850 # number of integer regfile reads
> system.cpu.int_regfile_writes 3795 # number of integer regfile writes
702,704c702,704
< system.cpu.cc_regfile_reads 24202 # number of cc regfile reads
< system.cpu.cc_regfile_writes 2924 # number of cc regfile writes
< system.cpu.misc_regfile_reads 2558 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
> system.cpu.cc_regfile_writes 2927 # number of cc regfile writes
> system.cpu.misc_regfile_reads 2559 # number of misc regfile reads
708,709c708,709
< system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks.
711c711
< system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks.
713,715c713,715
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy
723,724c723,724
< system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits
731,736c731,736
< system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits
< system.cpu.dcache.overall_hits::total 1906 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits
> system.cpu.dcache.overall_hits::total 1903 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
741,746c741,746
< system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
< system.cpu.dcache.overall_misses::total 358 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses
> system.cpu.dcache.overall_misses::total 361 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles
751,754c751,754
< system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles
767,768c767,768
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses
773,778c773,778
< system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency
783,786c783,786
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency
795,796c795,796
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
801,804c801,804
< system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits
813,814c813,814
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles
817,820c817,820
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles
829,830c829,830
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency
833,836c833,836
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
839,840c839,840
< system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks.
842c842
< system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks.
844,846c844,846
< system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy
851,852c851,852
< system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8095 # Number of data accesses
854,889c854,889
< system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits
< system.cpu.icache.overall_hits::total 3536 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
< system.cpu.icache.overall_misses::total 365 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency
---
> system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits
> system.cpu.icache.overall_hits::total 3532 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
> system.cpu.icache.overall_misses::total 366 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency
898,903c898,903
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
910,927c910,927
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
937c937
< system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use
942,944c942,944
< system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy
946c946
< system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy
984,993c984,993
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles
1022,1031c1022,1031
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency
1067,1075c1067,1075
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles
1077c1077
< system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles
1097,1105c1097,1105
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
1107c1107
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency
1176c1176
< system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks)
< host_inst_rate 10367 # Simulator instruction rate (inst/s)
< host_op_rate 12141 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 45828431 # Simulator tick rate (ticks/s)
< host_mem_usage 248616 # Number of bytes of host memory used
< host_seconds 0.44 # Real time elapsed on the host
---
> host_inst_rate 93691 # Simulator instruction rate (inst/s)
> host_op_rate 109699 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 414022055 # Simulator tick rate (ticks/s)
> host_mem_usage 265936 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
208,209c208,209
< system.physmem.totQLat 6124000 # Total ticks spent queuing
< system.physmem.totMemAccLat 14467750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 6135000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14478750 # Total ticks spent from burst creation until serviced by the DRAM
211c211
< system.physmem.avgQLat 13761.80 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 13786.52 # Average queueing delay per DRAM burst
213c213
< system.physmem.avgMemAccLat 32511.80 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 32536.52 # Average memory access latency per DRAM burst
235c235
< system.physmem_0.actBackEnergy 3561360 # Energy for active background per rank (pJ)
---
> system.physmem_0.actBackEnergy 3562500 # Energy for active background per rank (pJ)
237c237
< system.physmem_0.actPowerDownEnergy 5661240 # Energy for active power-down per rank (pJ)
---
> system.physmem_0.actPowerDownEnergy 5660100 # Energy for active power-down per rank (pJ)
242c242
< system.physmem_0.totalIdleTime 12272000 # Total Idle time Per DRAM Rank
---
> system.physmem_0.totalIdleTime 12261000 # Total Idle time Per DRAM Rank
247,248c247,248
< system.physmem_0.memoryStateTime::ACT 7340250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 12420250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 7351250 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 12409250 # Time in different power states
254c254
< system.physmem_1.actBackEnergy 1479720 # Energy for active background per rank (pJ)
---
> system.physmem_1.actBackEnergy 1478010 # Energy for active background per rank (pJ)
256c256
< system.physmem_1.actPowerDownEnergy 7413420 # Energy for active power-down per rank (pJ)
---
> system.physmem_1.actPowerDownEnergy 7415130 # Energy for active power-down per rank (pJ)
270,273c270,273
< system.cpu.branchPred.condPredicted 1442 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 522 # Number of conditional branches incorrect
< system.cpu.branchPred.BTBLookups 915 # Number of BTB lookups
< system.cpu.branchPred.BTBHits 449 # Number of BTB hits
---
> system.cpu.branchPred.condPredicted 1441 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 523 # Number of conditional branches incorrect
> system.cpu.branchPred.BTBLookups 913 # Number of BTB lookups
> system.cpu.branchPred.BTBHits 446 # Number of BTB hits
275c275
< system.cpu.branchPred.BTBHitPct 49.071038 # BTB Hit Percentage
---
> system.cpu.branchPred.BTBHitPct 48.849945 # BTB Hit Percentage
408,409c408,409
< system.cpu.fetch.icacheStallCycles 6160 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 11461 # Number of instructions fetch has processed
---
> system.cpu.fetch.icacheStallCycles 6162 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 11460 # Number of instructions fetch has processed
411,414c411,414
< system.cpu.fetch.predictedBranches 748 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 8317 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 1087 # Number of cycles fetch has spent squashing
< system.cpu.fetch.MiscStallCycles 162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
---
> system.cpu.fetch.predictedBranches 745 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 8314 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 1089 # Number of cycles fetch has spent squashing
> system.cpu.fetch.MiscStallCycles 142 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
416,421c416,421
< system.cpu.fetch.IcacheWaitRetryStallCycles 447 # Number of stall cycles due to full MSHR
< system.cpu.fetch.CacheLines 3903 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 179 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 15915 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.856236 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 1.206395 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.IcacheWaitRetryStallCycles 466 # Number of stall cycles due to full MSHR
> system.cpu.fetch.CacheLines 3900 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 180 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 15914 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856227 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 1.206589 # Number of instructions fetched each cycle (Total)
423,426c423,426
< system.cpu.fetch.rateDist::0 9529 59.87% 59.87% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 2505 15.74% 75.61% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 521 3.27% 78.89% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 3360 21.11% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 9531 59.89% 59.89% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 2501 15.72% 75.61% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 521 3.27% 78.88% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 3361 21.12% 100.00% # Number of instructions fetched each cycle (Total)
430c430
< system.cpu.fetch.rateDist::total 15915 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15914 # Number of instructions fetched each cycle (Total)
432,433c432,433
< system.cpu.fetch.rate 0.282256 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 5815 # Number of cycles decode is idle
---
> system.cpu.fetch.rate 0.282231 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 5816 # Number of cycles decode is idle
435c435
< system.cpu.decode.RunCycles 5174 # Number of cycles decode is running
---
> system.cpu.decode.RunCycles 5171 # Number of cycles decode is running
437,438c437,438
< system.cpu.decode.SquashCycles 384 # Number of cycles decode is squashing
< system.cpu.decode.BranchResolved 374 # Number of times decode resolved a branch
---
> system.cpu.decode.SquashCycles 385 # Number of cycles decode is squashing
> system.cpu.decode.BranchResolved 538 # Number of times decode resolved a branch
440c440
< system.cpu.decode.DecodedInsts 10174 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 10171 # Number of instructions handled by decode
442,443c442,443
< system.cpu.rename.SquashCycles 384 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 6926 # Number of cycles rename is idle
---
> system.cpu.rename.SquashCycles 385 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 6927 # Number of cycles rename is idle
446c446
< system.cpu.rename.RunCycles 4185 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 4182 # Number of cycles rename is running
448,449c448,449
< system.cpu.rename.RenamedInsts 9093 # Number of instructions processed by rename
< system.cpu.rename.SquashedInsts 464 # Number of squashed instructions processed by rename
---
> system.cpu.rename.RenamedInsts 9091 # Number of instructions processed by rename
> system.cpu.rename.SquashedInsts 462 # Number of squashed instructions processed by rename
454,455c454,455
< system.cpu.rename.RenamedOperands 9451 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 41117 # Number of register rename lookups that rename has made
---
> system.cpu.rename.RenamedOperands 9449 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 41113 # Number of register rename lookups that rename has made
459c459
< system.cpu.rename.UndoneMaps 3957 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3955 # Number of HB maps that are undone due to squashing
463,464c463,464
< system.cpu.memDep0.insertedLoads 1821 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1286 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 1823 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1287 # Number of stores inserted to the mem dependence unit.
469,470c469,470
< system.cpu.iq.iqInstsIssued 7222 # Number of instructions issued
< system.cpu.iq.iqSquashedInstsIssued 185 # Number of squashed instructions issued
---
> system.cpu.iq.iqInstsIssued 7227 # Number of instructions issued
> system.cpu.iq.iqSquashedInstsIssued 183 # Number of squashed instructions issued
472c472
< system.cpu.iq.iqSquashedOperandsExamined 8232 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedOperandsExamined 8218 # Number of squashed operands that are examined and possibly removed from graph
474,476c474,476
< system.cpu.iq.issued_per_cycle::samples 15915 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.453786 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 0.844098 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15914 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.454128 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 0.844358 # Number of insts issued each cycle
478,479c478,479
< system.cpu.iq.issued_per_cycle::0 11657 73.25% 73.25% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1985 12.47% 85.72% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% # Number of insts issued each cycle
481c481
< system.cpu.iq.issued_per_cycle::3 607 3.81% 99.74% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% # Number of insts issued each cycle
490c490
< system.cpu.iq.issued_per_cycle::total 15915 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15914 # Number of insts issued each cycle
492,523c492,523
< system.cpu.iq.fu_full::IntAlu 415 28.86% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.86% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 468 32.55% 61.40% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% # attempts to use FU when none available
530,562c530,562
< system.cpu.iq.FU_type_0::IntAlu 4533 62.77% 62.77% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.84% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.88% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 1600 22.15% 85.03% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1065 14.75% 99.78% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% # Type of FU issued
567,568c567,568
< system.cpu.iq.FU_type_0::total 7222 # Type of FU issued
< system.cpu.iq.rate 0.177860 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 7227 # Type of FU issued
> system.cpu.iq.rate 0.177983 # Inst issue rate
570,571c570,571
< system.cpu.iq.fu_busy_rate 0.199114 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 31933 # Number of integer instruction queue reads
---
> system.cpu.iq.fu_busy_rate 0.198976 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31940 # Number of integer instruction queue reads
573c573
< system.cpu.iq.int_inst_queue_wakeup_accesses 6615 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.int_inst_queue_wakeup_accesses 6623 # Number of integer instruction queue wakeup accesses
577c577
< system.cpu.iq.int_alu_accesses 8627 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8632 # Number of integer alu accesses
581c581
< system.cpu.iew.lsq.thread0.squashedLoads 794 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 796 # Number of loads squashed
584c584
< system.cpu.iew.lsq.thread0.squashedStores 348 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 349 # Number of stores squashed
590c590
< system.cpu.iew.iewSquashCycles 384 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 385 # Number of cycles IEW is squashing
595,596c595,596
< system.cpu.iew.iewDispLoadInsts 1821 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1286 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 1823 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1287 # Number of dispatched store instructions
602,606c602,606
< system.cpu.iew.predictedNotTakenIncorrect 318 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 378 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 6815 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 1418 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 407 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedNotTakenIncorrect 320 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 6823 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 1419 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 404 # Number of squashed instructions skipped in execute
609,610c609,610
< system.cpu.iew.exec_refs 2442 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1297 # Number of branches executed
---
> system.cpu.iew.exec_refs 2443 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1299 # Number of branches executed
612,618c612,618
< system.cpu.iew.exec_rate 0.167836 # Inst execution rate
< system.cpu.iew.wb_sent 6675 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 6631 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2981 # num instructions producing a value
< system.cpu.iew.wb_consumers 5426 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.163305 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.549392 # average fanout of values written-back
---
> system.cpu.iew.exec_rate 0.168033 # Inst execution rate
> system.cpu.iew.wb_sent 6684 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 6639 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2983 # num instructions producing a value
> system.cpu.iew.wb_consumers 5430 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.163502 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.549355 # average fanout of values written-back
621,624c621,624
< system.cpu.commit.branchMispredicts 363 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 15348 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.350404 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 0.989339 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 364 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 15346 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.350450 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 0.989791 # Number of insts commited each cycle
626,627c626,627
< system.cpu.commit.committed_per_cycle::0 12680 82.62% 82.62% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 1404 9.15% 91.76% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% # Number of insts commited each cycle
630c630
< system.cpu.commit.committed_per_cycle::4 164 1.07% 98.72% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% # Number of insts commited each cycle
638c638
< system.cpu.commit.committed_per_cycle::total 15348 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 15346 # Number of insts commited each cycle
689,692c689,692
< system.cpu.rob.rob_reads 23226 # The number of ROB reads
< system.cpu.rob.rob_writes 16730 # The number of ROB writes
< system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 24690 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 23224 # The number of ROB reads
> system.cpu.rob.rob_writes 16731 # The number of ROB writes
> system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 24691 # Total number of cycles that the CPU has spent unscheduled due to idling
699,700c699,700
< system.cpu.int_regfile_reads 6765 # number of integer regfile reads
< system.cpu.int_regfile_writes 3787 # number of integer regfile writes
---
> system.cpu.int_regfile_reads 6850 # number of integer regfile reads
> system.cpu.int_regfile_writes 3795 # number of integer regfile writes
702,704c702,704
< system.cpu.cc_regfile_reads 24202 # number of cc regfile reads
< system.cpu.cc_regfile_writes 2924 # number of cc regfile writes
< system.cpu.misc_regfile_reads 2558 # number of misc regfile reads
---
> system.cpu.cc_regfile_reads 24229 # number of cc regfile reads
> system.cpu.cc_regfile_writes 2927 # number of cc regfile writes
> system.cpu.misc_regfile_reads 2559 # number of misc regfile reads
708,709c708,709
< system.cpu.dcache.tags.tagsinuse 84.060908 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1926 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 84.085192 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1923 # Total number of references to valid blocks.
711c711
< system.cpu.dcache.tags.avg_refs 13.468531 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 13.447552 # Average number of references to valid blocks.
713,715c713,715
< system.cpu.dcache.tags.occ_blocks::cpu.data 84.060908 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.164181 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.164181 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.164229 # Average percentage of cache occupancy
723,724c723,724
< system.cpu.dcache.ReadReq_hits::cpu.data 1184 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1184 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1181 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1181 # number of ReadReq hits
731,736c731,736
< system.cpu.dcache.demand_hits::cpu.data 1906 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1906 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1906 # number of overall hits
< system.cpu.dcache.overall_hits::total 1906 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses
---
> system.cpu.dcache.demand_hits::cpu.data 1903 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1903 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1903 # number of overall hits
> system.cpu.dcache.overall_hits::total 1903 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 170 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 170 # number of ReadReq misses
741,746c741,746
< system.cpu.dcache.demand_misses::cpu.data 358 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 358 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 358 # number of overall misses
< system.cpu.dcache.overall_misses::total 358 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12046500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12046500 # number of ReadReq miss cycles
---
> system.cpu.dcache.demand_misses::cpu.data 361 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 361 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 361 # number of overall misses
> system.cpu.dcache.overall_misses::total 361 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12060000 # number of ReadReq miss cycles
751,754c751,754
< system.cpu.dcache.demand_miss_latency::cpu.data 20063000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 20063000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 20063000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 20063000 # number of overall miss cycles
---
> system.cpu.dcache.demand_miss_latency::cpu.data 20076500 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 20076500 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 20076500 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 20076500 # number of overall miss cycles
767,768c767,768
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123612 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.123612 # miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.125833 # miss rate for ReadReq accesses
773,778c773,778
< system.cpu.dcache.demand_miss_rate::cpu.data 0.158127 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.158127 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.158127 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.158127 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72134.730539 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 72134.730539 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.159452 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.159452 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 # average ReadReq miss latency
783,786c783,786
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 56041.899441 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 56041.899441 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 56041.899441 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 # average overall miss latency
795,796c795,796
< system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
< system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits
---
> system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 # number of ReadReq MSHR hits
> system.cpu.dcache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
801,804c801,804
< system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits
---
> system.cpu.dcache.demand_mshr_hits::cpu.data 217 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 217 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 217 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 217 # number of overall MSHR hits
813,814c813,814
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7999500 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7999500 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7989500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7989500 # number of ReadReq MSHR miss cycles
817,820c817,820
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 10594000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10594000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 10594000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10584000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10584000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10584000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10584000 # number of overall MSHR miss cycles
829,830c829,830
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77665.048544 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77665.048544 # average ReadReq mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77567.961165 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77567.961165 # average ReadReq mshr miss latency
833,836c833,836
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73569.444444 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 73569.444444 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 73500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 73500 # average overall mshr miss latency
839,840c839,840
< system.cpu.icache.tags.tagsinuse 137.464664 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 3536 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 137.523624 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 3532 # Total number of references to valid blocks.
842c842
< system.cpu.icache.tags.avg_refs 11.826087 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 11.812709 # Average number of references to valid blocks.
844,846c844,846
< system.cpu.icache.tags.occ_blocks::cpu.inst 137.464664 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.268486 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.268486 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 137.523624 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.268601 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.268601 # Average percentage of cache occupancy
851,852c851,852
< system.cpu.icache.tags.tag_accesses 8101 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 8101 # Number of data accesses
---
> system.cpu.icache.tags.tag_accesses 8095 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 8095 # Number of data accesses
854,889c854,889
< system.cpu.icache.ReadReq_hits::cpu.inst 3536 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 3536 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 3536 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 3536 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 3536 # number of overall hits
< system.cpu.icache.overall_hits::total 3536 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses
< system.cpu.icache.overall_misses::total 365 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 25043490 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 25043490 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 25043490 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 25043490 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 25043490 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 25043490 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 3901 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 3901 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 3901 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 3901 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 3901 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 3901 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093566 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.093566 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.093566 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.093566 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.093566 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.093566 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68612.301370 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 68612.301370 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 68612.301370 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 68612.301370 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 68612.301370 # average overall miss latency
---
> system.cpu.icache.ReadReq_hits::cpu.inst 3532 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 3532 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 3532 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 3532 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 3532 # number of overall hits
> system.cpu.icache.overall_hits::total 3532 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
> system.cpu.icache.overall_misses::total 366 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 25091490 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 25091490 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 25091490 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 25091490 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 25091490 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 25091490 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 3898 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 3898 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 3898 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 3898 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 3898 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 3898 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.093894 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.093894 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.093894 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.093894 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.093894 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.093894 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68555.983607 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 68555.983607 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 68555.983607 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 68555.983607 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 68555.983607 # average overall miss latency
898,903c898,903
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 66 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 66 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 66 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 66 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 66 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits
910,927c910,927
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22004990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 22004990 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22004990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 22004990 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22004990 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 22004990 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076647 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.076647 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076647 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.076647 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73595.284281 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73595.284281 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73595.284281 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 73595.284281 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22025990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 22025990 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22025990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 22025990 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22025990 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 22025990 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.076706 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.076706 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.076706 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.076706 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73665.518395 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73665.518395 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73665.518395 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 73665.518395 # average overall mshr miss latency
937c937
< system.cpu.l2cache.tags.tagsinuse 17.355508 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 17.362749 # Cycle average of tags in use
942,944c942,944
< system.cpu.l2cache.tags.occ_blocks::writebacks 9.226998 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.128510 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::writebacks 0.000563 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::writebacks 9.237342 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 8.125407 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::writebacks 0.000564 # Average percentage of cache occupancy
946c946
< system.cpu.l2cache.tags.occ_percent::total 0.001059 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.001060 # Average percentage of cache occupancy
984,993c984,993
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21645500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 21645500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7838000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7838000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 21645500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10298000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 31943500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 21645500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10298000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 31943500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 21666500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 21666500 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7828000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7828000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 21666500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10288000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 31954500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 21666500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10288000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 31954500 # number of overall miss cycles
1022,1031c1022,1031
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74383.161512 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74383.161512 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76097.087379 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76097.087379 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 75338.443396 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74383.161512 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77428.571429 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 75338.443396 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 74455.326460 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 74455.326460 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 76000 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 76000 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 75364.386792 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74455.326460 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77353.383459 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 75364.386792 # average overall miss latency
1067,1075c1067,1075
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19843000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19843000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6922500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6922500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19843000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9202500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29045500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19843000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9202500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 19864000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 19864000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6912500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6912500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19864000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9192500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29056500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19864000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9192500 # number of overall MSHR miss cycles
1077c1077
< system.cpu.l2cache.overall_mshr_miss_latency::total 30812426 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.overall_mshr_miss_latency::total 30823426 # number of overall MSHR miss cycles
1097,1105c1097,1105
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68424.137931 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68424.137931 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70637.755102 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70637.755102 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69486.842105 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68424.137931 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71894.531250 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 68496.551724 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 68496.551724 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 70535.714286 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 70535.714286 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69513.157895 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 68496.551724 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71816.406250 # average overall mshr miss latency
1107c1107
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65419.163482 # average overall mshr miss latency
---
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65442.518047 # average overall mshr miss latency
1176c1176
< system.membus.respLayer1.occupancy 2338000 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 2338250 # Layer occupancy (ticks)